[SPIRV] Support for the extension SPV_INTEL_fpga_argument_interfaces

[aadeshps-mcw]

--Added support for the extension SPV_INTEL_fpga_argument_interfaces
--Added test files for the extension SPV_INTEL_fpga_argument_interfaces

[github-actions]

Thank you for submitting a Pull Request (PR) to the LLVM Project!

This PR will be automatically labeled and the relevant teams will be notified.

If you wish to, you can add reviewers by using the "Reviewers" section on this page.

If this is not working for you, it is probably because you do not have write permissions for the repository. In which case you can instead tag reviewers by name in a comment by using @ followed by their GitHub username.

If you have received no comments on your PR for a week, you can request a review by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate is once a week. Please remember that you are asking for valuable time from other developers.

If you have further questions, they may be answered by the LLVM GitHub User Guide.

You can also ask questions in a comment on this PR, on the LLVM Discord or on the forums.

[llvmbot]

@llvm/pr-subscribers-backend-spir-v

Author: Aadesh Premkumar (aadeshps-mcw)

Changes

--Added support for the extension SPV_INTEL_fpga_argument_interfaces
--Added test files for the extension SPV_INTEL_fpga_argument_interfaces

---

Full diff: https://github.com/llvm/llvm-project/pull/140231.diff

6 Files Affected:

• (modified) llvm/docs/SPIRVUsage.rst (+2)
• (modified) llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp (+18-4)
• (modified) llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp (+3-1)
• (modified) llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp (+11)
• (modified) llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td (+10)
• (added) llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fpga_argument_interfaces/sycl-kernel-arg-annotation.ll (+42)

diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index 6ff8034cac00c..5dd294a435009 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -213,6 +213,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
      - Adds a bitwise instruction on three operands and a look-up table index for specifying the bitwise operation to perform. 
    * - ``SPV_INTEL_subgroup_matrix_multiply_accumulate``
      - Adds an instruction to compute the matrix product of an M x K matrix with a K x N matrix and then add an M x N matrix. 
+   * - ``SPV_INTEL_fpga_argument_interfaces``
+     - Adds kernel argument decorations that influence the interfaces built for for Field Programmable Gate Array (FPGA) kernel arguments.
 
 To enable multiple extensions, list them separated by comma. For example, to enable support for atomic operations on floating-point numbers and arbitrary precision integers, use:
 
diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
index 5991a9af6364d..df70b28c4d965 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
@@ -283,6 +283,18 @@ getExecutionModel(const SPIRVSubtarget &STI, const Function &F) {
   report_fatal_error("This HLSL entry point is not supported by this backend.");
 }
 
+static bool shouldSkipOperands(SPIRV::Decoration::Decoration Dec) {
+  switch (Dec) {
+  case SPIRV::Decoration::StableKernelArgumentINTEL:
+  case SPIRV::Decoration::RegisterMapKernelArgumentINTEL:
+  case SPIRV::Decoration::ConduitKernelArgumentINTEL:
+  case SPIRV::Decoration::Restrict:
+    return true;
+  default:
+    return false;
+  }
+}
+
 bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
                                              const Function &F,
                                              ArrayRef<ArrayRef<Register>> VRegs,
@@ -375,10 +387,12 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
           auto Dec =
               static_cast<SPIRV::Decoration::Decoration>(Const->getZExtValue());
           std::vector<uint32_t> DecVec;
-          for (unsigned j = 1; j < MD2->getNumOperands(); j++) {
-            ConstantInt *Const = getConstInt(MD2, j);
-            assert(Const && "MDOperand should be ConstantInt");
-            DecVec.push_back(static_cast<uint32_t>(Const->getZExtValue()));
+          if (!shouldSkipOperands(Dec)) {
+            for (unsigned j = 1; j < MD2->getNumOperands(); j++) {
+              ConstantInt *Const = getConstInt(MD2, j);
+              assert(Const && "MDOperand should be ConstantInt");
+              DecVec.push_back(static_cast<uint32_t>(Const->getZExtValue()));
+            }
           }
           buildOpDecorate(VRegs[i][0], MIRBuilder, Dec, DecVec);
         }
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 56cbd9414c9ee..8350673092d8a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -97,7 +97,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
          SPIRV::Extension::Extension::
              SPV_INTEL_subgroup_matrix_multiply_accumulate},
         {"SPV_INTEL_ternary_bitwise_function",
-         SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function}};
+         SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function},
+        {"SPV_INTEL_fpga_argument_interfaces",
+         SPIRV::Extension::Extension::SPV_INTEL_fpga_argument_interfaces}};
 
 bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
                                   StringRef ArgValue,
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index 6d2ecd563d200..f8d806c7406f4 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -920,6 +920,17 @@ static void addOpDecorateReqs(const MachineInstr &MI, unsigned DecIndex,
   } else if (Dec == SPIRV::Decoration::FPMaxErrorDecorationINTEL) {
     Reqs.addRequirements(SPIRV::Capability::FPMaxErrorINTEL);
     Reqs.addExtension(SPIRV::Extension::SPV_INTEL_fp_max_error);
+  } else if (Dec == SPIRV::Decoration::ConduitKernelArgumentINTEL ||
+             Dec == SPIRV::Decoration::RegisterMapKernelArgumentINTEL ||
+             Dec == SPIRV::Decoration::MMHostInterfaceAddressWidthINTEL ||
+             Dec == SPIRV::Decoration::MMHostInterfaceDataWidthINTEL ||
+             Dec == SPIRV::Decoration::MMHostInterfaceLatencyINTEL ||
+             Dec == SPIRV::Decoration::MMHostInterfaceReadWriteModeINTEL ||
+             Dec == SPIRV::Decoration::MMHostInterfaceMaxBurstINTEL ||
+             Dec == SPIRV::Decoration::MMHostInterfaceWaitRequestINTEL ||
+             Dec == SPIRV::Decoration::StableKernelArgumentINTEL) {
+    Reqs.addRequirements(SPIRV::Capability::FPGAArgumentInterfacesINTEL);
+    Reqs.addExtension(SPIRV::Extension::SPV_INTEL_fpga_argument_interfaces);
   }
 }
 
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index cc32200a0a261..8a470f7352a10 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -517,6 +517,7 @@ defm MemoryAccessAliasingINTEL : CapabilityOperand<5910, 0, 0, [SPV_INTEL_memory
 defm FPMaxErrorINTEL : CapabilityOperand<6169, 0, 0, [SPV_INTEL_fp_max_error], []>;
 defm TernaryBitwiseFunctionINTEL : CapabilityOperand<6241, 0, 0, [SPV_INTEL_ternary_bitwise_function], []>;
 defm SubgroupMatrixMultiplyAccumulateINTEL : CapabilityOperand<6236, 0, 0, [SPV_INTEL_subgroup_matrix_multiply_accumulate], []>;
+defm FPGAArgumentInterfacesINTEL : CapabilityOperand<6174, 0, 0, [SPV_INTEL_fpga_argument_interfaces], []>;
 
 //===----------------------------------------------------------------------===//
 // Multiclass used to define SourceLanguage enum values and at the same time
@@ -1268,6 +1269,15 @@ defm FunctionFloatingPointModeINTEL : DecorationOperand<6080, 0, 0, [], [Functio
 defm AliasScopeINTEL : DecorationOperand<5914, 0, 0, [], [MemoryAccessAliasingINTEL]>;
 defm NoAliasINTEL : DecorationOperand<5915, 0, 0, [], [MemoryAccessAliasingINTEL]>;
 defm FPMaxErrorDecorationINTEL : DecorationOperand<6170, 0, 0, [], [FPMaxErrorINTEL]>;
+defm ConduitKernelArgumentINTEL : DecorationOperand<6175, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm RegisterMapKernelArgumentINTEL: DecorationOperand<6176, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm MMHostInterfaceAddressWidthINTEL: DecorationOperand<6177, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm MMHostInterfaceDataWidthINTEL: DecorationOperand<6178, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm MMHostInterfaceLatencyINTEL: DecorationOperand<6179, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm MMHostInterfaceReadWriteModeINTEL: DecorationOperand<6180, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm MMHostInterfaceMaxBurstINTEL: DecorationOperand<6181, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm MMHostInterfaceWaitRequestINTEL: DecorationOperand<6182, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
+defm StableKernelArgumentINTEL: DecorationOperand<6183, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
 
 //===----------------------------------------------------------------------===//
 // Multiclass used to define BuiltIn enum values and at the same time
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fpga_argument_interfaces/sycl-kernel-arg-annotation.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fpga_argument_interfaces/sycl-kernel-arg-annotation.ll
new file mode 100644
index 0000000000000..c052d4c63dcf4
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fpga_argument_interfaces/sycl-kernel-arg-annotation.ll
@@ -0,0 +1,42 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_fpga_argument_interfaces %s -o - | FileCheck %s
+; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; CHECK: OpCapability FPGAArgumentInterfacesINTEL
+; CHECK: OpExtension "SPV_INTEL_fpga_argument_interfaces"
+; CHECK: OpName %[[ID:[0-9]+]] "_arg_p"
+; CHECK: OpDecorate %[[ID]] Alignment 4
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceAddressWidthINTEL 32
+; CHECK: OpDecorate %[[ID]] ConduitKernelArgumentINTEL
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceDataWidthINTEL 64
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceLatencyINTEL 1
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceMaxBurstINTEL 3
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceReadWriteModeINTEL 2
+; CHECK: OpDecorate %[[ID]] RegisterMapKernelArgumentINTEL
+; CHECK: OpDecorate %[[ID]] StableKernelArgumentINTEL
+; CHECK: OpDecorate %[[ID]] Restrict
+; CHECK: OpDecorate %[[ID]] MMHostInterfaceWaitRequestINTEL 5
+
+$_ZTS4MyIP = comdat any
+
+; Function Attrs: convergent mustprogress norecurse
+define weak_odr dso_local spir_kernel void @_ZTS4MyIP(ptr addrspace(4) noundef %_arg_p) #0 comdat !spirv.ParameterDecorations !1588
+; CHECK-LLVM-DAG:  !spirv.ParameterDecorations ![[PARMDECOR:[0-9]+]]
+{
+entry:
+		ret void
+}
+
+!1587 = !{i32 -1}
+!1588 = !{!1589}
+!1589 = !{!1590, !1591, !1593, !1594, !1595, !1596, !1597, !1598, !1599, !1600, !1601}
+!1590 = !{i32 44, i32 4}
+!1591 = !{i32 6177, i32 32}
+!1593 = !{i32 6175, i32 1}
+!1594 = !{i32 6178, i32 64}
+!1595 = !{i32 6179, i32 1}
+!1596 = !{i32 6181, i32 3}
+!1597 = !{i32 6180, i32 2}
+!1598 = !{i32 6176, i32 1}
+!1599 = !{i32 6183, i32 1}
+!1600 = !{i32 19, i32 1}
+!1601 = !{i32 6182, i32 5}