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--Added support for the extension SPV_INTEL_fpga_argument_interfaces
--Added test files for the extension SPV_INTEL_fpga_argument_interfaces
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6 files changed

+86
-5
lines changed

6 files changed

+86
-5
lines changed

‎llvm/docs/SPIRVUsage.rst

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@@ -217,6 +217,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
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- Adds an instruction to compute the matrix product of an M x K matrix with a K x N matrix and then add an M x N matrix.
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* - ``SPV_INTEL_int4``
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- Adds support for 4-bit integer type, and allow this type to be used in cooperative matrices.
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* - ``SPV_INTEL_fpga_argument_interfaces``
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- Adds kernel argument decorations that influence the interfaces built for for Field Programmable Gate Array (FPGA) kernel arguments.
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To enable multiple extensions, list them separated by comma. For example, to enable support for atomic operations on floating-point numbers and arbitrary precision integers, use:
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‎llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp

Lines changed: 18 additions & 4 deletions
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@@ -283,6 +283,18 @@ getExecutionModel(const SPIRVSubtarget &STI, const Function &F) {
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report_fatal_error("This HLSL entry point is not supported by this backend.");
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}
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static bool shouldSkipOperands(SPIRV::Decoration::Decoration Dec) {
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switch (Dec) {
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case SPIRV::Decoration::StableKernelArgumentINTEL:
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case SPIRV::Decoration::RegisterMapKernelArgumentINTEL:
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case SPIRV::Decoration::ConduitKernelArgumentINTEL:
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case SPIRV::Decoration::Restrict:
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return true;
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default:
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return false;
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}
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}
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bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs,
@@ -375,10 +387,12 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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auto Dec =
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static_cast<SPIRV::Decoration::Decoration>(Const->getZExtValue());
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std::vector<uint32_t> DecVec;
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for (unsigned j = 1; j < MD2->getNumOperands(); j++) {
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ConstantInt *Const = getConstInt(MD2, j);
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assert(Const && "MDOperand should be ConstantInt");
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DecVec.push_back(static_cast<uint32_t>(Const->getZExtValue()));
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if (!shouldSkipOperands(Dec)) {
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for (unsigned j = 1; j < MD2->getNumOperands(); j++) {
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ConstantInt *Const = getConstInt(MD2, j);
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assert(Const && "MDOperand should be ConstantInt");
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DecVec.push_back(static_cast<uint32_t>(Const->getZExtValue()));
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}
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}
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buildOpDecorate(VRegs[i][0], MIRBuilder, Dec, DecVec);
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}

‎llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
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SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function},
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{"SPV_INTEL_2d_block_io",
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SPIRV::Extension::Extension::SPV_INTEL_2d_block_io},
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{"SPV_INTEL_int4", SPIRV::Extension::Extension::SPV_INTEL_int4}};
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{"SPV_INTEL_int4", SPIRV::Extension::Extension::SPV_INTEL_int4},
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{"SPV_INTEL_fpga_argument_interfaces",
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SPIRV::Extension::Extension::SPV_INTEL_fpga_argument_interfaces}};
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bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
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StringRef ArgValue,

‎llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -920,6 +920,17 @@ static void addOpDecorateReqs(const MachineInstr &MI, unsigned DecIndex,
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} else if (Dec == SPIRV::Decoration::FPMaxErrorDecorationINTEL) {
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Reqs.addRequirements(SPIRV::Capability::FPMaxErrorINTEL);
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Reqs.addExtension(SPIRV::Extension::SPV_INTEL_fp_max_error);
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} else if (Dec == SPIRV::Decoration::ConduitKernelArgumentINTEL ||
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Dec == SPIRV::Decoration::RegisterMapKernelArgumentINTEL ||
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Dec == SPIRV::Decoration::MMHostInterfaceAddressWidthINTEL ||
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Dec == SPIRV::Decoration::MMHostInterfaceDataWidthINTEL ||
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Dec == SPIRV::Decoration::MMHostInterfaceLatencyINTEL ||
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Dec == SPIRV::Decoration::MMHostInterfaceReadWriteModeINTEL ||
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Dec == SPIRV::Decoration::MMHostInterfaceMaxBurstINTEL ||
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Dec == SPIRV::Decoration::MMHostInterfaceWaitRequestINTEL ||
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Dec == SPIRV::Decoration::StableKernelArgumentINTEL) {
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Reqs.addRequirements(SPIRV::Capability::FPGAArgumentInterfacesINTEL);
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Reqs.addExtension(SPIRV::Extension::SPV_INTEL_fpga_argument_interfaces);
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}
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}
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‎llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td

Lines changed: 10 additions & 0 deletions
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@@ -525,6 +525,7 @@ defm Subgroup2DBlockTransformINTEL : CapabilityOperand<6229, 0, 0, [SPV_INTEL_2d
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defm Subgroup2DBlockTransposeINTEL : CapabilityOperand<6230, 0, 0, [SPV_INTEL_2d_block_io], [Subgroup2DBlockIOINTEL]>;
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defm Int4TypeINTEL : CapabilityOperand<5112, 0, 0, [SPV_INTEL_int4], []>;
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defm Int4CooperativeMatrixINTEL : CapabilityOperand<5114, 0, 0, [SPV_INTEL_int4], [Int4TypeINTEL, CooperativeMatrixKHR]>;
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defm FPGAArgumentInterfacesINTEL : CapabilityOperand<6174, 0, 0, [SPV_INTEL_fpga_argument_interfaces], []>;
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529530
//===----------------------------------------------------------------------===//
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// Multiclass used to define SourceLanguage enum values and at the same time
@@ -1276,6 +1277,15 @@ defm FunctionFloatingPointModeINTEL : DecorationOperand<6080, 0, 0, [], [Functio
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defm AliasScopeINTEL : DecorationOperand<5914, 0, 0, [], [MemoryAccessAliasingINTEL]>;
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defm NoAliasINTEL : DecorationOperand<5915, 0, 0, [], [MemoryAccessAliasingINTEL]>;
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defm FPMaxErrorDecorationINTEL : DecorationOperand<6170, 0, 0, [], [FPMaxErrorINTEL]>;
1280+
defm ConduitKernelArgumentINTEL : DecorationOperand<6175, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
1281+
defm RegisterMapKernelArgumentINTEL: DecorationOperand<6176, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
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defm MMHostInterfaceAddressWidthINTEL: DecorationOperand<6177, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
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defm MMHostInterfaceDataWidthINTEL: DecorationOperand<6178, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
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defm MMHostInterfaceLatencyINTEL: DecorationOperand<6179, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
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defm MMHostInterfaceReadWriteModeINTEL: DecorationOperand<6180, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
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defm MMHostInterfaceMaxBurstINTEL: DecorationOperand<6181, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
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defm MMHostInterfaceWaitRequestINTEL: DecorationOperand<6182, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
1288+
defm StableKernelArgumentINTEL: DecorationOperand<6183, 0, 0, [], [FPGAArgumentInterfacesINTEL]>;
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12801290
//===----------------------------------------------------------------------===//
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// Multiclass used to define BuiltIn enum values and at the same time

‎llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fpga_argument_interfaces/sycl-kernel-arg-annotation.ll

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@@ -0,0 +1,42 @@
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; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_fpga_argument_interfaces %s -o - | FileCheck %s
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; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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4+
; CHECK: OpCapability FPGAArgumentInterfacesINTEL
5+
; CHECK: OpExtension "SPV_INTEL_fpga_argument_interfaces"
6+
; CHECK: OpName %[[ID:[0-9]+]] "_arg_p"
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; CHECK: OpDecorate %[[ID]] Alignment 4
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; CHECK: OpDecorate %[[ID]] MMHostInterfaceAddressWidthINTEL 32
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; CHECK: OpDecorate %[[ID]] ConduitKernelArgumentINTEL
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; CHECK: OpDecorate %[[ID]] MMHostInterfaceDataWidthINTEL 64
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; CHECK: OpDecorate %[[ID]] MMHostInterfaceLatencyINTEL 1
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; CHECK: OpDecorate %[[ID]] MMHostInterfaceMaxBurstINTEL 3
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; CHECK: OpDecorate %[[ID]] MMHostInterfaceReadWriteModeINTEL 2
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; CHECK: OpDecorate %[[ID]] RegisterMapKernelArgumentINTEL
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; CHECK: OpDecorate %[[ID]] StableKernelArgumentINTEL
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; CHECK: OpDecorate %[[ID]] Restrict
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; CHECK: OpDecorate %[[ID]] MMHostInterfaceWaitRequestINTEL 5
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$_ZTS4MyIP = comdat any
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; Function Attrs: convergent mustprogress norecurse
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define weak_odr dso_local spir_kernel void @_ZTS4MyIP(ptr addrspace(4) noundef %_arg_p) #0 comdat !spirv.ParameterDecorations !1588
23+
; CHECK-LLVM-DAG: !spirv.ParameterDecorations ![[PARMDECOR:[0-9]+]]
24+
{
25+
entry:
26+
ret void
27+
}
28+
29+
!1587 = !{i32 -1}
30+
!1588 = !{!1589}
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!1589 = !{!1590, !1591, !1593, !1594, !1595, !1596, !1597, !1598, !1599, !1600, !1601}
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!1590 = !{i32 44, i32 4}
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!1591 = !{i32 6177, i32 32}
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!1593 = !{i32 6175, i32 1}
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!1594 = !{i32 6178, i32 64}
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!1595 = !{i32 6179, i32 1}
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!1596 = !{i32 6181, i32 3}
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!1597 = !{i32 6180, i32 2}
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!1598 = !{i32 6176, i32 1}
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!1599 = !{i32 6183, i32 1}
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!1600 = !{i32 19, i32 1}
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!1601 = !{i32 6182, i32 5}

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