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[RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) isel in some cases. #102034
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…l in some cases. If x is a shl by 32 and c1 is an simm12, we would prefer to use a SRAIW+ANDI. This prevents selecting the slli to a separate slli instruction.
@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesIf x is a shl by 32 and c1 is an simm12, we would prefer to use a SRAIW+ANDI. This prevents selecting the slli to a separate slli instruction. Full diff: https://github.com/llvm/llvm-project/pull/102034.diff 2 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 3dcfeecec1e75..b140d72e36fed 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1460,7 +1460,11 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
SDValue X = N0.getOperand(0);
- if (isMask_64(C1)) {
+ // Prefer SRAIW + ANDI when possible.
+ bool Skip = C2 > 32 && IsC1ANDI && X.getOpcode() == ISD::SHL &&
+ isa<ConstantSDNode>(X.getOperand(1)) &&
+ X.getConstantOperandVal(1) == 32;
+ if (isMask_64(C1) && !Skip) {
unsigned Leading = XLen - llvm::bit_width(C1);
if (C2 > Leading) {
SDNode *SRAI = CurDAG->getMachineNode(
diff --git a/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll b/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
index 4749cc656693c..0d96fbfa81279 100644
--- a/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
+++ b/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
@@ -276,9 +276,8 @@ define i64 @sraiw_andi(i32 signext %0, i32 signext %1) nounwind {
; RV64-LABEL: sraiw_andi:
; RV64: # %bb.0: # %entry
; RV64-NEXT: add a0, a0, a1
-; RV64-NEXT: slli a0, a0, 32
-; RV64-NEXT: srai a0, a0, 2
-; RV64-NEXT: srli a0, a0, 61
+; RV64-NEXT: sraiw a0, a0, 31
+; RV64-NEXT: andi a0, a0, 7
; RV64-NEXT: ret
entry:
%3 = add i32 %0, %1
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Can you rebase this patch over cfd13cb?
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LGTM. Thank you!
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/16/builds/3026 Here is the relevant piece of the build log for the reference:
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llvm#102034 has implemented it.
llvm#102034 has implemented it.
llvm#102034 has implemented it.
If x is a shl by 32 and c1 is an simm12, we would prefer to use a SRAIW+ANDI. This prevents selecting the slli to a separate slli instruction.
Fixes regression from #101868