Skip to content

Issues: llvm/llvm-project

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Clear current search query, filters, and sorts
363 Open 3,029 Closed
363 Open 3,029 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

[RISC-V] Add SMLoc info for fixup. [NFCI] backend:RISC-V
#142054 opened May 29, 2025 by fpetrogalli Loading…
3
[RISCV][TTI] Discount slide cost if ri.vinsert/ri.vextract are available backend:RISC-V llvm:analysis
#142036 opened May 29, 2025 by preames Loading…
3
[RISC-V] Miscompile on -O[1-3] backend:RISC-V llvm:optimizations miscompilation
#142004 opened May 29, 2025 by ewlu
1
@topperc
2
[RISC-V] Adjust trampoline code for branch control flow protection backend:RISC-V
#141949 opened May 29, 2025 by jaidTw Loading…
2
[RISCV] Fix coalescing vsetvlis when AVL and vl registers are the same backend:RISC-V
#141941 opened May 29, 2025 by lukel97 Loading…
1
3
[MISched] Add templates for creating custom schedulers backend:AArch64 backend:AMDGPU backend:ARM backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 llvm:codegen
#141935 opened May 29, 2025 by wangpc-pp Loading…
8
[RISCV] VSETVLI pass crashes due to "Cannot create empty or backwards segment" error backend:RISC-V crash Prefer [crash-on-valid] or [crash-on-invalid]
#141907 opened May 29, 2025 by BeMg
1
5
[LV][RFC] Generating conditional VPBB that will be skip when the mask is inactive in VPlan. backend:RISC-V llvm:analysis llvm:transforms vectorizers
#141900 opened May 29, 2025 by ElvisWang123 Loading…
1
[RISCV] Can we teach RISCVectorPeephole to commute FMA to fold vmerge? backend:RISC-V
#141885 opened May 29, 2025 by topperc
1
Bad codegen for reversing bits in bytes without swapping bytes backend:AArch64 backend:ARM backend:RISC-V missed-optimization
#141863 opened May 28, 2025 by tom-rein
6
[RISCV] Implementation tracking for zvqdotq backend:RISC-V metabug Issue to collect references to a group of similar or related issues.
#141826 opened May 28, 2025 by preames
1 of 11 tasks
@preames
1
[Clang][FMV] Stop emitting implicit default version using target_clones. backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#141808 opened May 28, 2025 by labrinea Loading…
2
[LV] Maximum VF does not consider scaled reductions backend:RISC-V vectorizers
#141768 opened May 28, 2025 by preames
3
[RISCV] Add basic Mach-O triple support. backend:RISC-V llvm:binary-utilities mc Machine (object) code
#141682 opened May 27, 2025 by fpetrogalli Loading…
12
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible backend:RISC-V llvm:globalisel mc Machine (object) code
#141663 opened May 27, 2025 by asb Loading…
12
[CostModel] Add a DstTy to getShuffleCost backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 llvm:analysis llvm:transforms vectorizers
#141634 opened May 27, 2025 by davemgreen Loading…
5
[RISCV] Add shlcofideleg extension backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category mc Machine (object) code
#141572 opened May 27, 2025 by punkyc Loading…
11
[clang][RISCV] Handle target features correctly in CheckBuiltinFunctionCall backend:RISC-V clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#141548 opened May 27, 2025 by 4vtomat Loading…
6
[RISCV][FPEnv] Lowering of fpenv intrinsics backend:RISC-V
#141498 opened May 26, 2025 by spavloff Loading…
@spavloff
16
[RISCV][Zicfilp] Emit .note.gnu.property section for Zicfilp CFI unlabeled scheme backend:RISC-V llvm:support
#141468 opened May 26, 2025 by mylai-mtk Loading…
1
[RISCV] Implement intrinsics for XAndesVDot backend:RISC-V clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#141441 opened May 26, 2025 by tclin914 Loading…
2
[VPlan] Use VPInstruction for uniform binops. backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#141429 opened May 25, 2025 by fhahn Loading…
1
[WIP][SDAG] Add partial_reduce_sumla node backend:AArch64 backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#141267 opened May 23, 2025 by preames Loading…
6
[RISCV] Add pre-defined macro tests for Andes vendor extension. NFC. backend:RISC-V clang Clang issues not falling into any other category
#141172 opened May 23, 2025 by tclin914 Loading…
2
[RISCV] Implement base scheduling model for andes 45 series processor. backend:RISC-V
#141008 opened May 22, 2025 by tclin914 Loading…
1
ProTip! Follow long discussions with comments:>50.