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[RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) isel in some cases. #102034

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Merged
merged 3 commits into from
Aug 7, 2024
Merged

[RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) isel in some cases. #102034

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fdb760e
[RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) ise…
topperc Aug 5, 2024
8eefeb2
Merge remote-tracking branch 'origin/main' into pr/sra-regression
topperc Aug 5, 2024
c6ddc95
fixup! Rebase.
topperc Aug 5, 2024
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7 changes: 6 additions & 1 deletion llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1461,7 +1461,12 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {

SDValue X = N0.getOperand(0);

if (isMask_64(C1)) {
// Prefer SRAIW + ANDI when possible.
bool Skip = C2 > 32 && isInt<12>(N1C->getSExtValue()) &&
X.getOpcode() == ISD::SHL &&
isa<ConstantSDNode>(X.getOperand(1)) &&
X.getConstantOperandVal(1) == 32;
if (isMask_64(C1) && !Skip) {
unsigned Leading = XLen - llvm::bit_width(C1);
if (C2 > Leading) {
SDNode *SRAI = CurDAG->getMachineNode(
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5 changes: 2 additions & 3 deletions llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
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Expand Up @@ -276,9 +276,8 @@ define i64 @sraiw_andi(i32 signext %0, i32 signext %1) nounwind {
; RV64-LABEL: sraiw_andi:
; RV64: # %bb.0: # %entry
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srai a0, a0, 2
; RV64-NEXT: srli a0, a0, 61
; RV64-NEXT: sraiw a0, a0, 31
; RV64-NEXT: andi a0, a0, 7
; RV64-NEXT: ret
entry:
%3 = add i32 %0, %1
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