[RISCV] Sink hasPostISelHook = 1 for vector pseudos into the subclasses that set HasRoundModeOp. #114294
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…es that set HasRoundModeOp. I think this is NFC, but right now it does change the flag for the pseudos removed by llvm#114287. The rounding mode for those pseudos should never be DYN so the post isel hook shouldn't do anything, but it will get called.
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesI think this is NFC, but right now it does change the flag for the pseudos removed by #114287. The rounding mode for those pseudos should never be DYN so the post isel hook shouldn't do anything, but it will get called. Full diff: https://github.com/llvm/llvm-project/pull/114294.diff 1 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index d5b0fa340684b4..334b5045b4719e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1074,6 +1074,7 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
let HasVecPolicyOp = 1;
let HasRoundModeOp = 1;
let UsesVXRM = 0;
+ let hasPostISelHook = 1;
}
class VPseudoUnaryMask<VReg RetClass,
@@ -1115,6 +1116,7 @@ class VPseudoUnaryMaskRoundingMode<VReg RetClass,
let UsesMaskPolicy = 1;
let HasRoundModeOp = 1;
let UsesVXRM = 0;
+ let hasPostISelHook = 1;
}
class VPseudoUnaryMask_NoExcept<VReg RetClass,
@@ -1151,6 +1153,7 @@ class VPseudoUnaryNoMask_FRM<VReg RetClass,
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
let HasRoundModeOp = 1;
+ let hasPostISelHook = 1;
}
class VPseudoUnaryMask_FRM<VReg RetClass,
@@ -1172,6 +1175,7 @@ class VPseudoUnaryMask_FRM<VReg RetClass,
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
let HasRoundModeOp = 1;
+ let hasPostISelHook = 1;
}
class VPseudoUnaryNoMaskGPROut :
@@ -1266,6 +1270,7 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
let HasVecPolicyOp = 1;
let HasRoundModeOp = 1;
let UsesVXRM = UsesVXRM_;
+ let hasPostISelHook = !not(UsesVXRM_);
}
class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
@@ -1290,6 +1295,7 @@ class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
let UsesMaskPolicy = 1;
let HasRoundModeOp = 1;
let UsesVXRM = UsesVXRM_;
+ let hasPostISelHook = !not(UsesVXRM_);
}
// Special version of VPseudoBinaryNoMask where we pretend the first source is
@@ -1337,6 +1343,7 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
let IsTiedPseudo = 1;
let HasRoundModeOp = 1;
let UsesVXRM = 0;
+ let hasPostISelHook = 1;
}
class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
@@ -1424,6 +1431,7 @@ class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
let HasVecPolicyOp = 1;
let HasRoundModeOp = 1;
let UsesVXRM = 0;
+ let hasPostISelHook = 1;
}
// Like VPseudoBinaryMaskPolicy, but output can be V0 and there is no policy.
@@ -1494,6 +1502,7 @@ class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
let IsTiedPseudo = 1;
let HasRoundModeOp = 1;
let UsesVXRM = 0;
+ let hasPostISelHook = 1;
}
class VPseudoBinaryCarry<VReg RetClass,
@@ -1594,6 +1603,7 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
let HasSEWOp = 1;
let HasRoundModeOp = 1;
let UsesVXRM = 0;
+ let hasPostISelHook = 1;
}
class VPseudoUSSegLoadNoMask<VReg RetClass,
@@ -6455,7 +6465,7 @@ let Predicates = [HasVInstructionsAnyF] in {
//===----------------------------------------------------------------------===//
// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
//===----------------------------------------------------------------------===//
-let mayRaiseFPException = true, hasPostISelHook = 1 in {
+let mayRaiseFPException = true in {
defm PseudoVFADD : VPseudoVALU_VV_VF_RM;
defm PseudoVFSUB : VPseudoVALU_VV_VF_RM;
defm PseudoVFRSUB : VPseudoVALU_VF_RM;
@@ -6464,7 +6474,7 @@ defm PseudoVFRSUB : VPseudoVALU_VF_RM;
//===----------------------------------------------------------------------===//
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
//===----------------------------------------------------------------------===//
-let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in {
+let mayRaiseFPException = true, hasSideEffects = 0 in {
defm PseudoVFWADD : VPseudoVFWALU_VV_VF_RM;
defm PseudoVFWSUB : VPseudoVFWALU_VV_VF_RM;
defm PseudoVFWADD : VPseudoVFWALU_WV_WF_RM;
@@ -6474,7 +6484,7 @@ defm PseudoVFWSUB : VPseudoVFWALU_WV_WF_RM;
//===----------------------------------------------------------------------===//
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
//===----------------------------------------------------------------------===//
-let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in {
+let mayRaiseFPException = true, hasSideEffects = 0 in {
defm PseudoVFMUL : VPseudoVFMUL_VV_VF_RM;
defm PseudoVFDIV : VPseudoVFDIV_VV_VF_RM;
defm PseudoVFRDIV : VPseudoVFRDIV_VF_RM;
@@ -6483,14 +6493,14 @@ defm PseudoVFRDIV : VPseudoVFRDIV_VF_RM;
//===----------------------------------------------------------------------===//
// 13.5. Vector Widening Floating-Point Multiply
//===----------------------------------------------------------------------===//
-let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in {
+let mayRaiseFPException = true, hasSideEffects = 0 in {
defm PseudoVFWMUL : VPseudoVWMUL_VV_VF_RM;
}
//===----------------------------------------------------------------------===//
// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
//===----------------------------------------------------------------------===//
-let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in {
+let mayRaiseFPException = true, hasSideEffects = 0 in {
defm PseudoVFMACC : VPseudoVMAC_VV_VF_AAXA_RM;
defm PseudoVFNMACC : VPseudoVMAC_VV_VF_AAXA_RM;
defm PseudoVFMSAC : VPseudoVMAC_VV_VF_AAXA_RM;
@@ -6504,7 +6514,7 @@ defm PseudoVFNMSUB : VPseudoVMAC_VV_VF_AAXA_RM;
//===----------------------------------------------------------------------===//
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
//===----------------------------------------------------------------------===//
-let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in {
+let mayRaiseFPException = true, hasSideEffects = 0 in {
defm PseudoVFWMACC : VPseudoVWMAC_VV_VF_RM;
defm PseudoVFWNMACC : VPseudoVWMAC_VV_VF_RM;
defm PseudoVFWMSAC : VPseudoVWMAC_VV_VF_RM;
@@ -6516,7 +6526,7 @@ defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM;
//===----------------------------------------------------------------------===//
// 13.8. Vector Floating-Point Square-Root Instruction
//===----------------------------------------------------------------------===//
-let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in
+let mayRaiseFPException = true, hasSideEffects = 0 in
defm PseudoVFSQRT : VPseudoVSQR_V_RM;
//===----------------------------------------------------------------------===//
@@ -6528,7 +6538,7 @@ defm PseudoVFRSQRT7 : VPseudoVRCP_V;
//===----------------------------------------------------------------------===//
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
//===----------------------------------------------------------------------===//
-let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in
+let mayRaiseFPException = true, hasSideEffects = 0 in
defm PseudoVFREC7 : VPseudoVRCP_V_RM;
//===----------------------------------------------------------------------===//
@@ -6578,7 +6588,7 @@ defm PseudoVFMV_V : VPseudoVMV_F;
// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true in {
-let hasSideEffects = 0, hasPostISelHook = 1 in {
+let hasSideEffects = 0 in {
defm PseudoVFCVT_XU_F : VPseudoVCVTI_V_RM;
defm PseudoVFCVT_X_F : VPseudoVCVTI_V_RM;
}
@@ -6590,7 +6600,7 @@ defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V;
defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V;
defm PseudoVFROUND_NOEXCEPT : VPseudoVFROUND_NOEXCEPT_V;
-let hasSideEffects = 0, hasPostISelHook = 1 in {
+let hasSideEffects = 0 in {
defm PseudoVFCVT_F_XU : VPseudoVCVTF_V_RM;
defm PseudoVFCVT_F_X : VPseudoVCVTF_V_RM;
}
@@ -6602,7 +6612,7 @@ defm PseudoVFCVT_RM_F_X : VPseudoVCVTF_RM_V;
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true in {
-let hasSideEffects = 0, hasPostISelHook = 1 in {
+let hasSideEffects = 0 in {
defm PseudoVFWCVT_XU_F : VPseudoVWCVTI_V_RM;
defm PseudoVFWCVT_X_F : VPseudoVWCVTI_V_RM;
}
@@ -6623,7 +6633,7 @@ defm PseudoVFWCVTBF16_F_F : VPseudoVWCVTD_V;
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true in {
-let hasSideEffects = 0, hasPostISelHook = 1 in {
+let hasSideEffects = 0 in {
defm PseudoVFNCVT_XU_F : VPseudoVNCVTI_W_RM;
defm PseudoVFNCVT_X_F : VPseudoVNCVTI_W_RM;
}
@@ -6633,14 +6643,14 @@ defm PseudoVFNCVT_RM_X_F : VPseudoVNCVTI_RM_W;
defm PseudoVFNCVT_RTZ_XU_F : VPseudoVNCVTI_W;
defm PseudoVFNCVT_RTZ_X_F : VPseudoVNCVTI_W;
-let hasSideEffects = 0, hasPostISelHook = 1 in {
+let hasSideEffects = 0 in {
defm PseudoVFNCVT_F_XU : VPseudoVNCVTF_W_RM;
defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM;
}
defm PseudoVFNCVT_RM_F_XU : VPseudoVNCVTF_RM_W;
defm PseudoVFNCVT_RM_F_X : VPseudoVNCVTF_RM_W;
-let hasSideEffects = 0, hasPostISelHook = 1 in {
+let hasSideEffects = 0 in {
defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM;
defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM;
}
@@ -6679,7 +6689,7 @@ let Predicates = [HasVInstructionsAnyF] in {
//===----------------------------------------------------------------------===//
// 14.3. Vector Single-Width Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
-let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in {
+let mayRaiseFPException = true, hasSideEffects = 0 in {
defm PseudoVFREDOSUM : VPseudoVFREDO_VS_RM;
defm PseudoVFREDUSUM : VPseudoVFRED_VS_RM;
}
@@ -6691,8 +6701,7 @@ defm PseudoVFREDMAX : VPseudoVFREDMINMAX_VS;
//===----------------------------------------------------------------------===//
// 14.4. Vector Widening Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
-let IsRVVWideningReduction = 1, hasSideEffects = 0, mayRaiseFPException = true,
- hasPostISelHook = 1 in {
+let IsRVVWideningReduction = 1, hasSideEffects = 0, mayRaiseFPException = true in {
defm PseudoVFWREDUSUM : VPseudoVFWRED_VS_RM;
defm PseudoVFWREDOSUM : VPseudoVFWREDO_VS_RM;
}
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lukel97
approved these changes
Oct 30, 2024
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…es that set HasRoundModeOp. NFC (llvm#114294)
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Nov 4, 2024
…es that set HasRoundModeOp. NFC (llvm#114294)
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I think this is NFC, but right now it does change the flag for the pseudos removed by #114287. The rounding mode for those pseudos should never be DYN so the post isel hook shouldn't do anything, but it will get called.