A Tcl-Library for scripted HDL generation
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Updated
Apr 30, 2024 - Tcl
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systemverilog-hdl
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SPI Slave module written in SystemVerilog HDL
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Updated
May 12, 2025 - Tcl
This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.
fpga simulation verilog synthesis vivado systemverilog fpga-soc verilog-hdl 7segment systemverilog-hdl digitalclock nexys4ddr fpga-programming vivado-simulator
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Updated
Feb 28, 2025 - Tcl
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