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ddr

Here are 3 public repositories matching this topic...

adibis / DDR2_Controller

DDR2 memory controller written in Verilog

ddr verilog hdl verilog-project

Updated Feb 28, 2012
Verilog

Elphel / eddr3

mirror of https://git.elphel.com/Elphel/eddr3

fpga zynq ddr verilog xilinx open-core ddr3 memory-controller

Updated Oct 16, 2017
Verilog

DOUDIU / AXIS-AXI4-AXIS

This project is designed to delay the output of the video stream in AXI-STREAM format.

fpga ddr axi-stream axi-full

Updated Jul 14, 2024
Verilog

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