BrianHGinc / BrianHG-DDR3-Controller Star 78 Code Issues Pull requests DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included. fpga intel verilog xilinx altera systemverilog lattice hdl testbenches ddr3 Updated Apr 8, 2024 SystemVerilog
vbogdev / vbn-Riscv Star 1 Code Issues Pull requests An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga. processor-architecture fpga processor out-of-order superscalar risc-v processor-simulator ddr3 processor-design axi4 superscalar-cpu Updated Oct 7, 2024 SystemVerilog