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f6ea9fb
Added new Agafia SG0 Board
Khelicon 4171f79
Changes made as per requested
Khelicon fe4ffe3
fix: variant declaration
fpistm 4642ded
Merge pull request #1 from fpistm/AgafiaSG0
Khelicon 755e71e
fix(agafia): linker script typo
fpistm 3dba02b
Merge pull request #2 from fpistm/AgafiaSG0
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185 changes: 185 additions & 0 deletions
185
variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/ldscript.ld
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,185 @@ | ||
| /* | ||
| ****************************************************************************** | ||
| ** | ||
| ** @file : LinkerScript.ld | ||
| ** | ||
| ** @author : Auto-generated by STM32CubeIDE | ||
| ** | ||
| ** @brief : Linker script for STM32G071CBTx Device from STM32G0 series | ||
| ** 128Kbytes FLASH | ||
| ** 36Kbytes RAM | ||
| ** | ||
| ** Set heap size, stack size and stack location according | ||
| ** to application requirements. | ||
| ** | ||
| ** Set memory bank area and size if external memory is used | ||
| ** | ||
| ** Target : STMicroelectronics STM32 | ||
| ** | ||
| ** Distribution: The file is distributed as is, without any warranty | ||
| ** of any kind. | ||
| ** | ||
| ****************************************************************************** | ||
| ** @attention | ||
| ** | ||
| ** Copyright (c) 2022 STMicroelectronics. | ||
| ** All rights reserved. | ||
| ** | ||
| ** This software is licensed under terms that can be found in the LICENSE file | ||
| ** in the root directory of this software component. | ||
| ** If no LICENSE file comes with this software, it is provided AS-IS. | ||
| ** | ||
| ****************************************************************************** | ||
| */ | ||
|
|
||
| /* Entry Point */ | ||
| ENTRY(Reset_Handler) | ||
|
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| /* Highest address of the user mode stack */ | ||
| _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ | ||
|
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| _Min_Heap_Size = 0x200; /* required amount of heap */ | ||
| _Min_Stack_Size = 0x400; /* required amount of stack */ | ||
|
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| /* Memories definition */ | ||
| MEMORY | ||
| { | ||
| RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE | ||
| FLASH (rx) : ORIGIN = 0x8000000,+ LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET | ||
| } | ||
|
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||
| /* Sections */ | ||
| SECTIONS | ||
| { | ||
| /* The startup code into "FLASH" Rom type memory */ | ||
| .isr_vector : | ||
| { | ||
| . = ALIGN(4); | ||
| KEEP(*(.isr_vector)) /* Startup code */ | ||
| . = ALIGN(4); | ||
| } >FLASH | ||
|
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| /* The program code and other data into "FLASH" Rom type memory */ | ||
| .text : | ||
| { | ||
| . = ALIGN(4); | ||
| *(.text) /* .text sections (code) */ | ||
| *(.text*) /* .text* sections (code) */ | ||
| *(.glue_7) /* glue arm to thumb code */ | ||
| *(.glue_7t) /* glue thumb to arm code */ | ||
| *(.eh_frame) | ||
|
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| KEEP (*(.init)) | ||
| KEEP (*(.fini)) | ||
|
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| . = ALIGN(4); | ||
| _etext = .; /* define a global symbols at end of code */ | ||
| } >FLASH | ||
|
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| /* Constant data into "FLASH" Rom type memory */ | ||
| .rodata : | ||
| { | ||
| . = ALIGN(4); | ||
| *(.rodata) /* .rodata sections (constants, strings, etc.) */ | ||
| *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ | ||
| . = ALIGN(4); | ||
| } >FLASH | ||
|
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| .ARM.extab : { | ||
| . = ALIGN(4); | ||
| *(.ARM.extab* .gnu.linkonce.armextab.*) | ||
| . = ALIGN(4); | ||
| } >FLASH | ||
|
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| .ARM : { | ||
| . = ALIGN(4); | ||
| __exidx_start = .; | ||
| *(.ARM.exidx*) | ||
| __exidx_end = .; | ||
| . = ALIGN(4); | ||
| } >FLASH | ||
|
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| .preinit_array : | ||
| { | ||
| . = ALIGN(4); | ||
| PROVIDE_HIDDEN (__preinit_array_start = .); | ||
| KEEP (*(.preinit_array*)) | ||
| PROVIDE_HIDDEN (__preinit_array_end = .); | ||
| . = ALIGN(4); | ||
| } >FLASH | ||
|
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| .init_array : | ||
| { | ||
| . = ALIGN(4); | ||
| PROVIDE_HIDDEN (__init_array_start = .); | ||
| KEEP (*(SORT(.init_array.*))) | ||
| KEEP (*(.init_array*)) | ||
| PROVIDE_HIDDEN (__init_array_end = .); | ||
| . = ALIGN(4); | ||
| } >FLASH | ||
|
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| .fini_array : | ||
| { | ||
| . = ALIGN(4); | ||
| PROVIDE_HIDDEN (__fini_array_start = .); | ||
| KEEP (*(SORT(.fini_array.*))) | ||
| KEEP (*(.fini_array*)) | ||
| PROVIDE_HIDDEN (__fini_array_end = .); | ||
| . = ALIGN(4); | ||
| } >FLASH | ||
|
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| /* Used by the startup to initialize data */ | ||
| _sidata = LOADADDR(.data); | ||
|
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| /* Initialized data sections into "RAM" Ram type memory */ | ||
| .data : | ||
| { | ||
| . = ALIGN(4); | ||
| _sdata = .; /* create a global symbol at data start */ | ||
| *(.data) /* .data sections */ | ||
| *(.data*) /* .data* sections */ | ||
| *(.RamFunc) /* .RamFunc sections */ | ||
| *(.RamFunc*) /* .RamFunc* sections */ | ||
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| . = ALIGN(4); | ||
| _edata = .; /* define a global symbol at data end */ | ||
|
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| } >RAM AT> FLASH | ||
|
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| /* Uninitialized data section into "RAM" Ram type memory */ | ||
| . = ALIGN(4); | ||
| .bss : | ||
| { | ||
| /* This is used by the startup in order to initialize the .bss section */ | ||
| _sbss = .; /* define a global symbol at bss start */ | ||
| __bss_start__ = _sbss; | ||
| *(.bss) | ||
| *(.bss*) | ||
| *(COMMON) | ||
|
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| . = ALIGN(4); | ||
| _ebss = .; /* define a global symbol at bss end */ | ||
| __bss_end__ = _ebss; | ||
| } >RAM | ||
|
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| /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ | ||
| ._user_heap_stack : | ||
| { | ||
| . = ALIGN(8); | ||
| PROVIDE ( end = . ); | ||
| PROVIDE ( _end = . ); | ||
| . = . + _Min_Heap_Size; | ||
| . = . + _Min_Stack_Size; | ||
| . = ALIGN(8); | ||
| } >RAM | ||
|
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||
| /* Remove information from the compiler libraries */ | ||
| /DISCARD/ : | ||
| { | ||
| libc.a ( * ) | ||
| libm.a ( * ) | ||
| libgcc.a ( * ) | ||
| } | ||
|
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| .ARM.attributes 0 : { *(.ARM.attributes) } | ||
| } | ||
164 changes: 164 additions & 0 deletions
164
variants/STM32G0xx/G071C(6-8-B)(T-U)_G081CB(T-U)/variant_AGAFIA_SG0.cpp
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,164 @@ | ||
| /* | ||
| ******************************************************************************* | ||
| * Copyright (c) 2019, STMicroelectronics | ||
| * All rights reserved. | ||
| * | ||
| * Redistribution and use in source and binary forms, with or without | ||
| * modification, are permitted provided that the following conditions are met: | ||
| * | ||
| * 1. Redistributions of source code must retain the above copyright notice, | ||
| * this list of conditions and the following disclaimer. | ||
| * 2. Redistributions in binary form must reproduce the above copyright notice, | ||
| * this list of conditions and the following disclaimer in the documentation | ||
| * and/or other materials provided with the distribution. | ||
| * 3. Neither the name of STMicroelectronics nor the names of its contributors | ||
| * may be used to endorse or promote products derived from this software | ||
| * without specific prior written permission. | ||
| * | ||
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||
| * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||
| * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | ||
| * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | ||
| * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | ||
| * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | ||
| * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | ||
| * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | ||
| * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | ||
| * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| ******************************************************************************* | ||
| */ | ||
|
|
||
| #if defined(ARDUINO_AGAFIA_SG0) | ||
| #include "pins_arduino.h" | ||
|
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| #ifdef __cplusplus | ||
| extern "C" { | ||
| #endif | ||
|
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| // Pin number | ||
| const PinName digitalPin[] = { | ||
| PA_10, // D0 | ||
| PA_9, // D1 | ||
| PA_12, // D2 | ||
| PC_6, // D3 - SPI_CLK | ||
| PB_15, // D4 | ||
| PB_14, // D5 | ||
| PA_8, // D6 | ||
| PB_13, // D7 | ||
| PC_7, // D8 | ||
| PB_3, // D9 | ||
| PB_0, // D10 - SPI_CS | ||
| PA_7, // D11 - SPI_MOSI | ||
| PA_6, // D12 - PI_MISO | ||
| PA_5, // D13 - SPI_CLK | ||
| PB_9, // D14 | ||
| PB_8, // D15 | ||
|
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| PA_3, // D16 | ||
| PA_2, // D17 | ||
| PA_0, // D18 | ||
| PA_1, // D19 | ||
|
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| PA_11, // D20 | ||
| PA_15, // D21 | ||
| PD_0, // D22 | ||
| PD_1, // D23 | ||
| PD_2, // D24 | ||
| PD_3, // D25 | ||
| PD_4, // D26 | ||
| PB_4, // D27 | ||
| PB_5, // D28 | ||
| PB_6, // D29 | ||
| PB_7, // D30 | ||
|
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| PA_14, // D31 | ||
| PA_13, // D32 | ||
|
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| PF_0, // D33 | ||
| PF_1, // D34 | ||
| PC_13, // D35 | ||
|
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| PA_4, // D36/A0 - DAC1 | ||
| PB_12, // D37/A1 | ||
| PB_11, // D38/A2 | ||
| PB_10, // D39/A3 | ||
| PB_2, // D40/A4 | ||
| PB_1 // D41/A5 | ||
| }; | ||
|
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| // Analog (Ax) pin number array | ||
| const uint32_t analogInputPin[] = { | ||
| 36, // A0, PA4 | ||
| 37, // A1, PB12 | ||
| 38, // A2, PB11 | ||
| 39, // A3, PB10 | ||
| 40, // A4, PB2 | ||
| 41, // A5, PB1 | ||
| }; | ||
|
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|
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| #ifdef __cplusplus | ||
| } | ||
| #endif | ||
|
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| // ---------------------------------------------------------------------------- | ||
|
|
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| #ifdef __cplusplus | ||
| extern "C" { | ||
| #endif | ||
|
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| /** | ||
| * @brief System Clock Configuration | ||
| * The system Clock is configured as follows : | ||
| * System Clock source = PLL (HSI) | ||
| * SYSCLK(Hz) = 64000000 | ||
| * HCLK(Hz) = 64000000 | ||
| * AHB Prescaler = 1 | ||
| * APB1 Prescaler = 1 | ||
| * MSI Frequency(Hz) = 16000000 | ||
| * PLL_M = 1 | ||
| * PLL_N = 8 | ||
| * PLL_R = 2 | ||
| * PLL_P = 2 | ||
| * PLL_Q = 2 | ||
| * Flash Latency(WS) = 2 | ||
| * @param None | ||
| * @retval None | ||
| */ | ||
| WEAK void SystemClock_Config(void) | ||
| { | ||
| RCC_OscInitTypeDef RCC_OscInitStruct = {}; | ||
| RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; | ||
|
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| /* Configure the main internal regulator output voltage */ | ||
| HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); | ||
| /* Initializes the CPU, AHB and APB busses clocks */ | ||
| RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; | ||
| RCC_OscInitStruct.HSIState = RCC_HSI_ON; | ||
| RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; | ||
| RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; | ||
| RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; | ||
| RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; | ||
| RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; | ||
| RCC_OscInitStruct.PLL.PLLN = 8; | ||
| RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; | ||
| RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; | ||
| RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; | ||
| if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { | ||
| Error_Handler(); | ||
| } | ||
| /* Initializes the CPU, AHB and APB busses clocks */ | ||
| RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | ||
| | RCC_CLOCKTYPE_PCLK1; | ||
| RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; | ||
| RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; | ||
| RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; | ||
|
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| if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { | ||
| Error_Handler(); | ||
| } | ||
| } | ||
| #ifdef __cplusplus | ||
| } | ||
| #endif | ||
| #endif /* ARDUINO_AGAFIA_SG0 */ |
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