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system(U5) update STM32U5xx HAL Drivers to v1.1.0 , CMSIS Drivers to v1.1.0 #1685

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Merged
merged 4 commits into from
Apr 12, 2022
Merged

system(U5) update STM32U5xx HAL Drivers to v1.1.0 , CMSIS Drivers to v1.1.0 #1685

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7014e8c
system(U5) update STM32U5xx HAL Drivers to v1.1.0
ABOSTM Apr 12, 2022
c03979c
system(U5): update STM32U5xx CMSIS Drivers to v1.1.0
ABOSTM Apr 8, 2022
3eb3528
core(U5): update wrapped files
ABOSTM Apr 8, 2022
ba2ea41
variant U5: Regenerates variant board_entry with new U5 CMSIS v1.1.0
ABOSTM Apr 12, 2022
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8 changes: 8 additions & 0 deletions cores/arduino/stm32/stm32_def_build.h
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Original file line number Diff line number Diff line change
Expand Up @@ -414,6 +414,14 @@
#define CMSIS_STARTUP_FILE "startup_stm32u575xx.s"
#elif defined(STM32U585xx)
#define CMSIS_STARTUP_FILE "startup_stm32u585xx.s"
#elif defined(STM32U595xx)
#define CMSIS_STARTUP_FILE "startup_stm32u595xx.s"
#elif defined(STM32U599xx)
#define CMSIS_STARTUP_FILE "startup_stm32u599xx.s"
#elif defined(STM32U5A5xx)
#define CMSIS_STARTUP_FILE "startup_stm32u5a5xx.s"
#elif defined(STM32U5A9xx)
#define CMSIS_STARTUP_FILE "startup_stm32u5a9xx.s"
#elif defined(STM32WB10xx)
#define CMSIS_STARTUP_FILE "startup_stm32wb10xx_cm4.s"
#elif defined(STM32WB15xx)
Expand Down
2 changes: 2 additions & 0 deletions libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dsi.c
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Expand Up @@ -10,5 +10,7 @@
#include "stm32h7xx_hal_dsi.c"
#elif STM32L4xx
#include "stm32l4xx_hal_dsi.c"
#elif STM32U5xx
#include "stm32u5xx_hal_dsi.c"
#endif
#pragma GCC diagnostic pop
2 changes: 2 additions & 0 deletions libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gfxmmu.c
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Expand Up @@ -6,5 +6,7 @@
#include "stm32h7xx_hal_gfxmmu.c"
#elif STM32L4xx
#include "stm32l4xx_hal_gfxmmu.c"
#elif STM32U5xx
#include "stm32u5xx_hal_gfxmmu.c"
#endif
#pragma GCC diagnostic pop
8 changes: 8 additions & 0 deletions libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpu2d.c
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Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
/* HAL raised several warnings, ignore them */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wunused-parameter"

#ifdef STM32U5xx
#include "stm32u5xx_hal_gpu2d.c"
#endif
#pragma GCC diagnostic pop
2 changes: 2 additions & 0 deletions libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ltdc.c
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Expand Up @@ -10,5 +10,7 @@
#include "stm32h7xx_hal_ltdc.c"
#elif STM32L4xx
#include "stm32l4xx_hal_ltdc.c"
#elif STM32U5xx
#include "stm32u5xx_hal_ltdc.c"
#endif
#pragma GCC diagnostic pop
2 changes: 2 additions & 0 deletions libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ltdc_ex.c
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Expand Up @@ -10,5 +10,7 @@
#include "stm32h7xx_hal_ltdc_ex.c"
#elif STM32L4xx
#include "stm32l4xx_hal_ltdc_ex.c"
#elif STM32U5xx
#include "stm32u5xx_hal_ltdc_ex.c"
#endif
#pragma GCC diagnostic pop
8 changes: 8 additions & 0 deletions libraries/SrcWrapper/src/HAL/stm32yyxx_hal_xspi.c
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Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
/* HAL raised several warnings, ignore them */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wunused-parameter"

#ifdef STM32U5xx
#include "stm32u5xx_hal_xspi.c"
#endif
#pragma GCC diagnostic pop
53 changes: 24 additions & 29 deletions system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u575xx.h
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Expand Up @@ -12,24 +12,24 @@
* - Setup Interrupt Target
*
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
* Portions Copyright (c) 2021 STMicroelectronics, all rights reserved
*
* SPDX-License-Identifier: Apache-2.0
/**
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
* Portions Copyright (c) 2021 STMicroelectronics, all rights reserved
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
* SPDX-License-Identifier: Apache-2.0
*
* http://www.apache.org/licenses/LICENSE-2.0
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

#ifndef PARTITION_STM32U575XX_H
#define PARTITION_STM32U575XX_H
Expand Down Expand Up @@ -377,7 +377,7 @@
/*
// Interrupts 0..31
// <o.0> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
// <o.1> PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state
// <o.1> PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state
// <o.2> RTC_IRQn <0=> Secure state <1=> Non-Secure state
// <o.3> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
// <o.4> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
Expand All @@ -404,7 +404,6 @@
// <o.25> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
// <o.26> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
// <o.27> IWDG_IRQn <0=> Secure state <1=> Non-Secure state
// <o.28> SAES_IRQn <0=> Secure state <1=> Non-Secure state
// <o.29> GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
// <o.30> GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.31> GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
Expand All @@ -428,7 +427,7 @@
// <o.3> GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
// <o.4> GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
// <o.5> ADC1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.6> DAC_IRQn <0=> Secure state <1=> Non-Secure state
// <o.6> DAC1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.7> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
// <o.8> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.9> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
Expand Down Expand Up @@ -479,7 +478,7 @@
// <o.8> COMP_IRQn <0=> Secure state <1=> Non-Secure state
// <o.9> OTG_FS_IRQn <0=> Secure state <1=> Non-Secure state
// <o.10> CRS_IRQn <0=> Secure state <1=> Non-Secure state
// <o.11> FSMC_IRQn <0=> Secure state <1=> Non-Secure state
// <o.11> FMC_IRQn <0=> Secure state <1=> Non-Secure state
// <o.12> OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.13> PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state
// <o.14> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
Expand All @@ -497,7 +496,6 @@
// <o.26> SAI1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.27> SAI2_IRQn <0=> Secure state <1=> Non-Secure state
// <o.28> TSC_IRQn <0=> Secure state <1=> Non-Secure state
// <o.29> AES_IRQn <0=> Secure state <1=> Non-Secure state
// <o.30> RNG_IRQn <0=> Secure state <1=> Non-Secure state
// <o.31> FPU_IRQn <0=> Secure state <1=> Non-Secure state
*/
Expand All @@ -508,14 +506,13 @@
*/

/*
// <e>Initialize ITNS 3 (Interrupts 96..108)
// <e>Initialize ITNS 3 (Interrupts 96..125)
*/
#define NVIC_INIT_ITNS3 1

/*
// Interrupts 96..125
// <o.0> HASH_IRQn <0=> Secure state <1=> Non-Secure state
// <o.1> PKA_IRQn <0=> Secure state <1=> Non-Secure state
// <o.2> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
// <o.3> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
// <o.4> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
Expand All @@ -526,18 +523,16 @@
// <o.9> MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state
// <o.10> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.11> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
// <o.12> OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.13> OTFDEC2_IRQn <0=> Secure state <1=> Non-Secure state
// <o.14> LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
// <o.15> DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.16> ADF1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.17> ADC4_IRQn <0=> Secure state <1=> Non-Secure state
// <o.18> LPDMA_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
// <o.19> LPDMA_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.20> LPDMA_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
// <o.21> LPDMA_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
// <o.18> LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
// <o.19> LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.20> LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
// <o.21> LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
// <o.22> DMA2D_IRQn <0=> Secure state <1=> Non-Secure state
// <o.23> DCMI_IRQn <0=> Secure state <1=> Non-Secure state
// <o.23> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state
// <o.24> OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state
// <o.25> MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state
// <o.26> MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state
Expand Down
46 changes: 23 additions & 23 deletions system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u585xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -12,24 +12,24 @@
* - Setup Interrupt Target
*
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
* Portions Copyright (c) 2021 STMicroelectronics, all rights reserved
*
* SPDX-License-Identifier: Apache-2.0
/**
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
* Portions Copyright (c) 2021 STMicroelectronics, all rights reserved
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
* SPDX-License-Identifier: Apache-2.0
*
* http://www.apache.org/licenses/LICENSE-2.0
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

#ifndef PARTITION_STM32U585XX_H
#define PARTITION_STM32U585XX_H
Expand Down Expand Up @@ -377,7 +377,7 @@
/*
// Interrupts 0..31
// <o.0> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
// <o.1> PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state
// <o.1> PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state
// <o.2> RTC_IRQn <0=> Secure state <1=> Non-Secure state
// <o.3> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
// <o.4> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
Expand Down Expand Up @@ -428,7 +428,7 @@
// <o.3> GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
// <o.4> GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
// <o.5> ADC1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.6> DAC_IRQn <0=> Secure state <1=> Non-Secure state
// <o.6> DAC1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.7> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
// <o.8> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.9> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
Expand Down Expand Up @@ -479,7 +479,7 @@
// <o.8> COMP_IRQn <0=> Secure state <1=> Non-Secure state
// <o.9> OTG_FS_IRQn <0=> Secure state <1=> Non-Secure state
// <o.10> CRS_IRQn <0=> Secure state <1=> Non-Secure state
// <o.11> FSMC_IRQn <0=> Secure state <1=> Non-Secure state
// <o.11> FMC_IRQn <0=> Secure state <1=> Non-Secure state
// <o.12> OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.13> PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state
// <o.14> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
Expand Down Expand Up @@ -532,12 +532,12 @@
// <o.15> DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.16> ADF1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.17> ADC4_IRQn <0=> Secure state <1=> Non-Secure state
// <o.18> LPDMA_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
// <o.19> LPDMA_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.20> LPDMA_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
// <o.21> LPDMA_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
// <o.18> LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
// <o.19> LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
// <o.20> LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
// <o.21> LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
// <o.22> DMA2D_IRQn <0=> Secure state <1=> Non-Secure state
// <o.23> DCMI_IRQn <0=> Secure state <1=> Non-Secure state
// <o.23> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state
// <o.24> OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state
// <o.25> MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state
// <o.26> MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state
Expand Down
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