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Merged
merged 4 commits into from
Mar 30, 2021
Merged

Update STM32L4 HAL and CMSIS drivers #1344

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0628841
[L4] Update STM32L4xx HAL Drivers to v1.13.0
fpistm Mar 30, 2021
6a9567f
[L4] Update STM32L4xx CMSIS Drivers to v1.7.1
fpistm Mar 30, 2021
4da1a5f
[L4] Update wrapped files
fpistm Mar 30, 2021
9f3f053
[L4] Update the system source file
fpistm Mar 30, 2021
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3 changes: 3 additions & 0 deletions libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c
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Expand Up @@ -4,6 +4,9 @@
#ifdef STM32L0xx
#include "stm32l0xx_hal_smbus_ex.c"
#endif
#ifdef STM32L4xx
#include "stm32l4xx_hal_smbus_ex.c"
#endif
#ifdef STM32L5xx
#include "stm32l5xx_hal_smbus_ex.c"
#endif
1 change: 0 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h
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Expand Up @@ -2259,7 +2259,6 @@ typedef struct
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM_6 (0x40UL << CRS_CR_TRIM_Pos) /*!< 0x00004000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
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1 change: 0 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l422xx.h
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Expand Up @@ -2294,7 +2294,6 @@ typedef struct
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM_6 (0x40UL << CRS_CR_TRIM_Pos) /*!< 0x00004000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
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7 changes: 2 additions & 5 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h
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Expand Up @@ -5729,7 +5729,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
Expand Down Expand Up @@ -9277,15 +9276,13 @@ typedef struct

/*!< HSITRIM configuration */
#define RCC_ICSCR_HSITRIM_Pos (24U)
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */

/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
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7 changes: 2 additions & 5 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h
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Expand Up @@ -5714,7 +5714,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
Expand Down Expand Up @@ -8938,15 +8937,13 @@ typedef struct

/*!< HSITRIM configuration */
#define RCC_ICSCR_HSITRIM_Pos (24U)
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */

/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
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7 changes: 2 additions & 5 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h
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Expand Up @@ -5788,7 +5788,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
Expand Down Expand Up @@ -9369,15 +9368,13 @@ typedef struct

/*!< HSITRIM configuration */
#define RCC_ICSCR_HSITRIM_Pos (24U)
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */

/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
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7 changes: 2 additions & 5 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l442xx.h
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Expand Up @@ -5749,7 +5749,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
Expand Down Expand Up @@ -9154,15 +9153,13 @@ typedef struct

/*!< HSITRIM configuration */
#define RCC_ICSCR_HSITRIM_Pos (24U)
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */

/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
Expand Down
7 changes: 2 additions & 5 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l443xx.h
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Expand Up @@ -5823,7 +5823,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
Expand Down Expand Up @@ -9585,15 +9584,13 @@ typedef struct

/*!< HSITRIM configuration */
#define RCC_ICSCR_HSITRIM_Pos (24U)
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */

/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
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1 change: 0 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l451xx.h
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Expand Up @@ -5779,7 +5779,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
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1 change: 0 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l452xx.h
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Expand Up @@ -5821,7 +5821,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
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1 change: 0 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l462xx.h
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Expand Up @@ -5856,7 +5856,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
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1 change: 0 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h
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Expand Up @@ -6272,7 +6272,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
Expand Down
1 change: 0 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4a6xx.h
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Expand Up @@ -6336,7 +6336,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
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2 changes: 0 additions & 2 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4p5xx.h
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Expand Up @@ -1636,7 +1636,6 @@ typedef struct
#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
Expand Down Expand Up @@ -6481,7 +6480,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
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2 changes: 0 additions & 2 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4q5xx.h
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Expand Up @@ -1686,7 +1686,6 @@ typedef struct
#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
Expand Down Expand Up @@ -6533,7 +6532,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
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1 change: 0 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h
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Expand Up @@ -6198,7 +6198,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
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1 change: 0 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r7xx.h
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Expand Up @@ -6284,7 +6284,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
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1 change: 0 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h
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Expand Up @@ -6366,7 +6366,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
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1 change: 0 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s5xx.h
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Expand Up @@ -6262,7 +6262,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
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1 change: 0 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s7xx.h
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Expand Up @@ -6348,7 +6348,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
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1 change: 0 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s9xx.h
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Expand Up @@ -6430,7 +6430,6 @@ typedef struct
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */

/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
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2 changes: 1 addition & 1 deletion system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h
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Expand Up @@ -107,7 +107,7 @@
*/
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
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