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[New Variant] generic STM32F401R pinout #784

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@MCUdude

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@MCUdude

Hi!

As mentioned in #722 I'm working on a new pinout for a generic F401R. The pinout is not "board oriented" but rather "chip oriented". This means the Arduino style pinout matches the port numbers as closely as possible.

I've gotten all digital pins to work as they should, but I'm having a hard time getting the analog pins to work, due to the way the analogRead function is implemented. Is there a way I can get the pinout below to work by using analogRead(A0) or analogRead(PA0) without having to "align" all analog pins so that A0, A1...A15 comes after eachother?

/*----------------------------------------------------------------------------
 *        Pins
 *----------------------------------------------------------------------------*/
                // | ANALOG | USART     | TWI      | SPI                    | SPECIAL   |
                // |--------|-----------|----------|------------------------|-----------|
#define PA0  0  // | A0     |           |          |                        |           |
#define PA1  1  // | A1     |           |          |                        |           |
#define PA2  2  // | A2     | USART2_TX |          |                        |           |
#define PA3  3  // | A3     | USART2_RX |          |                        |           |
#define PA4  4  // | A4     |           |          | SPI1_SS, (SPI3_SS)     |           |
#define PA5  5  // | A5     |           |          | SPI1_SCK               |           |
#define PA6  6  // | A6     |           |          | SPI1_MISO              |           |
#define PA7  7  // | A7     |           |          | SPI1_MOSI              |           |
#define PA8  8  // |        |           | TWI3_SCL |                        |           |
#define PA9  9  // |        | USART1_TX |          |                        |           |
#define PA10 10 // |        | USART1_RX |          |                        |           |
#define PA11 11 // |        | USART6_TX |          |                        |           |
#define PA12 12 // |        | USART6_RX |          |                        |           |
#define PA13 13 // |        |           |          |                        | SWD_SWDIO |
#define PA14 14 // |        |           |          |                        | SWD_SWCLK |
#define PA15 15 // |        |           |          | SPI1_SS, (SPI3_SS)     |           |
                // |--------|-----------|----------|------------------------|-----------|
#define PB0  16 // | A8     |           |          |                        |           |
#define PB1  17 // | A9     |           |          |                        |           |
#define PB2  18 // |        |           |          |                        | BOOT1     |
#define PB3  19 // |        |           | TWI2_SDA | SPI1_SCK,  (SPI3_SCK)  |           |
#define PB4  20 // |        |           | TWI3_SDA | SPI1_MISO, (SPI3_MISO) |           |
#define PB5  21 // |        |           |          | SPI1_MOSI, (SPI3_MOSI) |           |
#define PB6  22 // |        | USART1_TX | TWI1_SCL |                        |           |
#define PB7  23 // |        | USART1_RX | TWI1_SDA |                        |           |
#define PB8  24 // |        |           | TWI1_SCL |                        |           |
#define PB9  25 // |        |           | TWI1_SDA | SPI2_SS                |           |
#define PB10 26 // |        |           | TWI2_SCL | SPI2_SCK               |           |
#define PB12 27 // |        |           |          | SPI2_SS                |           |
#define PB13 28 // |        |           |          | SPI2_SCK               |           |
#define PB14 29 // |        |           |          | SPI2_MISO              |           |
#define PB15 30 // |        |           |          | SPI2_MOSI              |           |
                // |--------|-----------|----------|------------------------|-----------|
#define PC0  31 // | A10    |           |          |                        |           |
#define PC1  32 // | A11    |           |          |                        |           |
#define PC2  33 // | A12    |           |          | SPI2_MISO              |           |
#define PC3  34 // | A13    |           |          | SPI2_MOSI              |           |
#define PC4  35 // | A14    |           |          |                        |           |
#define PC5  36 // | A15    |           |          |                        |           |
#define PC6  37 // |        | USART6_TX |          |                        |           |
#define PC7  38 // |        | USART6_RX |          |                        |           |
#define PC8  39 // |        |           |          |                        |           |
#define PC9  40 // |        |           | TWI3_SDA |                        |           |
#define PC10 41 // |        |           |          | SPI3_SCK               |           |
#define PC11 42 // |        |           |          | SPI3_MISO              |           |
#define PC12 43 // |        |           |          | SPI3_MOSI              |           |
#define PC13 44 // |        |           |          |                        |           |
#define PC14 45 // |        |           |          |                        | OSC32_IN  |
#define PC15 46 // |        |           |          |                        | OSC32_OUT |
                // |--------|-----------|----------|------------------------|-----------|
#define PD2  47 // |        |           |          |                        |           |
                // |--------|-----------|----------|------------------------|-----------|
#define PH0  48 // |        |           |          |                        | OSC_IN    |
#define PH1  49 // |        |           |          |                        | OSC_OUT   |
                // |--------|-----------|----------|------------------------|-----------|

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