Closed
Description
Describe the bug
CI compilation failed for several MCU:
- STM32F051R4 and STM32_F058R8, see CI check Added F0 boards #1792
- STM32L010C6 see CI check Added Generic L0xx Boards #1796
/github/home/.arduino15/packages/STMicroelectronics/hardware/stm32/2.3.0/variants/STM32F0xx/F051R4T/PeripheralPins.c:128:69: error: 'GPIO_AF0_TIM3' undeclared here (not in a function); did you mean 'GPIO_AF1_TIM3'?
128 | {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM3, 3, 0)}, // TIM3_CH3
| ^~~~~~~~~~~~~
/github/home/.arduino15/packages/STMicroelectronics/hardware/stm32/2.3.0/cores/arduino/stm32/PinNamesTypes.h:88:26: note: in definition of macro 'STM_PIN_DEFINE_EXT'
88 | ((AFNUM & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\
| ^~~~~
/github/home/.arduino15/packages/STMicroelectronics/hardware/stm32/2.3.0/variants/STM32F0xx/F051R4T/PeripheralPins.c:128:23: note: in expansion of macro 'STM_PIN_DATA_EXT'
128 | {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM3, 3, 0)}, // TIM3_CH3
| ^~~~~~~~~~~~~~~~
Error during build: exit status 1
| 76/325 | GENERIC_F051R4TX | failed | 19.23 s |
Analysis
1st analysis shows that some GPIO specificities are not properly managed:
For example, STM32F051R4 has Port C.
On PC8 we can access to Alternate function TIM3_CH3.
But this GPIO port (PORTC) doesn't have register GPIOx_AFRL/GPIOx_AFRH registers,
there is a unique Alternate capability which is TIM3_CH3, no register to select it, it is default.
This is the reason why define GPIO_AF0_TIM3 doesn't exist, there is no register to enter this value.
This is subtly mentioned in Reference Manual RM0091 Rev 10
8.1 Introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and
GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR).
Ports A and B also have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers
(GPIOx_AFRH and GPIOx_AFRL).
On STM32F07x and STM32F09x devices, also ports C, D, E, and F have two 32-bit alternate function selection registers
(GPIOx_AFRH and GPIOx_AFRL).
Also in CMSIS there is a define which clearly state that only port A and port B support Alternate registers (for stm32f051x8),
it may be useful for a potential fix:
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB))