Increase performance of UART RX.

[nseidle]

This PR

• Increases the UART buffers from 256 * 4 (TX/RX for UART0 and UART1) to 4096 * 4
• Removes the loop within the RX ISR
• These changes allow Artemis to receive full speed 460800bps without dropping bytes

We are only doing single byte reads from the UART FIFO. By calling am_hal_uart_transfer multiple times it increases the ISR time.

Original timing:

Timing after this PR:

You can see the ISR becomes shorter and more repetitive.

FWIW - With burst mode turned on, ISR drops even more to 8.5us so 921600bps may be possible.

For reference:

• How big is RX FIFO within HAL? 32 bytes
• Is there a 'nearly full' interrupt for the RX FIFO? No
• We could check the RX FIFO empty bit in the ISR in a loop but this is basically skirting the HAL layer. I've attempted this without much luck.
• We could increase the ISR priority level but we haven't done this for any ISRs in the core, yet, so I'm not sure if we want to.

This PR attempts to strike a balance between RAM footprint (what's and extra 15k between friends?) and increase serial performance.

[oclyke]

Cool - where previously the ISR allowed for possibly catching more than one byte per interrupt (with the do while loop) we now expect to read just one byte each time. This reduces execution time significantly because there is not a wasted HAL call that is used to show when no more data is available in the HAL buffers. Looks good to me!