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[AMDGPU][SDAG] Initial support for ISD::PTRADD #141725

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[AMDGPU][SDAG] Initial support for ISD::PTRADD #141725

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610b51e
[AMDGPU][SDAG] Initial support for ISD::PTRADD
ritter-x2a May 27, 2025
f902408
Set GISelShouldIgnore for the 64-bit PTRADD patterns.
ritter-x2a May 28, 2025
d62ce07
Disable PTRADD for 32-bit pointers and remove relevant changes
ritter-x2a May 28, 2025
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13 changes: 13 additions & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,14 @@ static cl::opt<bool> UseDivergentRegisterIndexing(
cl::desc("Use indirect register addressing for divergent indexes"),
cl::init(false));

// TODO This option should be removed once we switch to always using PTRADD in
// the SelectionDAG.
static cl::opt<bool> UseSelectionDAGPTRADD(
"amdgpu-use-sdag-ptradd", cl::Hidden,
cl::desc("Generate ISD::PTRADD nodes for 64-bit pointer arithmetic in the "
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why only 32-bit pointer?

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You mean "why only 64-bit", right? That's following a suggestion by Matt, to start only with 64-bit pointers since it simplifies the patches and since the problem I am actually preparing to solve with this only affects codegen for the flat AS 0.

"SelectionDAG ISel"),
cl::init(false));

static bool denormalModeIsFlushAllF32(const MachineFunction &MF) {
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
return Info->getMode().FP32Denormals == DenormalMode::getPreserveSign();
Expand Down Expand Up @@ -10448,6 +10456,11 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
}
}

bool SITargetLowering::shouldPreservePtrArith(const Function &F,
EVT PtrVT) const {
return UseSelectionDAGPTRADD && PtrVT == MVT::i64;
}

// The raw.(t)buffer and struct.(t)buffer intrinsics have two offset args:
// offset (the offset that is included in bounds checking and swizzling, to be
// split between the instruction's voffset and immoffset fields) and soffset
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2 changes: 2 additions & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.h
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Expand Up @@ -259,6 +259,8 @@ class SITargetLowering final : public AMDGPUTargetLowering {

bool shouldExpandVectorDynExt(SDNode *N) const;

bool shouldPreservePtrArith(const Function &F, EVT PtrVT) const override;

private:
// Analyze a combined offset from an amdgcn_s_buffer_load intrinsic and store
// the three offsets (voffset, soffset and instoffset) into the SDValue[3]
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14 changes: 14 additions & 0 deletions llvm/lib/Target/AMDGPU/SIInstructions.td
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Expand Up @@ -1376,6 +1376,20 @@ def : GCNPat <
(i32 (V_MOV_B32_e32 (i32 0))), sub1)
>;

//===----------------------------------------------------------------------===//
// PTRADD Patterns
//===----------------------------------------------------------------------===//

// GlobalISel shouldn't generate 64-bit addition pseudos.
let GISelShouldIgnore = 1 in {
def : GCNPat<
(DivergentBinFrag<ptradd> i64:$src0, i64:$src1),
(V_ADD_U64_PSEUDO $src0, $src1)>;
def : GCNPat<
(UniformBinFrag<ptradd> i64:$src0, i64:$src1),
(S_ADD_U64_PSEUDO $src0, $src1)>;
}

/********** ============================================ **********/
/********** Extraction, Insertion, Building and Casting **********/
/********** ============================================ **********/
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