NVlabs · charleshong3 · May 8, 2025
diff --git a/dataset_code-complete-iccad2023/Prob053_m2014_q4d_ref.sv b/dataset_code-complete-iccad2023/Prob053_m2014_q4d_ref.sv
@@ -6,7 +6,7 @@ module RefModule (
 );
 
   initial
-    out = 0;
+    out = 1'hx;
 
   always@(posedge clk) begin
     out <= in ^ out;

diff --git a/dataset_code-complete-iccad2023/Prob104_mt2015_muxdff_ref.sv b/dataset_code-complete-iccad2023/Prob104_mt2015_muxdff_ref.sv
@@ -7,7 +7,7 @@ module RefModule (
   output reg Q
 );
 
-  initial Q=0;
+  initial Q=1'hx;
   always @(posedge clk)
     Q <= L ? r_in : q_in;
 

diff --git a/dataset_spec-to-rtl/Prob034_dff8_ref.sv b/dataset_spec-to-rtl/Prob034_dff8_ref.sv
@@ -6,7 +6,7 @@ module RefModule (
 );
 
   initial
-    q = 8'h0;
+    q = 8'hx;
 
   always @(posedge clk)
     q <= d;

diff --git a/dataset_spec-to-rtl/Prob053_m2014_q4d_ref.sv b/dataset_spec-to-rtl/Prob053_m2014_q4d_ref.sv
@@ -6,7 +6,7 @@ module RefModule (
 );
 
   initial
-    out = 0;
+    out = 1'hx;
 
   always@(posedge clk) begin
     out <= in ^ out;

diff --git a/dataset_spec-to-rtl/Prob104_mt2015_muxdff_ref.sv b/dataset_spec-to-rtl/Prob104_mt2015_muxdff_ref.sv
@@ -7,7 +7,7 @@ module RefModule (
   output reg Q
 );
 
-  initial Q=0;
+  initial Q=1'hx;
   always @(posedge clk)
     Q <= L ? r_in : q_in;
-Original file line number
+Diff line change
@@ Expand Up / @@ -6,7 +6,7 @@ module RefModule ( @@
     );
       initial
-        q = 8'h0;
+        q = 8'hx;
       always @(posedge clk)
         q <= d;
@@ Expand Down @@