Fixing problem prompts and testbenches for better consistency and accuracy.

Author: npfet

dataset_code-complete-iccad2023/Prob045_edgedetect2_prompt.txt

@@ -1,7 +1,7 @@
 
 For each bit in an 8-bit vector, detect when the input signal changes
 from one clock cycle to the next (detect any edge). The output bit should
-be set the cycle after a 0 to 1 transition occurs.
+be set the cycle after a 0 to 1 or 1 to 0 transition occurs.
 
 module TopModule (
   input clk,

dataset_code-complete-iccad2023/Prob074_ece241_2014_q4_prompt.txt

@@ -6,7 +6,7 @@ Build this circuit in Verilog.
 
 Input x goes to three different two-input gates: a XOR, an AND, and a OR
 gate. Each of the three gates is connected to the input of a D flip-flop
-and then the flip-flop outputs all go to a three-input XNOR, whose output
+and then the flip-flop outputs all go to a three-input NOR, whose output
 is Z. The second input of the XOR is its corresponding flip-flop's
 output, the second input of the AND is its corresponding flip-flop's
 complemented output, and finally the second input of the OR is its

dataset_code-complete-iccad2023/Prob079_fsm3onehot_test.sv

@@ -10,32 +10,13 @@ module stimulus_gen (
 	input tb_match
 );
 
-	int errored1 = 0;
-	int onehot_error = 0;
-	
 	initial begin
 		// Test the one-hot cases first.
 		repeat(200) @(posedge clk, negedge clk) begin
 			state <= 1<< ($unsigned($random) % 4);
 			in <= $random;
-			if (!tb_match) onehot_error++;
 		end
 
-			
-		// Random.
-		errored1 = 0;
-		repeat(400) @(posedge clk, negedge clk) begin
-			state <= $random;
-			in <= $random;
-			if (!tb_match)
-				errored1++;
-		end
-		if (!onehot_error && errored1) 
-			$display ("Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.");
-
-		if (!onehot_error && errored1)
-			$display("Hint: Are you doing something more complicated than deriving state transition equations by inspection?\n");
-
 		#1 $finish;
 	end
 

dataset_code-complete-iccad2023/Prob082_lfsr32_prompt.txt

@@ -1,11 +1,11 @@
 
 A linear feedback shift register is a shift register usually with a few
 XOR gates to produce the next state of the shift register. A Galois LFSR
-is one particular arrangement where bit positions with a "tap" are XORed
-with the output bit to produce each bit's next value, while bit positions
-without a tap shift. Build a 32-bit Galois LFSR with taps at bit
-positions 32, 22, 2, and 1. Reset should be active high synchronous, and
-should reset the output q to 32'h1.
+is one particular arrangement that shifts right, where a bit position with
+a "tap" is XORed with the LSB output bit (q[0]) to produce its next value,
+while bit positions without a tap shift right unchanged.  Build a 32-bit Galois
+LFSR with taps at bit positions 32, 22, 2, and 1. Reset should be active high
+synchronous, and should reset the output q to 32'h1.
 
 module TopModule (
   input clk,

dataset_code-complete-iccad2023/Prob086_lfsr5_prompt.txt

@@ -1,11 +1,11 @@
 
 A linear feedback shift register is a shift register usually with a few
 XOR gates to produce the next state of the shift register. A Galois LFSR
-is one particular arrangement where bit positions with a "tap" are XORed
-with the output bit to produce its next value, while bit positions
-without a tap shift. If the taps positions are carefully chosen, the LFSR
-can be made to be "maximum-length". A maximum-length LFSR of n bits
-cycles through 2**n-1 states before repeating (the all-zero state is
+is one particular arrangement that shifts right, where a bit position with
+a "tap" is XORed with the LSB output bit (q[0]) to produce its next value,
+while bit positions without a tap shift right unchanged. If the taps positions
+are carefully chosen, the LFSR can be made to be "maximum-length". A maximum-length
+LFSR of n bits cycles through 2**n-1 states before repeating (the all-zero state is
 never reached). Build a 5-bit maximal-length Galois LFSR with taps at bit
 positions 5 and 3. The active-high synchronous reset should reset the
 LFSR output to 1.

dataset_code-complete-iccad2023/Prob099_m2014_q6c_test.sv

@@ -11,38 +11,13 @@ module stimulus_gen (
 	input tb_match
 );
 
-	int errored1 = 0;
-	int onehot_error = 0;
-	int temp;
-	
 	initial begin
 		// Test the one-hot cases first.
 		repeat(200) @(posedge clk, negedge clk) begin
 			y <= 1<< ($unsigned($random) % 6);
 			w <= $random;
-			if (!tb_match) onehot_error++;
-		end
-			
-			
-		// Random.
-		errored1 = 0;
-		repeat(400) @(posedge clk, negedge clk) begin
-			do 
-				temp = $random;
-			while ( !{temp[6:5],temp[3:2]} == !{temp[4],temp[1]} );	
-			// Make y[4,1] and y[6,5,3,2] mutually exclusive, so we can accept Y4=(~y[1] & ~y[4]) &w as a valid answer too.
-
-			y[6:1] <= temp[6:1];
-			w <= $random;
-			if (!tb_match)
-				errored1++;
-		end
-		if (!onehot_error && errored1) 
-			$display ("Hint: Your circuit passed when given only one-hot inputs, but not with semi-random inputs.");
-
-		if (!onehot_error && errored1)
-			$display("Hint: Are you doing something more complicated than deriving state transition equations by inspection?\n");
-
+		end	
+	
 		#1 $finish;
 	end
 

dataset_code-complete-iccad2023/Prob104_mt2015_muxdff_prompt.txt

@@ -2,10 +2,10 @@
 Consider this Verilog module "full_module":
 
   module full_module (
-      input [2:0] r,
-      input L,
-      input clk,
-      output reg [2:0] q
+      input [2:0] r, // load value
+      input L, // load
+      input clk, // clock
+      output reg [2:0] q // output
 
     always @(posedge clk) begin
       if (L) begin
@@ -17,9 +17,11 @@ Consider this Verilog module "full_module":
 
   endmodule
 
-You want to create a hierarchical Verilog design where a flipflop and 2-1
-multiplexer are in a submodule, and that submodule is instantiated three
-times in this code. Create the submodule called "top_module".
+Note that q[2:0] is three bits wide, representing three flip-flops that can be
+loaded from r when L is asserted. You want to factor full_module into a hierarchical
+design, flipflop and 2:1 multiplexer are in a submodule "TopModule", and that submodule
+will be instantiated three times in full_module code. Create the submodule called "TopModule".
+You do not have to provide the revised full_module.
 
 module TopModule (
   input clk,

dataset_code-complete-iccad2023/Prob124_rule110_prompt.txt

@@ -5,20 +5,20 @@ array of cells (on or off). At each time step, the state of each cell
 changes. In Rule 110, the next state of each cell depends only on itself
 and its two neighbours, according to the following table:
 
-  Left | Center | Right | Center's next state
-  1    | 1      | 1     | 0
-  1    | 1      | 0     | 1
-  1    | 0      | 1     | 1
-  1    | 0      | 0     | 0
-  0    | 1      | 1     | 1
-  0    | 1      | 0     | 1
-  0    | 0      | 1     | 1
-  0    | 0      | 0     | 0
+  Left[i+1] | Center[i] | Right[i-1] | Center's next state 
+  1         | 1         | 1          | 0
+  1         | 1         | 0          | 1
+  1         | 0         | 1          | 1
+  1         | 0         | 0          | 0
+  0         | 1         | 1          | 1
+  0         | 1         | 0          | 1
+  0         | 0         | 1          | 1
+  0         | 0         | 0          | 0
 
 In this circuit, create a 512-cell system (q[511:0]), and advance by one
 time step each clock cycle. The synchronous active high load input
 indicates the state of the system should be loaded with data[511:0].
-Assume the boundaries (q[-1] and q[512]) are both zero (off).
+Assume the boundaries (q[-1] and q[512], if they existed) are both zero (off).
 
 module TopModule (
   input clk,

dataset_code-complete-iccad2023/Prob134_2014_q3c_prompt.txt

@@ -2,7 +2,7 @@
 Given the state-assigned table shown below, implement the logic functions
 Y[0] and z.
 
-   Present state y[2:0] | Next state Y[2:0] x=0, Next state Y[2:0] x=1 | Output z
+   Present state input y[2:0] | Next state Y[2:0] when x=0, Next state Y[2:0] when x=1 | Output z
    000 | 000, 001 | 0
    001 | 001, 100 | 0
    010 | 010, 001 | 0

dataset_code-complete-iccad2023/Prob143_fsm_onehot_test.sv

@@ -26,11 +26,6 @@ module stimulus_gen (
 		#1;
 	endtask	
 
-
-
-	int errored1 = 0;
-	int errored2 = 0;
-	int onehot_error = 0;
 	reg [9:0] state_error = 10'h0;
 
 	initial begin
@@ -59,35 +54,8 @@ module stimulus_gen (
 		repeat(200) @(posedge clk, negedge clk) begin
 			state <= 1<< ($unsigned($random) % 10);
 			in <= $random;
-			if (!tb_match) onehot_error++;
-		end
-		
-		// Two-hot.
-		errored1 = 0;
-		repeat(400) @(posedge clk, negedge clk) begin
-			state <= (1<< ($unsigned($random) % 10)) | (1<< ($unsigned($random) % 10));
-			in <= $random;
-			if (!tb_match)
-				errored1++;
 		end
 
-		if (!onehot_error && errored1) 
-			$display ("Hint: Your circuit passed when given only one-hot inputs, but not with two-hot inputs.");
-		
-		// Random.
-		errored2 = 0;
-		repeat(800) @(posedge clk, negedge clk) begin
-			state <= $random;
-			in <= $random;
-			if (!tb_match)
-				errored2++;
-		end
-		if (!onehot_error && errored2) 
-			$display ("Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.");
-
-		if (!onehot_error && (errored1 || errored2))
-			$display("Hint: Are you doing something more complicated than deriving state transition equations by inspection?\n");
-		
 		for (int i=0;i<$bits(state_error);i++)
 			$display("Hint: next_state[%0d] is %s.", i, (state_error[i] === 1'b0) ? "correct": "incorrect");
 

dataset_code-complete-iccad2023/Prob145_circuit8_prompt.txt

@@ -2,46 +2,46 @@
 This is a sequential circuit. Read the simulation waveforms to determine
 what the circuit does, then implement it.
 
-  time   clk a   p   q
-  0ns    0   0   x   x
-  5ns    0   0   x   x
-  10ns   0   0   x   x
-  15ns   0   0   x   x
-  20ns   0   0   x   x
-  25ns   1   0   0   x
-  30ns   1   0   0   x
-  35ns   1   0   0   x
-  40ns   1   0   0   x
-  45ns   1   0   0   x
-  50ns   1   0   0   x
-  55ns   0   0   0   0
-  60ns   0   0   0   0
-  65ns   0   0   0   0
-  70ns   0   1   0   0
-  75ns   0   0   0   0
-  80ns   0   1   0   0
-  85ns   1   0   0   0
-  90ns   1   1   1   0
-  95ns   1   0   0   0
-  100ns  1   1   1   0
-  105ns  1   0   0   0
-  110ns  1   1   1   0
-  115ns  0   0   1   1
-  120ns  0   1   1   1
-  125ns  0   0   1   1
-  130ns  0   1   1   1
-  135ns  0   0   1   1
-  140ns  0   0   1   1
-  145ns  1   0   0   1
-  150ns  1   0   0   1
-  155ns  1   0   0   1
-  160ns  1   0   0   1
-  165ns  1   1   1   1
-  170ns  1   0   0   1
-  175ns  0   1   0   0
-  180ns  0   0   0   0
-  185ns  0   1   0   0
-  190ns  0   0   0   0
+  time   clock  a   p   q
+  0ns    0      0   x   x
+  5ns    0      0   x   x
+  10ns   0      0   x   x
+  15ns   0      0   x   x
+  20ns   0      0   x   x
+  25ns   1      0   0   x
+  30ns   1      0   0   x
+  35ns   1      0   0   x
+  40ns   1      0   0   x
+  45ns   1      0   0   x
+  50ns   1      0   0   x
+  55ns   0      0   0   0
+  60ns   0      0   0   0
+  65ns   0      0   0   0
+  70ns   0      1   0   0
+  75ns   0      0   0   0
+  80ns   0      1   0   0
+  85ns   1      0   0   0
+  90ns   1      1   1   0
+  95ns   1      0   0   0
+  100ns  1      1   1   0
+  105ns  1      0   0   0
+  110ns  1      1   1   0
+  115ns  0      0   1   1
+  120ns  0      1   1   1
+  125ns  0      0   1   1
+  130ns  0      1   1   1
+  135ns  0      0   1   1
+  140ns  0      0   1   1
+  145ns  1      0   0   1
+  150ns  1      0   0   1
+  155ns  1      0   0   1
+  160ns  1      0   0   1
+  165ns  1      1   1   1
+  170ns  1      0   0   1
+  175ns  0      1   0   0
+  180ns  0      0   0   0
+  185ns  0      1   0   0
+  190ns  0      0   0   0
 
 module TopModule (
   input clock,

dataset_code-complete-iccad2023/Prob150_review2015_fsmonehot_prompt.txt

@@ -3,22 +3,24 @@ Given the following Moore state machine with 3 input (d, done_counting,
 ack) and 3 outputs (shift_ena, counting, done). Unless otherwise stated in
 the diagram below, assume outputs are 0 and inputs are don't cares.
 
-  S () --d=0--> S
-  S () --d=1--> S1
-  S1 () --d=0--> S
-  S1 () --d=1--> S11
-  S11 () --d=0--> S110
-  S11 () --d=1--> S11
-  S110 () --d=0--> S
-  S110 () --d=1--> B0
-  B0 (shift_ena=1) -- (always go to next cycle) --> B1
-  B1 (shift_ena=1) -- (always go to next cycle) --> B2
-  B2 (shift_ena=1) -- (always go to next cycle) --> B3
-  B3 (shift_ena=1) -- (always go to next cycle) --> Count
-  Count (counting=1) --!(done_counting)--> Count
-  Count (counting=1) --(done_counting)--> Wait
-  Wait (done=1) --ack=0--> Wait
-  Wait (done=1) --ack=1--> S
+state   (output)      --input--> next state
+-------------------------------------------
+  S     ()            --d=0--> S
+  S     ()            --d=1--> S1
+  S1    ()            --d=0--> S
+  S1    ()            --d=1--> S11
+  S11   ()            --d=0--> S110
+  S11   ()            --d=1--> S11
+  S110  ()            --d=0--> S
+  S110  ()            --d=1--> B0
+  B0    (shift_ena=1) --(always go to next cycle)--> B1
+  B1    (shift_ena=1) --(always go to next cycle)--> B2
+  B2    (shift_ena=1) --(always go to next cycle)--> B3
+  B3    (shift_ena=1) --(always go to next cycle)--> Count
+  Count (counting=1)  --done_counting=0--> Count
+  Count (counting=1)  --done_counting=1--> Wait
+  Wait  (done=1)      --ack=0--> Wait
+  Wait  (done=1)      --ack=1--> S
 
 At reset, the state machine starts in state "S". Derive next-state logic
 equations and output logic equations by inspection assuming the following
@@ -29,16 +31,16 @@ Derive state transition and output logic equations by inspection assuming
 a one-hot encoding. Implement only the state transition logic and output
 logic (the combinational logic portion) for this state machine.
 
-Write code that generates the following equations:
+Write code that generates the following signals:
 
-  - B3_next -- next-state logic for state B3
-  - S_next
-  - S1_next
-  - Count_next
-  - Wait_next
-  - done -- output logic
-  - counting
-  - shift_ena
+ - B3_next -- Assert when next-state is B3 state
+ - S_next -- Assert when next-state is S state
+ - S1_next -- Assert when next-state is S1 state
+ - Count_next -- Assert when next-state is Count state
+ - Wait_next -- Assert when next-state is Wait state
+ - done -- output logic
+ - counting -- output logic
+ - shift_ena -- output logic
 
 module TopModule (
   input d,