Basic FPGA demo circuits made in Verilog HDL, VHDL and SystemVerilog
0 - blink 1 - led counter 2 - led shiffter 3 - button 4 - hamming code 5 - button modes 6 - semaphore 7 - 7 segment 8 - 7 segment semaphore 9 - simple clock 10 - sum 11 - calculator
The official language adopted by the project is Brazilian Portuguese; therefore, most of the documentation and commits are in this language.
If you'd like to contribute to the project, please feel free to do so. The CONTRIBUTING.md file contains the necessary instructions.
This project is licensed under the MIT license, which grants full freedom for use.