From 5eb4190ece5ac9bd6d8e628eb0b0e45b3adbc0e0 Mon Sep 17 00:00:00 2001
From: rishijain01 <41798222+rishijain01@users.noreply.github.com>
Date: Wed, 2 Oct 2019 12:46:30 +0530
Subject: [PATCH 1/2] Create decoder_3_8

---
 .../decoder_3_8"                              | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 "Project 2 \342\200\223 Combinational Logic/decoder_3_8"

diff --git "a/Project 2 \342\200\223 Combinational Logic/decoder_3_8" "b/Project 2 \342\200\223 Combinational Logic/decoder_3_8"
new file mode 100644
index 0000000..d9990dc
--- /dev/null
+++ "b/Project 2 \342\200\223 Combinational Logic/decoder_3_8"	
@@ -0,0 +1,32 @@
+module decoder3_8(s,d);
+input [2:0] s;
+output reg [7:0] d;
+
+always@(s)
+begin
+case(s)
+
+
+3'b000 : d=8'b00000001;
+
+3'b001 : d=8'b00000010;
+
+3'b010 : d=8'b00000100;
+
+3'b011 : d=8'b00001000;
+
+3'b100 : d=8'b00010000;
+
+3'b101 : d=8'b00100000;
+
+3'b110 : d=8'b01000000;
+
+3'b111 : d=8'b10000000;
+
+
+endcase 
+
+end 
+
+    
+endmodule

From c0c25ea67c13ff4e592cbc8d4f7c88ff0df4b973 Mon Sep 17 00:00:00 2001
From: rishijain01 <41798222+rishijain01@users.noreply.github.com>
Date: Wed, 2 Oct 2019 12:49:20 +0530
Subject: [PATCH 2/2] 4 BIT ALU

---
 4 bit ALU | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 4 bit ALU

diff --git a/4 bit ALU b/4 bit ALU
new file mode 100644
index 0000000..bfcd453
--- /dev/null
+++ b/4 bit ALU	
@@ -0,0 +1,66 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 06/14/2019 04:04:29 PM
+// Design Name: 
+// Module Name: alu_checker
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// Author : Rishi Jain
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module alu_checker(a,b,oper,opcode,s,z,p,out);
+    
+     input [3:0] a;
+    input [3:0] b;
+    input oper;
+    input [1:0] opcode;
+    output  s,z,p;
+    output reg [7:0] out;   
+    
+    always@(opcode or oper)
+    begin
+    if(oper==0)
+    begin
+    case(opcode)
+    
+    2'b00 : out = a+b;
+    2'b01 : out =  a-b;
+    2'b10 : out= a/b;
+    2'b11 : out= a*b ;
+    
+    endcase
+    end
+    
+    else if(oper==1)
+    begin
+    case(opcode)
+    
+    2'b00 : out= a | b;
+    2'b01 : out = a&b;
+    2'b10 : out = a^b;
+    2'b11 : out = (~(a^b)) ;
+ 
+    endcase
+    end 
+ end
+ 
+assign s = out[7];
+assign z = ~|(out);
+assign p = ^(out);
+
+
+endmodule
+