Created

Author: wsnyder

.gitignore

@@ -0,0 +1,41 @@
+# Compiled Object files
+*.slo
+*.lo
+*.o
+*.obj
+
+# Precompiled Headers
+*.gch
+*.pch
+
+# Compiled Dynamic libraries
+*.so
+*.dylib
+*.dll
+
+# Fortran module files
+*.mod
+
+# Compiled Static libraries
+*.lai
+*.la
+*.a
+*.lib
+
+# Verilator/simulator temporaries
+*.dmp
+*.log
+*.csrc
+*.vcd
+obj_*
+logs
+
+# Executables
+*.exe
+*.out
+*.app
+*.gcda
+*.gcov
+*.gcno
+*qmake_gcov
+*.pro.user

.travis.yml

@@ -0,0 +1,17 @@
+language: cpp
+dist: focal
+os: linux
+compiler: gcc
+#cache: ccache
+
+services:
+  - docker
+
+# This uses the latest version of Verilator, you may prefer :stable
+# We run make from inside the container, overriding default entry point (Verilator binary itself)
+# You may prefer to build install Verilator from git locally (slower but avoids docker)
+script: 
+  - docker run -ti -v ${PWD}:/work --user $(id -u):$(id -g) -e CCACHE_DIR=/work/.ccache --entrypoint make verilator/verilator:latest
+
+after_success: 
+  - bash <(curl -s https://codecov.io/bash)

Codecov.png

@@ -0,0 +1,107 @@
+######################################################################
+#
+# DESCRIPTION: Make Verilator model and run coverage
+#
+# This calls the object directory makefile.  That allows the objects to
+# be placed in the "current directory" which simplifies the Makefile.
+#
+# This file is placed under the Creative Commons Public Domain, for
+# any use, without warranty, 2020 by Wilson Snyder.
+# SPDX-License-Identifier: CC0-1.0
+#
+######################################################################
+
+ifneq ($(words $(CURDIR)),1)
+ $(error Unsupported: GNU Make cannot build in directories containing spaces, build elsewhere: '$(CURDIR)')
+endif
+
+# This example started with the Verilator example files.
+# Please see those examples for commented sources, here:
+# https://github.com/verilator/verilator/tree/master/examples
+
+######################################################################
+# Set up variables
+
+# If $VERILATOR_ROOT isn't in the environment, we assume it is part of a
+# package install, and verilator is in your path. Otherwise find the
+# binary relative to $VERILATOR_ROOT (such as when inside the git sources).
+ifeq ($(VERILATOR_ROOT),)
+VERILATOR = verilator
+VERILATOR_COVERAGE = verilator_coverage
+else
+export VERILATOR_ROOT
+VERILATOR = $(VERILATOR_ROOT)/bin/verilator
+VERILATOR_COVERAGE = $(VERILATOR_ROOT)/bin/verilator_coverage
+endif
+
+VERILATOR_FLAGS =
+# Generate C++ in executable form
+VERILATOR_FLAGS += -cc --exe
+# Generate makefile dependencies (not shown as complicates the Makefile)
+#VERILATOR_FLAGS += -MMD
+# Optimize
+VERILATOR_FLAGS += -Os -x-assign 0
+# Warn abount lint issues; may not want this on less solid designs
+VERILATOR_FLAGS += -Wall
+# Make waveforms
+#VERILATOR_FLAGS += --trace
+# Check SystemVerilog assertions
+VERILATOR_FLAGS += --assert
+# Generate coverage analysis
+VERILATOR_FLAGS += --coverage
+# Run make to compile model, with as many CPUs as are free
+VERILATOR_FLAGS += --build -j
+# Run Verilator in debug mode
+#VERILATOR_FLAGS += --debug
+# Add this trace to get a backtrace in gdb
+#VERILATOR_FLAGS += --gdbbt
+
+# Input files for Verilator
+VERILATOR_INPUT = -f input.vc top.v sim_main.cpp
+
+######################################################################
+
+# Create annotated source
+VERILATOR_COV_FLAGS += --annotate logs/annotated
+# A single coverage hit is considered good enough
+VERILATOR_COV_FLAGS += --annotate-min 1
+# Create LCOV info
+VERILATOR_COV_FLAGS += --write-info logs/coverage.info
+# Input file from Verilator
+VERILATOR_COV_FLAGS += logs/coverage.dat
+
+######################################################################
+default: run
+
+run:
+	@echo
+	@echo "-- Verilator coverage example"
+
+	@echo
+	@echo "-- VERILATE ----------------"
+	$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_INPUT)
+
+	@echo
+	@echo "-- RUN ---------------------"
+	@rm -rf logs
+	@mkdir -p logs
+	obj_dir/Vtop
+
+	@echo
+	@echo "-- COVERAGE ----------------"
+	@rm -rf logs/annotated
+	$(VERILATOR_COVERAGE) $(VERILATOR_COV_FLAGS)
+
+	@echo
+	@echo "-- DONE --------------------"
+
+
+######################################################################
+# Other targets
+
+show-config:
+	$(VERILATOR) -V
+
+maintainer-copy::
+clean mostlyclean distclean maintainer-clean::
+	-rm -rf obj_dir logs *.log *.dmp *.vpd core

LICENSE

@@ -0,0 +1,21 @@
+# travis_verilator_gcov
+
+[![Travis CI logo](TravisCI.png)](https://travis-ci.org)
+![Whitespace](Whitespace.png)
+[![Codecov logo](Codecov.png)](https://www.codecov.io)
+![Whitespace](Whitespace.png)
+[![Verilator logo](verilator_56x48-min.png)](https://verilator.org)
+
+[![Build Status](https://travis-ci.org/verilator/example-systemverilog.svg?branch=master)](https://travis-ci.org/verilator/example-systemverilog)
+[![codecov.io](https://codecov.io/github/verilator/example-systemverilog/coverage.svg?branch=master)](https://codecov.io/github/verilator/example-systemverilog?branch=master)
+
+This GitHub is part of [the SystemVerilog Verilator Codecov Tutorial](https://github.com/verilator/example-systemverilog).
+
+The goal of this project is to demonstrate a SystemVerilog project with:
+ * Verilator
+ * C++ compiler: `g++`
+ * Travis-CI running Docker
+ * Code coverage with `verilator_coverage` (note: it should show the code coverage is below 100%)
+ * Code coverage published in CodeCov.
+
+We are happy to help if you have any questions. Please contact email our Support at [support@codecov.io](mailto:support@codecov.io)

Makefile

@@ -0,0 +1,3 @@
+#!/bin/bash
+qmake travis_qmake_gcc_cpp11_gcov.pro
+make

README.md

@@ -0,0 +1,2 @@
+// This file typically lists flags required by a large project, e.g. include directories
++libext+.v+.sv+.vh+.svh -y .

TravisCI.png

@@ -0,0 +1,56 @@
+// DESCRIPTION: Verilator: Verilog example module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2017 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+//======================================================================
+
+#include <verilated.h>
+
+#include "Vtop.h"
+
+vluint64_t main_time = 0;
+double sc_time_stamp() {
+    return main_time;  // Note does conversion to real, to match SystemC
+}
+
+int main(int argc, char** argv, char** env) {
+    // This example started with the Verilator example files.
+    // Please see those examples for commented sources, here:
+    // https://github.com/verilator/verilator/tree/master/examples
+
+    if (0 && argc && argv && env) {}
+
+    Verilated::debug(0);
+    Verilated::randReset(2);
+    Verilated::traceEverOn(true);
+    Verilated::commandArgs(argc, argv);
+    Verilated::mkdir("logs");
+
+    Vtop* top = new Vtop;  // Or use a const unique_ptr, or the VL_UNIQUE_PTR wrapper
+
+    top->clk = 0;
+    while (!Verilated::gotFinish()) {
+        ++main_time;
+        top->clk = !top->clk;
+        top->reset = (main_time < 10) ? 1 : 0;
+        if (main_time < 5) {
+            // Zero coverage if still early in reset, otherwise toggles there may
+            // falsely indicate a signal is covered
+            VerilatedCov::zero();
+        }
+        top->eval();
+    }
+
+    top->final();
+
+    //  Coverage analysis (since test passed)
+#if VM_COVERAGE
+    Verilated::mkdir("logs");
+    VerilatedCov::write("logs/coverage.dat");
+#endif
+
+    delete top;
+    top = NULL;
+    exit(0);
+}

Whitespace.png

@@ -0,0 +1,49 @@
+// DESCRIPTION: Verilator: Verilog example module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2003 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+// ======================================================================
+
+module top
+  (input logic clk,
+   input logic reset);
+
+   // Create 100 cycles of example stimulus
+   reg [31:0] count_c;
+   always_ff @ (posedge clk) begin
+      //$display("[%0t] clk=%b reset=%b", $time, clk, reset);
+      if (reset) begin
+	 count_c <= 0;
+      end
+      else begin
+	 count_c <= count_c + 1;
+	 if (count_c >= 99) begin
+            $write("*-* All Finished *-*\n");
+            $finish;
+	 end
+      end
+   end
+
+   // Example coverage analysis
+   cover property (@(posedge clk) count_c == 30);  // Hit
+   cover property (@(posedge clk) count_c == 300);  // Not covered
+
+   // Example toggle analysis
+   wire count_hit_50;  // Hit
+   wire count_hit_500;  // Not covered
+
+   assign count_hit_50 = (count_c == 50);
+   assign count_hit_500 = (count_c == 500);
+
+   // Example line and block coverage
+   always_comb begin
+      if (count_hit_50) begin  // Hit	
+         $write("[%0t] got 50\n", $time);  // Hit
+      end
+      if (count_hit_500) begin  // Not covered
+         $write("[%0t] got 600\n", $time);  // Not covered
+      end
+   end
+
+endmodule