RTL data structure
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May 24, 2025 - SystemVerilog
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system-verilog
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HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design
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Jan 28, 2025 - SystemVerilog
Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
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Mar 13, 2024 - SystemVerilog
AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.
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Mar 22, 2017 - SystemVerilog
A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL
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Jun 5, 2023 - SystemVerilog
16 bit serial multiplier in SystemVerilog
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Oct 13, 2018 - SystemVerilog
Synthesizable SystemVerilog IP-Core of the I2S Receiver
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Jun 7, 2020 - SystemVerilog
UVM Test bench for a 8-bit ALU
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Dec 24, 2020 - SystemVerilog
Pulse Width Modulator programmed through an Advanced Peripheral Bus interface
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May 15, 2018 - SystemVerilog
Quartus II project for a basic interface for writing in a LCD screen using a PS2 keyboard using Altera DE2-70 board
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Oct 30, 2017 - SystemVerilog
RISC-V five stage pipline CPU
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Jul 26, 2019 - SystemVerilog
A systemverilog implementation of the data structures: priority queue, queue and stack
system stack hardware open-hardware priority-queue data-structures rtl verilog systemverilog fifo hdl system-verilog hardware-description-language
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Apr 2, 2020 - SystemVerilog
This testbench is based on SV and UVM Class based to verify Verilog HDL Design
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Mar 23, 2023 - SystemVerilog
Proyecto Final para el curso de Taller de Diseño Digital. La idea es hacer un procesador uniciclo para procesar un texto utilizando los lenguajes de programación ARM, Python y SystemVerilog.
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May 5, 2022 - SystemVerilog
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Dec 11, 2017 - SystemVerilog
An FPGA-based Chess Engine and TPU
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Feb 9, 2023 - SystemVerilog
Verilog Codes for various Design
pipeline multiplication verilog fifo uvm adder system-verilog verilog-hdl max-pooling sequence-detector one-detector reconfigurable-matrix-adder
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Nov 24, 2023 - SystemVerilog
Multiple DUT with parallel stimulus
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Sep 13, 2019 - SystemVerilog
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
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Jun 6, 2020 - SystemVerilog
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