@@ -150,7 +150,7 @@ static void __attribute__((noinline))
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{
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uint32_t lo, hi;
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- asm volatile (" rdtsc" : " =a" (lo), " =d" (hi));
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+ __asm__ __volatile__ (" rdtsc" : " =a" (lo), " =d" (hi));
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return (uint64_t )hi << 32 | lo;
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}
@@ -245,7 +245,7 @@ static void __attribute__((noinline))
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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- asm volatile (" " );
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+ __asm__ __volatile__ (" " );
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}
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print_result (s, " Empty loop:" );
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@@ -374,69 +374,69 @@ static void __attribute__((noinline))
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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- asm (" nop" );
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+ __asm__ __volatile__ (" nop" );
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}
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print_result (s, " raw 'nop':" );
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#if defined(__i386__) || defined(__x86_64__)
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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- asm (" pause" );
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+ __asm__ __volatile__ (" pause" );
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}
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print_result (s, " raw 'pause':" );
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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- asm (" mfence" );
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+ __asm__ __volatile__ (" mfence" );
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}
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print_result (s, " Atomic mfence:" );
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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- asm (" lfence" );
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+ __asm__ __volatile__ (" lfence" );
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}
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print_result (s, " Atomic lfence:" );
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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- asm (" sfence" );
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+ __asm__ __volatile__ (" sfence" );
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}
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print_result (s, " Atomic sfence:" );
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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uint64_t sidt_rval;
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- asm (" sidt %0" : " =m" (sidt_rval));
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+ __asm__ __volatile__ (" sidt %0" : " =m" (sidt_rval));
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}
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print_result (s, " 'sidt' instruction:" );
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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long prev;
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- asm volatile (" cmpxchg %1,%2"
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+ __asm__ __volatile__ (" cmpxchg %1,%2"
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: " =a" (prev) : " r" (0l ), " m" (global), " 0" (1l ));
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}
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print_result (s, " 'cmpxchg' without the 'lock' prefix:" );
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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global = 0 ;
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- asm volatile (" mfence" ::: " memory" );
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+ __asm__ __volatile__ (" mfence" ::: " memory" );
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}
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print_result (s, " Store + mfence:" );
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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unsigned long _clbr;
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#ifdef __LP64__
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- asm volatile (" cpuid" : " =a" (_clbr)
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+ __asm__ __volatile__ (" cpuid" : " =a" (_clbr)
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: " 0" (0 ) : " rbx" , " rcx" , " rdx" , " cc" , " memory" );
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#else
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#ifdef __llvm__
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- asm volatile (" cpuid" : " =a" (_clbr) : " 0" (0 )
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+ __asm__ __volatile__ (" cpuid" : " =a" (_clbr) : " 0" (0 )
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: " ebx" , " ecx" , " edx" , " cc" , " memory" );
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#else // gcc does not allow inline i386 asm to clobber ebx
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- asm volatile (" pushl %%ebx\n\t cpuid\n\t popl %%ebx"
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+ __asm__ __volatile__ (" pushl %%ebx\n\t cpuid\n\t popl %%ebx"
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: " =a" (_clbr) : " 0" (0 ) : " ecx" , " edx" , " cc" , " memory" );
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#endif
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#endif
@@ -454,35 +454,35 @@ asm volatile("pushl %%ebx\n\tcpuid\n\tpopl %%ebx"
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#ifdef _ARM_ARCH_7
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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- asm (" yield" );
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+ __asm__ __volatile__ (" yield" );
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}
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print_result (s, " raw 'yield':" );
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#endif
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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#ifdef _ARM_ARCH_7
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- asm volatile (" dmb ish" : : : " memory" );
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+ __asm__ __volatile__ (" dmb ish" : : : " memory" );
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#else
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- asm volatile (" mcr p15, 0, %0, c7, c10, 5" : : " r" (0 ) : " memory" );
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+ __asm__ __volatile__ (" mcr p15, 0, %0, c7, c10, 5" : : " r" (0 ) : " memory" );
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#endif
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}
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print_result (s, " 'dmb ish' instruction:" );
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#ifdef _ARM_ARCH_7
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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- asm volatile (" dmb ishst" : : : " memory" );
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+ __asm__ __volatile__ (" dmb ishst" : : : " memory" );
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}
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print_result (s, " 'dmb ishst' instruction:" );
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#endif
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#ifdef _ARM_ARCH_7
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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- asm volatile (" str %[_r], [%[_p], %[_o]]" :
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+ __asm__ __volatile__ (" str %[_r], [%[_p], %[_o]]" :
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: [_p] " p" (&global), [_o] " M" (0 ), [_r] " r" (0 ) : " memory" );
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- asm volatile (" dmb ishst" : : : " memory" );
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+ __asm__ __volatile__ (" dmb ishst" : : : " memory" );
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}
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print_result (s, " 'str + dmb ishst' instructions:" );
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#endif
@@ -493,10 +493,10 @@ asm volatile("str %[_r], [%[_p], %[_o]]" :
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uintptr_t prev;
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uint32_t t;
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do {
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- asm volatile (" ldrex %[_r], [%[_p], %[_o]]"
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+ __asm__ __volatile__ (" ldrex %[_r], [%[_p], %[_o]]"
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: [_r] " =&r" (prev) \
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: [_p] " p" (&global), [_o] " M" (0 ) : " memory" );
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- asm volatile (" strex %[_t], %[_r], [%[_p], %[_o]]"
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+ __asm__ __volatile__ (" strex %[_t], %[_r], [%[_p], %[_o]]"
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: [_t] " =&r" (t) \
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: [_p] " p" (&global), [_o] " M" (0 ), [_r] " r" (0 ) : " memory" );
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} while (t);
@@ -507,26 +507,26 @@ asm volatile("strex %[_t], %[_r], [%[_p], %[_o]]"
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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#ifdef _ARM_ARCH_7
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- asm volatile (" dsb ish" : : : " memory" );
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+ __asm__ __volatile__ (" dsb ish" : : : " memory" );
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#else
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- asm volatile (" mcr p15, 0, %0, c7, c10, 4" : : " r" (0 ) : " memory" );
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+ __asm__ __volatile__ (" mcr p15, 0, %0, c7, c10, 4" : : " r" (0 ) : " memory" );
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#endif
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}
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print_result (s, " 'dsb ish' instruction:" );
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#if BENCH_SLOW
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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- register long _swtch_pri asm (" ip" ) = -59 ;
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- asm volatile (" svc 0x80" : : " r" (_swtch_pri) : " r0" , " memory" );
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+ register long _swtch_pri __asm__ (" ip" ) = -59 ;
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+ __asm__ __volatile__ (" svc 0x80" : : " r" (_swtch_pri) : " r0" , " memory" );
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}
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print_result (s, " swtch_pri syscall:" );
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s = mach_absolute_time ();
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for (i = cnt; i; i--) {
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- register long _r0 asm (" r0" ) = 0 , _r1 asm (" r1" ) = 1 , _r2 asm (" r2" ) = 1 ;
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- register long _thread_switch asm (" ip" ) = -61 ;
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- asm volatile (" svc 0x80" : " +r" (_r0)
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+ register long _r0 __asm__ (" r0" ) = 0 , _r1 __asm__ (" r1" ) = 1 , _r2 __asm__ (" r2" ) = 1 ;
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+ register long _thread_switch __asm__ (" ip" ) = -61 ;
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+ __asm__ __volatile__ (" svc 0x80" : " +r" (_r0)
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: " r" (_r1), " r" (_r2), " r" (_thread_switch): " memory" );
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}
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print_result (s, " thread_switch syscall:" );
@@ -636,9 +636,9 @@ asm volatile("svc 0x80" : "+r" (_r0)
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while (!__sync_bool_compare_and_swap (&global, 0 , 1 )) {
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do {
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#if defined(__i386__) || defined(__x86_64__)
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- asm (" pause" );
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+ __asm__ __volatile__ (" pause" );
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#elif defined(__arm__) && defined _ARM_ARCH_7
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- asm (" yield" );
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+ __asm__ __volatile__ (" yield" );
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#endif
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} while (global);
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}
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