From 3667312388d33fd08993bb9fc819db4613f463ab Mon Sep 17 00:00:00 2001 From: Alexandre Bourdiol Date: Wed, 15 Dec 2021 10:16:26 +0100 Subject: [PATCH 1/2] HardwareTimer: NonReg: Fix spelling Signed-off-by: Alexandre Bourdiol --- .../HardwareTimer_OutputInput_test.ino | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/examples/NonReg/HardwareTimer/HardwareTimer_OutputInput_test/HardwareTimer_OutputInput_test.ino b/examples/NonReg/HardwareTimer/HardwareTimer_OutputInput_test/HardwareTimer_OutputInput_test.ino index 772de58..8bd8149 100644 --- a/examples/NonReg/HardwareTimer/HardwareTimer_OutputInput_test/HardwareTimer_OutputInput_test.ino +++ b/examples/NonReg/HardwareTimer/HardwareTimer_OutputInput_test/HardwareTimer_OutputInput_test.ino @@ -8,9 +8,9 @@ Designed to work on Nucleo_L476RG TIM1 ch1N and ch2 are used for output generation (TIM1_CH1N_PIN, and TIM1_CH2_PIN). It is important that both channel are on the same timer, in order to check influence on channel dependant API. - Management of interruption is done with variable incrementation. - TIM8 ch1/ch2 are used to measure frequence and duty cycle of TIM1_CH1N output generated signal - TIM8 ch3/ch4 are used to measure frequence and duty cycle of TIM1_CH2 output generated signal + Management of interruption is done with variable increment. + TIM8 ch1/ch2 are used to measure frequency and duty cycle of TIM1_CH1N output generated signal + TIM8 ch3/ch4 are used to measure frequency and duty cycle of TIM1_CH2 output generated signal Regular channel and complementary channel (TIM1_CH1N) are tested. @@ -61,7 +61,7 @@ #define OUTPUT_DUTY1 20 // percentage #define OUTPUT_DUTY2 30 // percentage -#define TEMPO_BEFORE_MEASUREMENT 500 // milisecondes +#define TEMPO_BEFORE_MEASUREMENT 500 // millisecondes #define TOLERANCE 10 // Percentage #define EXPECTED_INTERRUPT_COUNT ((TEMPO_BEFORE_MEASUREMENT * OUTPUT_FREQUENCY) / 1000) @@ -594,4 +594,4 @@ void loop() while (1) { }; -} \ No newline at end of file +} From ee1f536e67f1ea97b93a0b2abb0fb821fa5b5faa Mon Sep 17 00:00:00 2001 From: Alexandre Bourdiol Date: Wed, 15 Dec 2021 10:19:55 +0100 Subject: [PATCH 2/2] HardwareTimer: NonReg: Fix TIM8 Pin definition Due to changes in PeripheralPins.c of nucleo_l476rg, it is necessary to adapt the sketch to match the right pin definition Signed-off-by: Alexandre Bourdiol --- .../HardwareTimer_OutputInput_test.ino | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/NonReg/HardwareTimer/HardwareTimer_OutputInput_test/HardwareTimer_OutputInput_test.ino b/examples/NonReg/HardwareTimer/HardwareTimer_OutputInput_test/HardwareTimer_OutputInput_test.ino index 8bd8149..12a499b 100644 --- a/examples/NonReg/HardwareTimer/HardwareTimer_OutputInput_test/HardwareTimer_OutputInput_test.ino +++ b/examples/NonReg/HardwareTimer/HardwareTimer_OutputInput_test/HardwareTimer_OutputInput_test.ino @@ -49,11 +49,11 @@ #define Output2_channel 2 // TIM input -#define TIM8_CH1_PIN PC6 // CN10 pin 4 Use also channel2 for freq/duty measurement +#define TIM8_CH1_PIN PC_6_ALT1 // CN10 pin 4 Use also channel2 for freq/duty measurement #define Freq1_channelRising 1 #define Freq1_channelFalling 2 -#define TIM8_CH3_PIN PC8 // CN10 pin 2 Use also channel4 for freq/duty measurement +#define TIM8_CH3_PIN PC_8_ALT1 // CN10 pin 2 Use also channel4 for freq/duty measurement #define Freq2_channelRising 3 #define Freq2_channelFalling 4