From 65ef1908a11b6fa934455d32ee1233b5a9321420 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 12 Feb 2020 14:03:56 +0100 Subject: [PATCH 1/6] [MP1] Update STM32MP1xx HAL Drivers to v1.2.0 Included in STM32CubeMP1 FW V1.2.0 Note: dos2unix applied on all files Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 179 +- .../Inc/stm32mp1xx_hal_adc.h | 8 +- .../Inc/stm32mp1xx_hal_conf_template.h | 14 + .../Inc/stm32mp1xx_hal_qspi.h | 0 .../Inc/stm32mp1xx_hal_rtc.h | 959 ++++ .../Inc/stm32mp1xx_hal_rtc_ex.h | 1598 ++++++ .../Inc/stm32mp1xx_hal_sd.h | 0 .../Inc/stm32mp1xx_hal_sd_ex.h | 0 .../Inc/stm32mp1xx_hal_sram.h | 222 + .../Inc/stm32mp1xx_hal_uart.h | 185 +- .../Inc/stm32mp1xx_hal_uart_ex.h | 94 +- .../Inc/stm32mp1xx_ll_adc.h | 105 +- .../Inc/stm32mp1xx_ll_cortex.h | 311 ++ .../Inc/stm32mp1xx_ll_fmc.h | 542 ++ .../Inc/stm32mp1xx_ll_gpio.h | 16 +- .../Inc/stm32mp1xx_ll_rcc.h | 4 + .../Inc/stm32mp1xx_ll_rtc.h | 4802 +++++++++++++++++ .../Inc/stm32mp1xx_ll_sdmmc.h | 0 .../Inc/stm32mp1xx_ll_tim.h | 7 +- .../Inc/stm32mp1xx_ll_utils.h | 4 + .../STM32MP1xx_HAL_Driver/Release_Notes.html | 418 +- .../Src/stm32mp1xx_hal.c | 11 +- .../Src/stm32mp1xx_hal_adc.c | 2 + .../Src/stm32mp1xx_hal_adc_ex.c | 21 +- .../Src/stm32mp1xx_hal_qspi.c | 0 .../Src/stm32mp1xx_hal_rtc.c | 1773 ++++++ .../Src/stm32mp1xx_hal_rtc_ex.c | 2472 +++++++++ .../Src/stm32mp1xx_hal_sd.c | 0 .../Src/stm32mp1xx_hal_sd_ex.c | 0 .../Src/stm32mp1xx_hal_sram.c | 1113 ++++ .../Src/stm32mp1xx_hal_uart.c | 782 ++- .../Src/stm32mp1xx_hal_uart_ex.c | 41 +- .../Src/stm32mp1xx_ll_fmc.c | 502 ++ .../Src/stm32mp1xx_ll_rtc.c | 878 +++ .../Src/stm32mp1xx_ll_sdmmc.c | 0 .../Src/stm32mp1xx_ll_tim.c | 2 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 37 files changed, 16400 insertions(+), 667 deletions(-) mode change 100644 => 100755 system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_qspi.h create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rtc.h create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rtc_ex.h mode change 100644 => 100755 system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sd.h mode change 100644 => 100755 system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sd_ex.h create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sram.h create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_cortex.h create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_fmc.h create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rtc.h mode change 100644 => 100755 system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_sdmmc.h mode change 100644 => 100755 system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rtc.c create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rtc_ex.c mode change 100644 => 100755 system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd.c mode change 100644 => 100755 system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd_ex.c create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sram.c create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_fmc.c create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_rtc.c mode change 100644 => 100755 system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_sdmmc.c diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 385174ed38..bb24db0309 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -236,12 +236,12 @@ #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) -#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH) -#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH) +#if defined(STM32G4) || defined(STM32H7) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -306,8 +306,17 @@ #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + #endif /* STM32L4 */ +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#endif + #if defined(STM32H7) #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 @@ -365,6 +374,9 @@ #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + #endif /* STM32H7 */ /** @@ -566,7 +578,14 @@ #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 -#endif + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 @@ -737,32 +756,65 @@ #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 #endif /* STM32H7 */ - + #if defined(STM32F3) -#define HRTIM_OUTPUTSET_TIMEV_1 HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 -#define HRTIM_OUTPUTSET_TIMEV_2 HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 -#define HRTIM_OUTPUTSET_TIMEV_3 HRTIM_OUTPUTSET_TIMAEV3_TIMBCMP4 -#define HRTIM_OUTPUTSET_TIMEV_4 HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2 -#define HRTIM_OUTPUTSET_TIMEV_5 HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3 -#define HRTIM_OUTPUTSET_TIMEV_6 HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1 -#define HRTIM_OUTPUTSET_TIMEV_7 HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2 -#define HRTIM_OUTPUTSET_TIMEV_8 HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3 -#define HRTIM_OUTPUTSET_TIMEV_9 HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4 - -#define HRTIM_OUTPUTRESET_TIMEV_1 HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 -#define HRTIM_OUTPUTRESET_TIMEV_2 HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 -#define HRTIM_OUTPUTRESET_TIMEV_3 HRTIM_OUTPUTRESET_TIMAEV3_TIMBCMP4 -#define HRTIM_OUTPUTRESET_TIMEV_4 HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2 -#define HRTIM_OUTPUTRESET_TIMEV_5 HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3 -#define HRTIM_OUTPUTRESET_TIMEV_6 HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1 -#define HRTIM_OUTPUTRESET_TIMEV_7 HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2 -#define HRTIM_OUTPUTRESET_TIMEV_8 HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3 -#define HRTIM_OUTPUTRESET_TIMEV_9 HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4 - -#define HRTIM_EVENTSRC_1 HRTIM_EEV1SRC_GPIO -#define HRTIM_EVENTSRC_2 HRTIM_EEV2SRC_GPIO -#define HRTIM_EVENTSRC_3 HRTIM_EEV3SRC_GPIO -#define HRTIM_EVENTSRC_4 HRTIM_EEV4SRC_GPIO +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the events that can be selected to configure the + * set/reset crossbar of a timer output + */ +#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) +#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) +#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) +#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) +#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) +#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) +#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) +#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) +#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) + +#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) +#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) +#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) +#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) +#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) +#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) +#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) +#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) +#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) + +/** @brief Constants defining the event filtering applied to external events + * by a timer + */ +#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + #endif /* STM32F3 */ /** * @} @@ -903,7 +955,7 @@ #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -994,6 +1046,16 @@ #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT + +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL +#endif /* STM32H7 */ + /** * @} */ @@ -1387,6 +1449,30 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1409,12 +1495,12 @@ #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode -#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7A3xxQ || STM32H7B3xxQ */ +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ /** * @} @@ -1445,16 +1531,18 @@ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32L6 */ +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ #if defined(STM32F4) #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT @@ -1473,6 +1561,13 @@ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown @@ -1545,14 +1640,14 @@ #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA -#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ /** * @} */ @@ -3386,9 +3481,9 @@ #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND /* alias CMSIS for compatibilities */ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler @@ -3656,9 +3751,9 @@ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32L4) +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE -#endif +#endif /* STM32L4 || STM32F4 || STM32F7 */ /** * @} */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h index a7961d1980..0eb482215e 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h @@ -624,10 +624,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management * @{ */ -#define ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000) /*!< Regular Conversion data stored in DR register only */ -#define ADC_CONVERSIONDATA_DFSDM ((uint32_t)ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */ -#define ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */ -#define ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)) /*!< DMA circular mode selected */ +#define ADC_CONVERSIONDATA_DR (0x00000000UL) /*!< Regular Conversion data stored in DR register only */ +#define ADC_CONVERSIONDATA_DFSDM (ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */ +#define ADC_CONVERSIONDATA_DMA_ONESHOT (ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */ +#define ADC_CONVERSIONDATA_DMA_CIRCULAR (ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1) /*!< DMA circular mode selected */ /** * @} */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_conf_template.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_conf_template.h index edc07c922e..7004397599 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_conf_template.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_conf_template.h @@ -55,6 +55,7 @@ #define HAL_QSPI_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED #define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED #define HAL_SAI_MODULE_ENABLED #define HAL_SD_MODULE_ENABLED #define HAL_SMBUS_MODULE_ENABLED @@ -153,6 +154,15 @@ #define CSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* CSI_VALUE */ +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ @@ -269,6 +279,10 @@ #include "stm32mp1xx_hal_rng.h" #endif /* HAL_RNG_MODULE_ENABLED */ +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32mp1xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + #ifdef HAL_SAI_MODULE_ENABLED #include "stm32mp1xx_hal_sai.h" #endif /* HAL_SAI_MODULE_ENABLED */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_qspi.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_qspi.h old mode 100644 new mode 100755 diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rtc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rtc.h new file mode 100644 index 0000000000..f049dc966b --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rtc.h @@ -0,0 +1,959 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_hal_rtc.h + * @author MCD Application Team + * @brief Header file of RTC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32MP1xx_HAL_RTC_H +#define STM32MP1xx_HAL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_hal_def.h" + +/** @addtogroup STM32MP1xx_HAL_Driver + * @{ + */ + +/** @defgroup RTC RTC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Types RTC Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ + +} HAL_RTCStateTypeDef; + +/** + * @brief RTC Configuration Structure definition + */ +typedef struct +{ + uint32_t HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ + + uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ + + uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. + This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ + + uint32_t OutPutRemap; /*!< Specifies the remap for RTC output. + This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */ + + uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. + This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ + + uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. + This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ + + uint32_t OutPutPullUp; /*!< Specifies the RTC Output Pull-Up mode. + This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */ +} RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hour. + This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. + This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ + + uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. + This parameter corresponds to a time unit range between [0-1] Second + with [1 Sec / SecondFraction +1] granularity */ + + uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content + corresponding to Synchronous pre-scaler factor value (PREDIV_S) + This parameter corresponds to a time unit range between [0-1] Second + with [1 Sec / SecondFraction +1] granularity. + This field will be used only by HAL_RTC_GetTime function */ + + uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. + This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ + + uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BKP bit + in CR register to store the operation. + This parameter can be a value of @ref RTC_StoreOperation_Definitions */ +} RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t Date; /*!< Specifies the RTC Date. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ + +} RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. + This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ + + uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. + If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint32_t Alarm; /*!< Specifies the alarm . + This parameter can be a value of @ref RTC_Alarms_Definitions */ +} RTC_AlarmTypeDef; + +/** + * @brief RTC Handle Structure definition + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +typedef struct __RTC_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ +{ + RTC_TypeDef *Instance; /*!< Legacy register base address. Not used anymore, the driver directly uses cmsis base address */ + + RTC_InitTypeDef Init; /*!< RTC required parameters */ + + HAL_LockTypeDef Lock; /*!< RTC locking object */ + + __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ + void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */ + void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */ + void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */ + void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ + void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */ + void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */ + void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 1 Event callback */ + void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 2 Event callback */ + void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 3 Event callback */ + void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 4 Event callback */ + void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 5 Event callback */ + void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 8 Event callback */ + void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ + void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ + +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + +} RTC_HandleTypeDef; + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RTC Callback ID enumeration definition + */ +typedef enum +{ + HAL_RTC_ALARM_A_EVENT_CB_ID = 0U, /*!< RTC Alarm A Event Callback ID */ + HAL_RTC_ALARM_B_EVENT_CB_ID = 1U, /*!< RTC Alarm B Event Callback ID */ + HAL_RTC_TIMESTAMP_EVENT_CB_ID = 2U, /*!< RTC TimeStamp Event Callback ID */ + HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 3U, /*!< RTC WakeUp Timer Event Callback ID */ + HAL_RTC_TAMPER1_EVENT_CB_ID = 4U, /*!< RTC Tamper 1 Callback ID */ + HAL_RTC_TAMPER2_EVENT_CB_ID = 5U, /*!< RTC Tamper 2 Callback ID */ + HAL_RTC_TAMPER3_EVENT_CB_ID = 6U, /*!< RTC Tamper 3 Callback ID */ + HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID = 12U, /*!< RTC Internal Tamper 1 Callback ID */ + HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID = 13U, /*!< RTC Internal Tamper 2 Callback ID */ + HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 14U, /*!< RTC Internal Tamper 3 Callback ID */ + HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 15U, /*!< RTC Internal Tamper 5 Callback ID */ + HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID = 16U, /*!< RTC Internal Tamper 8 Callback ID */ + HAL_RTC_MSPINIT_CB_ID = 34U, /*!< RTC Msp Init callback ID */ + HAL_RTC_MSPDEINIT_CB_ID = 35U /*!< RTC Msp DeInit callback ID */ +} HAL_RTC_CallbackIDTypeDef; + +/** + * @brief HAL RTC Callback pointer definition + */ +typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_Exported_Constants RTC Exported Constants + * @{ + */ + +/** @defgroup RTC_Hour_Formats RTC Hour Formats + * @{ + */ +#define RTC_HOURFORMAT_24 0x00000000u +#define RTC_HOURFORMAT_12 RTC_CR_FMT +/** + * @} + */ + +/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition + * @{ + */ +#define RTC_OUTPUT_DISABLE 0x00000000u +#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0 +#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1 +#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL +#define RTC_OUTPUT_TAMPER RTC_CR_TAMPOE +/** + * @} + */ + + +/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions + * @{ + */ +#define RTC_OUTPUT_POLARITY_HIGH 0x00000000u +#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL +/** + * @} + */ + +/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT + * @{ + */ +#define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u +#define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE +/** + * @} + */ + +/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT + * @{ + */ +#define RTC_OUTPUT_PULLUP_NONE 0x00000000u +#define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU +/** + * @} + */ + +/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap + * @{ + */ +#define RTC_OUTPUT_REMAP_NONE 0x00000000u +#define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN +/** + * @} + */ + +/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions + * @{ + */ +#define RTC_HOURFORMAT12_AM 0x0u +#define RTC_HOURFORMAT12_PM 0x1u +/** + * @} + */ + +/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions + * @{ + */ +#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H +#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H +#define RTC_DAYLIGHTSAVING_NONE 0x00000000u +/** + * @} + */ + +/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions + * @{ + */ +#define RTC_STOREOPERATION_RESET 0x00000000u +#define RTC_STOREOPERATION_SET RTC_CR_BKP +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions + * @{ + */ +#define RTC_FORMAT_BIN 0x00000000u +#define RTC_FORMAT_BCD 0x00000001u +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_MONTH_JANUARY ((uint8_t)0x01U) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) +#define RTC_MONTH_MARCH ((uint8_t)0x03U) +#define RTC_MONTH_APRIL ((uint8_t)0x04U) +#define RTC_MONTH_MAY ((uint8_t)0x05U) +#define RTC_MONTH_JUNE ((uint8_t)0x06U) +#define RTC_MONTH_JULY ((uint8_t)0x07U) +#define RTC_MONTH_AUGUST ((uint8_t)0x08U) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10U) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12U) + +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions + * @{ + */ +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) + +/** + * @} + */ + +/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions + * @{ + */ +#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000u +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL + +/** + * @} + */ + +/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions + * @{ + */ +#define RTC_ALARMMASK_NONE 0x00000000u +#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 +#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 +#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 +#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 +#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS | \ + RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS) + +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions + * @{ + */ +#define RTC_ALARM_A RTC_CR_ALRAE +#define RTC_ALARM_B RTC_CR_ALRBE + +/** + * @} + */ + + +/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions + * @{ + */ +#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000u /*!< All Alarm SS fields are masked. + There is no comparison on sub seconds + for Alarm */ +#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] not used in Alarm + comparison. Only SS[0] is compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] not used in Alarm + comparison. Only SS[1:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] not used in Alarm + comparison. Only SS[2:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] not used in Alarm + comparison. Only SS[3:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] not used in Alarm + comparison. Only SS[4:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] not used in Alarm + comparison. Only SS[5:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] not used in Alarm + comparison. Only SS[6:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] not used in Alarm + comparison. Only SS[7:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] not used in Alarm + comparison. Only SS[8:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] not used in Alarm + comparison. Only SS[9:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] not used in Alarm + comparison. Only SS[10:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] not used in Alarm + comparison.Only SS[11:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] not used in Alarm + comparison. Only SS[12:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] not used in Alarm + comparison. Only SS[13:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match + to activate alarm. */ +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions + * @{ + */ +#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */ +#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */ +#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */ +#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */ +/** + * @} + */ + +/** @defgroup RTC_Flag_Mask RTC Flag Mask (5bits) describe in RTC_Flags_Definitions + * @{ + */ +#define RTC_FLAG_MASK 0x001Fu /*!< RTC flags mask (5bits) */ +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions RTC Flags Definitions + * Elements values convention: 000000XX000YYYYYb + * - YYYYY : Interrupt flag position in the XX register (5bits) + * - XX : Interrupt status register (2bits) + * - 01: ICSR register + * - 10: SR or SCR or MISR or SMISR registers + * @{ + */ +#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */ +#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos) /*!< Initialization flag */ +#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos) /*!< Registers synchronization flag */ +#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos) /*!< Initialization status flag */ +#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos) /*!< Shift operation pending flag */ +#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos) /*!< Wakeup timer write flag */ +#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos) /*!< Internal Time-stamp flag */ +#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos) /*!< Time-stamp overflow flag */ +#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos) /*!< Time-stamp flag */ +#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos) /*!< Wakeup timer flag */ +#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos) /*!< Alarm B flag */ +#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos) /*!< Alarm A flag */ +/** + * @} + */ + +/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions + * @{ + */ +#define RTC_CLEAR_ITSF RTC_SCR_CITSF /*!< Clear Internal Time-stamp flag */ +#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF /*!< Clear Time-stamp overflow flag */ +#define RTC_CLEAR_TSF RTC_SCR_CTSF /*!< Clear Time-stamp flag */ +#define RTC_CLEAR_WUTF RTC_SCR_CWUTF /*!< Clear Wakeup timer flag */ +#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF /*!< Clear Alarm B flag */ +#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF /*!< Clear Alarm A flag */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RTC_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @brief Reset RTC handle state + * @param __HANDLE__ RTC handle. + * @retval None + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_RTC_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0) +#else +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @brief Disable the write protection for RTC registers. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ + do{ \ + RTC->WPR = 0xCAU; \ + RTC->WPR = 0x53U; \ + } while(0U) + +/** + * @brief Enable the write protection for RTC registers. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ + do{ \ + RTC->WPR = 0xFFU; \ + } while(0U) + +/** + * @brief Add 1 hour (summer time change). + * @param __HANDLE__ specifies the RTC handle. + * @param __BKP__ Backup + * This parameter can be: + * @arg @ref RTC_STOREOPERATION_RESET + * @arg @ref RTC_STOREOPERATION_SET + * @retval None + */ +#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__) \ + do { \ + __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ + SET_BIT(RTC->CR, RTC_CR_ADD1H); \ + MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \ + __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ + } while(0); + +/** + * @brief Subtract 1 hour (winter time change). + * @param __HANDLE__ specifies the RTC handle. + * @param __BKP__ Backup + * This parameter can be: + * @arg @ref RTC_STOREOPERATION_RESET + * @arg @ref RTC_STOREOPERATION_SET + * @retval None + */ +#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__) \ + do { \ + __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ + SET_BIT(RTC->CR, RTC_CR_SUB1H); \ + MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \ + __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ + } while(0); + +/** + * @brief Enable the RTC ALARMA peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ALRAE)) + +/** + * @brief Disable the RTC ALARMA peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ALRAE)) + +/** + * @brief Enable the RTC ALARMB peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ALRBE)) + +/** + * @brief Disable the RTC ALARMB peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ALRBE)) + +/** + * @brief Enable the RTC Alarm interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC Alarm interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC Alarm interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL) + +/** + * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) + +/** + * @brief Get the selected RTC Alarms flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to check. + * This parameter can be: + * @arg @ref RTC_FLAG_ALRAF + * @arg @ref RTC_FLAG_ALRBF + * @retval None + */ +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) + +/** + * @brief Clear the RTC Alarms pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_ALRAF + * @arg @ref RTC_FLAG_ALRBF + * @retval None + */ +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) ? ((RTC->SCR = (RTC_CLEAR_ALRAF))) : \ + (RTC->SCR = (RTC_CLEAR_ALRBF))) + +#if defined(CORE_CM4) +/** + * @brief Enable interrupt on the RTC Alarm associated Exti line. + * @retval None + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI_C2->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable interrupt on the RTC Alarm associated Exti line. + * @retval None + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI_C2->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Enable event on the RTC Alarm associated Exti line. + * @retval None + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI_C2->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable event on the RTC Alarm associated Exti line. + * @retval None + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI_C2->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) + +#elif defined(CORE_CA7) + +#else /* !CORE_CA7 */ + +#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI_C1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable interrupt on the RTC Alarm associated Exti line. + * @retval None + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI_C1->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Enable event on the RTC Alarm associated Exti line. + * @retval None + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI_C1->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable event on the RTC Alarm associated Exti line. + * @retval None + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI_C1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) + +#error Please #define CORE_CM4 or CORE_CA7 + +#endif +/** + * @} + */ + +/* Include RTC HAL Extended module */ +#include "stm32mp1xx_hal_rtc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); + +void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions + * @{ + */ +/* RTC Time and Date functions ************************************************/ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions + * @{ + */ +/* RTC Alarm functions ********************************************************/ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTC_Private_Constants RTC Private Constants + * @{ + */ +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \ + RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \ + RTC_TR_SU) +#define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \ + RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ + RTC_DR_DU) +#define RTC_INIT_MASK 0xFFFFFFFFu +#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF)) + +#define RTC_TIMEOUT_VALUE 1000u + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RTC_Private_Macros RTC Private Macros + * @{ + */ + +/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters + * @{ + */ +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ + ((OUTPUT) == RTC_OUTPUT_WAKEUP) || \ + ((OUTPUT) == RTC_OUTPUT_TAMPER)) + +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ + ((FORMAT) == RTC_HOURFORMAT_24)) + +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ + ((POL) == RTC_OUTPUT_POLARITY_LOW)) + +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ + ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) + +#define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \ + ((TYPE) == RTC_OUTPUT_PULLUP_ON)) + +#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \ + ((REMAP) == RTC_OUTPUT_REMAP_POS1)) + +#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \ + ((PM) == RTC_HOURFORMAT12_PM)) + +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ + ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ + ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) + +#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ + ((OPERATION) == RTC_STOREOPERATION_SET)) + +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \ + ((FORMAT) == RTC_FORMAT_BCD)) + +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99u) + +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u)) + +#define IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u)) + +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u)) + +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ + ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) + +#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0UL) + +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || \ + ((ALARM) == RTC_ALARM_B)) + +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS) + +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == 0UL) || \ + (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE))) + +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos)) + +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos)) + +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u)) + +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u) + +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u) + +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u) + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------*/ +/** @defgroup RTC_Private_Functions RTC Private Functions + * @{ + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc); +uint8_t RTC_ByteToBcd2(uint8_t Value); +uint8_t RTC_Bcd2ToByte(uint8_t Value); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32MP1xx_HAL_RTC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rtc_ex.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rtc_ex.h new file mode 100644 index 0000000000..f803a5ea25 --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rtc_ex.h @@ -0,0 +1,1598 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_hal_rtc_ex.h + * @author MCD Application Team + * @brief Header file of RTC HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32MP1xx_HAL_RTC_EX_H +#define STM32MP1xx_HAL_RTC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_hal_def.h" + +/** @addtogroup STM32MP1xx_HAL_Driver + * @{ + */ + +/** @defgroup RTCEx RTCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Types RTCEx Exported Types + * @{ + */ + +/** @defgroup RTCEx_Tamper_structure_definition RTCEx Tamper structure definition + * @{ + */ +typedef struct +{ + uint32_t Tamper; /*!< Specifies the Tamper Pin. + This parameter can be a value of @ref RTCEx_Tamper_Pins */ + + uint32_t Trigger; /*!< Specifies the Tamper Trigger. + This parameter can be a value of @ref RTCEx_Tamper_Trigger */ + + uint32_t NoErase; /*!< Specifies the Tamper no erase mode. + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */ + + uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. + This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */ + + uint32_t Filter; /*!< Specifies the TAMP Filter Tamper. + This parameter can be a value of @ref RTCEx_Tamper_Filter */ + + uint32_t SamplingFrequency; /*!< Specifies the sampling frequency. + This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies */ + + uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration . + This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration */ + + uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp . + This parameter can be a value of @ref RTCEx_Tamper_Pull_UP */ + + uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. + This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */ +} RTC_TamperTypeDef; +/** + * @} + */ + + +/** @defgroup RTCEx_Active_Seed_Size Seed size Definitions + * @{ + */ +#define RTC_ATAMP_SEED_NB_UINT32 4U +/** + * @} + */ + + +/** @defgroup RTCEx_ActiveTamper_structures_definition RTCEx Active Tamper structures definitions + * @{ + */ +typedef struct +{ + uint32_t Enable; /*!< Specifies the Tamper input is active. + This parameter can be a value of @ref RTCEx_ActiveTamper_Enable */ + + uint32_t Interrupt; /*!< Specifies the interrupt mode + This parameter can be a value of @ref RTCEx_ActiveTamper_Interrupt */ + + uint32_t Output; /*!< Specifies the TAMP output to be compared with. + The same output can be used for several tamper inputs. + This parameter can be a value of @ref RTCEx_ActiveTamper_Sel */ + + uint32_t NoErase; /*!< Specifies the Tamper no erase mode. + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */ + + uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. + This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */ + +} RTC_ATampInputTypeDef; + + +typedef struct +{ + uint32_t ActiveFilter; /*!< Specifies the Active tamper filter enable. + This parameter can be a value of @ref RTCEx_ActiveTamper_Filter */ + + uint32_t ActiveAsyncPrescaler; /*!< Specifies the Active Tamper asynchronous Prescaler clock. + This parameter can be a value of @ref RTCEx_ActiveTamper_Async_prescaler */ + + uint32_t TimeStampOnTamperDetection; /*!< Specifies the timeStamp on tamper detection. + This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */ + + uint32_t ActiveOutputChangePeriod; /*!< Specifies the Active Tamper output change period. + This parameter can be a value from 0 to 7. */ + + uint32_t Seed[RTC_ATAMP_SEED_NB_UINT32]; + /*!< Specifies the RNG Seed value. + This parameter is an array of value from 0 to 0xFFFFFFFF. */ + + RTC_ATampInputTypeDef TampInput[RTC_TAMP_NB]; + /*!< Specifies configuration of all active tampers. + The index of TampInput[RTC_TAMP_NB] can be a value of RTCEx_ActiveTamper_Sel */ +} RTC_ActiveTampersTypeDef; +/** + * @} + */ + +/** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition + * @{ + */ +typedef struct +{ + uint32_t IntTamper; /*!< Specifies the Internal Tamper Pin. + This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */ + + uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. + This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */ + + uint32_t NoErase; /*!< Specifies the internal Tamper no erase mode. + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */ + +} RTC_InternalTamperTypeDef; +/** + * @} + */ + +/** @defgroup RTCEx_Secure_State_structure_definition RTCEx Secure structure definition + * @{ + */ +typedef struct +{ + uint32_t rtcSecureFull; /*!< Specifies If the RTC is fully secure or not + This parameter can be a value of @ref RTCEx_RTC_Secure_Full */ + uint32_t rtcNonSecureFeatures; /*!< Specifies the non-secure features. + This parameter is only relevant if RTC is not fully secure (rtcSecureFull == RTC_SECURE_FULL_NO). + This parameter can be a combination of @ref RTCEx_RTC_NonSecure_Features. */ + + uint32_t tampSecureFull; /*!< Specifies If the TAMP is fully secure or not + This parameter can be a value of @ref RTCEx_TAMP_Secure_Full */ + + uint32_t backupRegisterStartZone2; /*!< Specifies the backup register start zone 2 + Zone 1 : read secure write secure. + Zone 2 : read non-secure write secure. + This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify the register. + Warning : this parameter is shared with RTC_PrivilegeStateTypeDef. */ + + uint32_t backupRegisterStartZone3; /*!< Specifies the backup register start zone 3 + Zone 3 : read non-secure write non-secure + This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify the register. + Warning : this parameter is shared with RTC_PrivilegeStateTypeDef. */ + +} RTC_SecureStateTypeDef ; +/** + * @} + */ + +/** @defgroup RTCEx_Privilege_State_structure_definition RTCEx Privilege structure definition + * @{ + */ +typedef struct +{ + uint32_t rtcPrivilegeFull; /*!< Specifies If the RTC is fully privileged or not. + This parameter can be a value of @ref RTCEx_RTC_Privilege_Full. */ + + uint32_t rtcPrivilegeFeatures; /*!< Specifies the privileged features. + This parameter is only relevant if RTC is not fully privileged (rtcPrivilegeFull == RTC_PRIVILEGE_FULL_NO). + This parameter can be a combination of @ref RTCEx_RTC_Privilege_Features. */ + + uint32_t tampPrivilegeFull; /*!< Specifies If the TAMP is fully privileged or not. + This parameter can be a value of @ref RTCEx_TAMP_Privilege_Full. */ + + uint32_t backupRegisterPrivZone; /*!< Specifies backup register zone to be privileged. + This parameter can be a combination of @ref RTCEx_Backup_Reg_Privilege_zone. + Warning : this parameter is writable in secure mode or if trustzone is disabled. */ + + + uint32_t backupRegisterStartZone2; /*!< Specifies the backup register start zone 2. + Zone 1 : read secure write secure. + Zone 2 : read non-secure write secure. + This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify the register . + Warning : this parameter is writable in secure mode or if trustzone is disabled. + Warning : this parameter is shared with RTC_SecureStateTypeDef */ + + uint32_t backupRegisterStartZone3; /*!< Specifies the backup register start zone 3. + Zone 3 : read non-secure write non-secure. + This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify the register. + Warning : this parameter is writable in secure mode or if trustzone is disabled. + Warning : this parameter is shared with RTC_SecureStateTypeDef. */ + +} RTC_PrivilegeStateTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants + * @{ + */ + +/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition + * @{ + */ +#define RTC_TIMESTAMPEDGE_RISING 0x00000000u +#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE +/** + * @} + */ + +/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection + * @{ + */ +#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000u +/** + * @} + */ + +/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions + * @{ + */ +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000u +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2 +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2) +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions + * @{ + */ +#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000u /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 32s, else 2exp20 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 16s, else 2exp19 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 8s, else 2exp18 RTCCLK pulses */ +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions + * @{ + */ +#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0] + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000u /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0] */ +/** + * @} + */ + +/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions + * @{ + */ +#define RTC_CALIBOUTPUT_512HZ 0x00000000u +#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL + +/** + * @} + */ + + +/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions + * @{ + */ +#define RTC_SHIFTADD1S_RESET 0x00000000u +#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pins RTCEx Tamper Pins Definition + * @{ + */ +#define RTC_TAMPER_1 TAMP_CR1_TAMP1E +#define RTC_TAMPER_2 TAMP_CR1_TAMP2E +#define RTC_TAMPER_3 TAMP_CR1_TAMP3E +#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3 ) + +/** + * @} + */ + +/** @defgroup RTCEx_Internal_Tamper_Pins RTCEx Internal Tamper Pins Definition + * @{ + */ +#define RTC_INT_TAMPER_1 TAMP_CR1_ITAMP1E +#define RTC_INT_TAMPER_2 TAMP_CR1_ITAMP2E +#define RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E +#define RTC_INT_TAMPER_4 TAMP_CR1_ITAMP4E +#define RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E +#define RTC_INT_TAMPER_8 TAMP_CR1_ITAMP8E +#define RTC_INT_TAMPER_ALL (RTC_INT_TAMPER_1 | RTC_INT_TAMPER_2 |\ + RTC_INT_TAMPER_3 | RTC_INT_TAMPER_5 |\ + RTC_INT_TAMPER_4 | RTC_INT_TAMPER_8) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Trigger RTCEx Tamper Trigger + * @{ + */ +#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x01u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_LOWLEVEL 0x02u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x03u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_MaskFlag RTCEx Tamper MaskFlag + * @{ + */ +#define RTC_TAMPERMASK_FLAG_DISABLE 0x00u +#define RTC_TAMPERMASK_FLAG_ENABLE 0x01u +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_EraseBackUp RTCEx Tamper EraseBackUp +* @{ +*/ +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u +#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Filter RTCEx Tamper Filter + * @{ + */ +#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ +#define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 + consecutive samples at the active level */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Sampling_Frequencies RTCEx Tamper Sampling Frequencies + * @{ + */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1 | \ + TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration RTCEx Tamper Pin Precharge Duration + * @{ + */ +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pull_UP RTCEx Tamper Pull UP + * @{ + */ +#define RTC_TAMPER_PULLUP_ENABLE 0x00000000u /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection RTCEx Tamper TimeStamp On Tamper Detection Definitions + * @{ + */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ +/** + * @} + */ + +/** @defgroup RTCEx_Internal_Tamper_Interrupt RTCEx Internal Tamper Interrupt + * @{ + */ +#define RTC_IT_TAMP_1 TAMP_IER_TAMP1IE /*!< Tamper 1 Interrupt */ +#define RTC_IT_TAMP_2 TAMP_IER_TAMP2IE /*!< Tamper 2 Interrupt */ +#define RTC_IT_TAMP_3 TAMP_IER_TAMP3IE /*!< Tamper 3 Interrupt */ + +#define RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 | RTC_IT_TAMP_3) + +#define RTC_IT_INT_TAMP_1 TAMP_IER_ITAMP1IE /*!< Tamper 1 internal Interrupt */ +#define RTC_IT_INT_TAMP_2 TAMP_IER_ITAMP2IE /*!< Tamper 2 internal Interrupt */ +#define RTC_IT_INT_TAMP_3 TAMP_IER_ITAMP3IE /*!< Tamper 3 internal Interrupt */ +#define RTC_IT_INT_TAMP_4 TAMP_IER_ITAMP4IE /*!< Tamper 4 internal Interrupt */ +#define RTC_IT_INT_TAMP_5 TAMP_IER_ITAMP5IE /*!< Tamper 5 internal Interrupt */ +#define RTC_IT_INT_TAMP_8 TAMP_IER_ITAMP8IE /*!< Tamper 8 internal Interrupt */ + +#define RTC_IT_INT_TAMP_ALL (RTC_IT_INT_TAMP_1 | RTC_IT_INT_TAMP_2 |\ + RTC_IT_INT_TAMP_3 | RTC_IT_INT_TAMP_4 |\ + RTC_IT_INT_TAMP_5 | RTC_IT_INT_TAMP_8 ) +/** + * @} + */ + +/** @defgroup RTCEx_Flags RTCEx Flags + * @{ + */ +#define RTC_FLAG_TAMP_1 TAMP_SR_TAMP1F +#define RTC_FLAG_TAMP_2 TAMP_SR_TAMP2F +#define RTC_FLAG_TAMP_3 TAMP_SR_TAMP3F +#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3) + + +#define RTC_FLAG_INT_TAMP_1 TAMP_SR_ITAMP1F +#define RTC_FLAG_INT_TAMP_2 TAMP_SR_ITAMP2F +#define RTC_FLAG_INT_TAMP_3 TAMP_SR_ITAMP3F +#define RTC_FLAG_INT_TAMP_4 TAMP_SR_ITAMP4F +#define RTC_FLAG_INT_TAMP_5 TAMP_SR_ITAMP5F +#define RTC_FLAG_INT_TAMP_8 TAMP_SR_ITAMP8F +#define RTC_FLAG_INT_TAMP_ALL (RTC_FLAG_INT_TAMP_1 | RTC_FLAG_INT_TAMP_2 |\ + RTC_FLAG_INT_TAMP_3 | RTC_FLAG_INT_TAMP_4 |\ + RTC_FLAG_INT_TAMP_5 | RTC_FLAG_INT_TAMP_8) +/** + * @} + */ + + +/** @defgroup RTCEx_ActiveTamper_Enable RTCEx_ActiveTamper_Enable Definitions + * @{ + */ +#define RTC_ATAMP_ENABLE 1u +#define RTC_ATAMP_DISABLE 0u +/** + * @} + */ + +/** @defgroup RTCEx_ActiveTamper_Interrupt RTCEx_ActiveTamper_Interrupt Definitions + * @{ + */ +#define RTC_ATAMP_INTERRUPT_ENABLE 1u +#define RTC_ATAMP_INTERRUPT_DISABLE 0u +/** + * @} + */ + +/** @defgroup RTCEx_ActiveTamper_Filter RTCEx_ActiveTamper_Filter Definitions + * @{ + */ +#define RTC_ATAMP_FILTER_ENABLE TAMP_ATCR1_FLTEN +#define RTC_ATAMP_FILTER_DISABLE 0u +/** + * @} + */ + +/** @defgroup RTCEx_ActiveTamper_Async_prescaler RTCEx Active_Tamper_Asynchronous_Prescaler clock Definitions + * @{ + */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK 0u /*!< RTCCLK */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +/** + * @} + */ + +/** @defgroup RTCEx_ActiveTamper_Sel RTCEx Active Tamper selection Definition + * @{ + */ +#define RTC_ATAMP_1 0u /*!< Tamper 1 */ +#define RTC_ATAMP_2 1u /*!< Tamper 2 */ +#define RTC_ATAMP_3 2u /*!< Tamper 3 */ +/** + * @} + */ + + +/** @defgroup RTCEx_MonotonicCounter_Instance RTCEx Monotonic Counter Instance Definition + * @{ + */ +#define RTC_MONOTONIC_COUNTER_1 0u /*!< Monotonic counter 1 */ +/** + * @} + */ + + +/** @defgroup RTCEx_Backup_Registers RTCEx Backup Registers Definition + * @{ + */ +#define RTC_BKP_NUMBER RTC_BACKUP_NB +#define RTC_BKP_DR0 0x00u +#define RTC_BKP_DR1 0x01u +#define RTC_BKP_DR2 0x02u +#define RTC_BKP_DR3 0x03u +#define RTC_BKP_DR4 0x04u +#define RTC_BKP_DR5 0x05u +#define RTC_BKP_DR6 0x06u +#define RTC_BKP_DR7 0x07u +#define RTC_BKP_DR8 0x08u +#define RTC_BKP_DR9 0x09u +#define RTC_BKP_DR10 0x0Au +#define RTC_BKP_DR11 0x0Bu +#define RTC_BKP_DR12 0x0Cu +#define RTC_BKP_DR13 0x0Du +#define RTC_BKP_DR14 0x0Eu +#define RTC_BKP_DR15 0x0Fu +#define RTC_BKP_DR16 0x10u +#define RTC_BKP_DR17 0x11u +#define RTC_BKP_DR18 0x12u +#define RTC_BKP_DR19 0x13u +#define RTC_BKP_DR20 0x14u +#define RTC_BKP_DR21 0x15u +#define RTC_BKP_DR22 0x16u +#define RTC_BKP_DR23 0x17u +#define RTC_BKP_DR24 0x18u +#define RTC_BKP_DR25 0x19u +#define RTC_BKP_DR26 0x1Au +#define RTC_BKP_DR27 0x1Bu +#define RTC_BKP_DR28 0x1Cu +#define RTC_BKP_DR29 0x1Du +#define RTC_BKP_DR30 0x1Eu +#define RTC_BKP_DR31 0x1Fu +/** + * @} + */ + + +/** @defgroup RTCEx_RTC_Secure_Full RTCEx Secure Definition + * @{ + */ +#define RTC_SECURE_FULL_YES 0u /*!< RTC full secure */ +#define RTC_SECURE_FULL_NO RTC_SMCR_DECPROT /*!< RTC is not full secure, features can be non-secure. See RTC_LL_EC_NONSECURE_RTC_FEATURE */ +/** + * @} + */ + +/** @defgroup RTCEx_RTC_NonSecure_Features RTCEx Secure Features Definition + * @{ + */ +#define RTC_NONSECURE_FEATURE_NONE 0u +#define RTC_NONSECURE_FEATURE_INIT RTC_SMCR_INITDPROT /*!< Initialization */ +#define RTC_NONSECURE_FEATURE_CAL RTC_SMCR_CALDPROT /*!< Calibration */ +#define RTC_NONSECURE_FEATURE_TS RTC_SMCR_TSDPROT /*!< Time stamp */ +#define RTC_NONSECURE_FEATURE_WUT RTC_SMCR_WUTDPROT /*!< Wake up timer */ +#define RTC_NONSECURE_FEATURE_ALRA RTC_SMCR_ALRADPROT /*!< Alarm A */ +#define RTC_NONSECURE_FEATURE_ALRB RTC_SMCR_ALRBDPROT /*!< Alarm B */ +#define RTC_NONSECURE_FEATURE_ALL (RTC_SMCR_INITDPROT | RTC_SMCR_CALDPROT | \ + RTC_SMCR_TSDPROT | RTC_SMCR_WUTDPROT | \ + RTC_SMCR_ALRADPROT | RTC_SMCR_ALRBDPROT) +/** + * @} + */ + +/** @defgroup RTCEx_TAMP_Secure_Full RTCEx TAMP Secure + * @{ + */ +#define TAMP_SECURE_FULL_YES 0u /*!< TAMPER full secure */ +#define TAMP_SECURE_FULL_NO TAMP_SMCR_TAMPDPROT /*!< TAMPER is not secure */ +/** + * @} + */ + + +/** @defgroup RTCEx_RTC_Privilege_Full RTCEx Privilege Features + * @{ + */ +#define RTC_PRIVILEGE_FULL_YES RTC_PRIVCR_PRIV +#define RTC_PRIVILEGE_FULL_NO 0u +/** + * @} + */ + +/** @defgroup RTCEx_RTC_Privilege_Features RTCEx Privilege Features Definition + * @{ + */ +#define RTC_PRIVILEGE_FEATURE_NONE 0u +#define RTC_PRIVILEGE_FEATURE_INIT RTC_PRIVCR_INITPRIV /*!< Initialization */ +#define RTC_PRIVILEGE_FEATURE_CAL RTC_PRIVCR_CALPRIV /*!< Calibration */ +#define RTC_PRIVILEGE_FEATURE_TS RTC_PRIVCR_TSPRIV /*!< Time stamp */ +#define RTC_PRIVILEGE_FEATURE_WUT RTC_PRIVCR_WUTPRIV /*!< Wake up timer */ +#define RTC_PRIVILEGE_FEATURE_ALRA RTC_PRIVCR_ALRAPRIV /*!< Alarm A */ +#define RTC_PRIVILEGE_FEATURE_ALRB RTC_PRIVCR_ALRBPRIV /*!< Alarm B */ +#define RTC_PRIVILEGE_FEATURE_ALL (RTC_PRIVCR_INITPRIV | RTC_PRIVCR_CALPRIV | \ + RTC_PRIVCR_TSPRIV | RTC_PRIVCR_WUTPRIV | \ + RTC_PRIVCR_ALRAPRIV | RTC_PRIVCR_ALRBPRIV) +/** + * @} + */ + +/** @defgroup RTCEx_TAMP_Privilege_Full RTCEx TAMP security Definition + * @{ + */ +#define TAMP_PRIVILEGE_FULL_YES TAMP_PRIVCR_TAMPPRIV +#define TAMP_PRIVILEGE_FULL_NO 0u +/** + * @} + */ + +/** @defgroup RTCEx_Backup_Reg_Privilege_zone RTCEx Privilege Backup register privilege zone Definition + * @{ + */ +#define RTC_PRIVILEGE_BKUP_ZONE_NONE 0u +#define RTC_PRIVILEGE_BKUP_ZONE_1 TAMP_PRIVCR_BKPRWPRIV +#define RTC_PRIVILEGE_BKUP_ZONE_2 TAMP_PRIVCR_BKPWPRIV +#define RTC_PRIVILEGE_BKUP_ZONE_ALL (RTC_PRIVILEGE_BKUP_ZONE_1 | RTC_PRIVILEGE_BKUP_ZONE_2) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros + * @{ + */ + +/** @brief Clear the specified RTC pending flag. + * @param __HANDLE__ specifies the RTC Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref RTC_CLEAR_ITSF Clear Internal Time-stamp flag + * @arg @ref RTC_CLEAR_TSOVF Clear Time-stamp overflow flag + * @arg @ref RTC_CLEAR_TSF Clear Time-stamp flag + * @arg @ref RTC_CLEAR_WUTF Clear Wakeup timer flag + * @arg @ref RTC_CLEAR_ALRBF Clear Alarm B flag + * @arg @ref RTC_CLEAR_ALRAF Clear Alarm A flag + * @retval None + */ +#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) (RTC->SCR = (__FLAG__)) + +/** @brief Check whether the specified RTC flag is set or not. + * @param __HANDLE__ specifies the RTC Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref RTC_FLAG_RECALPF Recalibration pending Flag + * @arg @ref RTC_FLAG_INITF Initialization flag + * @arg @ref RTC_FLAG_RSF Registers synchronization flag + * @arg @ref RTC_FLAG_INITS Initialization status flag + * @arg @ref RTC_FLAG_SHPF Shift operation pending flag + * @arg @ref RTC_FLAG_WUTWF Wakeup timer write flag + * @arg @ref RTC_FLAG_ITSF Internal Time-stamp flag + * @arg @ref RTC_FLAG_TSOVF Time-stamp overflow flag + * @arg @ref RTC_FLAG_TSF Time-stamp flag + * @arg @ref RTC_FLAG_WUTF Wakeup timer flag + * @arg @ref RTC_FLAG_ALRBF Alarm B flag + * @arg @ref RTC_FLAG_ALRAF Alarm A flag + * @retval None + */ +#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? (RTC->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \ + (RTC->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK)))) + +/* ---------------------------------WAKEUPTIMER---------------------------------*/ +/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer + * @{ + */ +/** + * @brief Enable the RTC WakeUp Timer peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_WUTE)) + +/** + * @brief Disable the RTC WakeUp Timer peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_WUTE)) + +/** + * @brief Enable the RTC WakeUpTimer interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC WakeUpTimer interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) + + +/** + * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != 0UL) ? 1UL : 0UL) +/** + * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0UL) ? 1UL : 0UL) + +/** + * @brief Get the selected RTC WakeUpTimers flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_WUTF + * @arg @ref RTC_FLAG_WUTWF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) + +/** + * @brief Clear the RTC Wake Up timers pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_WUTF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF)) + + +#if defined(CORE_CM4) + +/* WAKE-UP TIMER EXTI */ +/* ------------------ */ +/** + * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI_C2->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI_C2->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable event on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI_C2->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable event on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI_C2->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @} + */ +#elif defined(CORE_CA7) +/* WAKE-UP TIMER EXTI */ +/* ------------------ */ +/** + * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI_C1->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI_C1->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable event on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI_C1->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable event on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI_C1->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @} + */ +#else /* !CORE_CA7 */ + +#error Please #define CORE_CM4 or CORE_CA7 + +#endif + + + +/* ---------------------------------TIMESTAMP---------------------------------*/ +/** @defgroup RTCEx_Timestamp RTC Timestamp + * @{ + */ +/** + * @brief Enable the RTC TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TSE)) + +/** + * @brief Disable the RTC TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TSE)) + +/** + * @brief Enable the RTC TimeStamp interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC TimeStamp interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL) +/** + * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) + +/** + * @brief Get the selected RTC TimeStamps flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_TSF + * @arg @ref RTC_FLAG_TSOVF + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__))) + +/** + * @brief Clear the RTC Time Stamps pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_TSF + * @arg @ref RTC_FLAG_TSOVF + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__))) + +#if defined(CORE_CM4) +/** + * @brief Enable interrupt on the RTC Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT() (EXTI_C2->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) + +/** + * @brief Disable interrupt on the RTC Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT() (EXTI_C2->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) + +/** + * @brief Enable event on the RTC Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI_C2->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) + +/** + * @brief Disable event on the RTC Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI_C2->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) + +#elif defined(CORE_CA7) +/** + * @brief Enable interrupt on the RTC Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT() (EXTI_C1->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) + +/** + * @brief Disable interrupt on the RTC Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT() (EXTI_C1->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) + +/** + * @brief Enable event on the RTC Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI_C1->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) + +/** + * @brief Disable event on the RTC Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI_C1->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) + +#else /* !CORE_CA7 */ + +#error Please #define CORE_CM4 or CORE_CA7 + +#endif + +/** + * @brief Enable the RTC internal TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ITSE)) + +/** + * @brief Disable the RTC internal TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ITSE)) + +/** + * @brief Get the selected RTC Internal Time Stamps flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_ITSF + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__))) + +/** + * @brief Clear the RTC Internal Time Stamps pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_ITSF + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF)) + +/** + * @brief Enable the RTC TimeStamp on Tamper detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TAMPTS)) + +/** + * @brief Disable the RTC TimeStamp on Tamper detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TAMPTS)) + +/** + * @brief Enable the RTC Tamper detection output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TAMPOE)) + +/** + * @brief Disable the RTC Tamper detection output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TAMPOE)) + + +/** + * @} + */ + + +/* ------------------------------Calibration----------------------------------*/ +/** @defgroup RTCEx_Calibration RTC Calibration + * @{ + */ + +/** + * @brief Enable the RTC calibration output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_COE)) + +/** + * @brief Disable the calibration output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_COE)) + + +/** + * @brief Enable the clock reference detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_REFCKON)) + +/** + * @brief Disable the clock reference detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_REFCKON)) + + +/** + * @brief Get the selected RTC shift operations flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_SHPF + * @retval None + */ +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +/** + * @} + */ + + +/* ------------------------------Tamper----------------------------------*/ +/** @defgroup RTCEx_Tamper RTCEx tamper + * @{ + */ +/** + * @brief Enable the TAMP Tamper input detection. + * @param __HANDLE__ specifies the RTC handle. + * @param __TAMPER__ specifies the RTC Tamper source to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_ALL: All tampers + * @arg RTC_TAMPER_1: Tamper1 + * @arg RTC_TAMPER_2: Tamper2 + * @arg RTC_TAMPER_3: Tamper3 + * @retval None + */ +#define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 |= (__TAMPER__)) + +/** + * @brief Disable the TAMP Tamper input detection. + * @param __HANDLE__ specifies the RTC handle. + * @param __TAMPER__ specifies the RTC Tamper sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_ALL: All tampers + * @arg RTC_TAMPER_1: Tamper1 + * @arg RTC_TAMPER_2: Tamper2 + * @arg RTC_TAMPER_3: Tamper3 + */ +#define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 &= ~(__TAMPER__)) + + +/**************************************************************************************************/ +/** + * @brief Enable the TAMP Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER |= (__INTERRUPT__)) + +/** + * @brief Disable the TAMP Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER &= ~(__INTERRUPT__)) + + +/**************************************************************************************************/ +/** + * @brief Check whether the specified RTC Tamper interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. + * This parameter can be: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts + * @arg RTC_IT_INT_TAMP_1: Internal Tamper1 interrupt + * @arg RTC_IT_INT_TAMP_2: Internal Tamper2 interrupt + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_4: Internal Tamper4 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((TAMP->MISR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) + + +/** + * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. + * This parameter can be: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_ALL: All internal tampers interrupts + * @arg RTC_IT_INT_TAMP_1: Internal Tamper1 interrupt + * @arg RTC_IT_INT_TAMP_2: Internal Tamper2 interrupt + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((TAMP->IER) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) + + +/** + * @brief Get the selected RTC Tampers flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_TAMP_ALL: All tampers flag + * @arg RTC_FLAG_TAMP_1: Tamper1 flag + * @arg RTC_FLAG_TAMP_2: Tamper2 flag + * @arg RTC_FLAG_TAMP_3: Tamper3 flag + * @arg RTC_FLAG_INT_TAMP_1: Internal Tamper1 flag + * @arg RTC_FLAG_INT_TAMP_2: Internal Tamper2 flag + * @arg RTC_FLAG_INT_TAMP_3: Internal Tamper3 flag + * @arg RTC_FLAG_INT_TAMP_4: Internal Tamper4 flag + * @arg RTC_FLAG_INT_TAMP_5: Internal Tamper5 flag + * @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 flag + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((TAMP->SR) & (__FLAG__)) != 0U) + +/** + * @brief Clear the RTC Tamper's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag to clear. + * This parameter can be: + * @arg RTC_FLAG_TAMP_ALL: All tampers flag + * @arg RTC_FLAG_TAMP_1: Tamper1 flag + * @arg RTC_FLAG_TAMP_2: Tamper2 flag + * @arg RTC_FLAG_TAMP_3: Tamper3 flag + * @arg RTC_FLAG_INT_TAMP_ALL: All Internal Tamper flags + * @arg RTC_FLAG_INT_TAMP_1: Internal Tamper1 flag + * @arg RTC_FLAG_INT_TAMP_2: Internal Tamper2 flag + * @arg RTC_FLAG_INT_TAMP_3: Internal Tamper3 flag + * @arg RTC_FLAG_INT_TAMP_4: Internal Tamper4 flag + * @arg RTC_FLAG_INT_TAMP_5: Internal Tamper5 flag + * @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 flag + * @retval None + */ +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((TAMP->SCR) = (__FLAG__)) + + +#if defined(CORE_CM4) +/** + * @brief Enable interrupt on the RTC tamper associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_EXTI_ENABLE_IT() (EXTI_C2->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) + +/** + * @brief Disable interrupt on the RTC tamper associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_EXTI_DISABLE_IT() (EXTI_C2->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) + +/** + * @brief Enable event on the RTC tamper associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI_C2->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) + +/** + * @brief Disable event on the RTC tamper associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI_C2->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) + +#elif defined(CORE_CA7) +/** + * @brief Enable interrupt on the RTC tamper associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_EXTI_ENABLE_IT() (EXTI_C1->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) + +/** + * @brief Disable interrupt on the RTC tamper associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_EXTI_DISABLE_IT() (EXTI_C1->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) + +/** + * @brief Enable event on the RTC tamper associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI_C1->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) + +/** + * @brief Disable event on the RTC tamper associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI_C1->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) + +#else /* !CORE_CA7 */ + +#error Please #define CORE_CM4 or CORE_CA7 + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions + * @{ + */ + +/* RTC TimeStamp functions *****************************************/ +/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions + * @{ + */ + +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); +void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + + +/* RTC Wake-up functions ******************************************************/ +/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions + * @{ + */ + +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, uint32_t WakeUpAutoClr); +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/* Extended Control functions ************************************************/ +/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions + * @{ + */ + +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance); +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *Value); +/** + * @} + */ + +/* Extended RTC features functions *******************************************/ +/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions + * @{ + */ + +void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper); +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper); +HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout); +void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions + * @{ + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group7 Extended RTC secure functions + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState); +#if defined (CORTEX_IN_SECURE_STATE) +HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState); +#endif /* #if defined (CORTEX_IN_SECURE_STATE) */ +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Constants RTCEx Private Constants + * @{ + */ +#if defined (CORTEX_IN_SECURE_STATE) +#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM18 /*!< External interrupt line 18 Connected to the RTC Alarm event */ +#define RTC_EXTI_LINE_TIMESTAMP_EVENT EXTI_IMR1_IM18 /*!< External interrupt line 18 Connected to the RTC Time Stamp events */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM18 /*!< External interrupt line 18 Connected to the RTC Wakeup event */ +#define RTC_EXTI_LINE_TAMPER_EVENT EXTI_IMR1_IM20 /*!< External interrupt line 20 Connected to the RTC tamper events */ +#else /* #if defined (CORTEX_IN_SECURE_STATE) */ +#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define RTC_EXTI_LINE_TIMESTAMP_EVENT EXTI_IMR1_IM17 /*!< External interrupt line 17 Connected to the RTC Time Stamp events */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM17 /*!< External interrupt line 17 Connected to the RTC Wakeup event */ +#define RTC_EXTI_LINE_TAMPER_EVENT EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC tamper events */ +#endif /* #if defined (CORTEX_IN_SECURE_STATE) */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Macros RTCEx Private Macros + * @{ + */ + +/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters + * @{ + */ +#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ + ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) + + +#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT)) + + + +#define IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) + +#define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE) (((MODE) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \ + ((MODE) == RTC_TAMPERDETECTIONOUTPUT_DISABLE)) + +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) + +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT) + +#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) + +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ + ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) + +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM) + +#define IS_RTC_LOW_POWER_CALIB(LPCAL) (((LPCAL) == RTC_LPCAL_SET) || \ + ((LPCAL) == RTC_LPCAL_RESET)) + + +#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \ + (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U)) + +#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__) ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0x00U) && \ + (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U)) + +#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) + +#define IS_RTC_TAMPER_ERASE_MODE(__MODE__) (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \ + ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE)) + +#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__) (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \ + ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE)) + +#define IS_RTC_TAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE)) + +#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) + +#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) + +#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \ + ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE)) + +#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) + +#define IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER) + +#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ + ((SEL) == RTC_SHIFTADD1S_SET)) + +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS) + +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ + ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) + +#define IS_RTC_SECURE_FULL(__STATE__) (((__STATE__) == RTC_SECURE_FULL_YES) || \ + ((__STATE__) == RTC_SECURE_FULL_NO)) + +#define IS_RTC_NONSECURE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_NONSECURE_FEATURE_ALL) == 0u) + +#define IS_TAMP_SECURE_FULL(__STATE__) (((__STATE__) == TAMP_SECURE_FULL_YES) || \ + ((__STATE__) == TAMP_SECURE_FULL_NO)) + +#define IS_RTC_PRIVILEGE_FULL(__STATE__) (((__STATE__) == RTC_PRIVILEGE_FULL_YES) || \ + ((__STATE__) == RTC_PRIVILEGE_FULL_NO)) + +#define IS_RTC_PRIVILEGE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_PRIVILEGE_FEATURE_ALL) == 0u) + +#define IS_TAMP_PRIVILEGE_FULL(__STATE__) (((__STATE__) == TAMP_PRIVILEGE_FULL_YES) || \ + ((__STATE__) == TAMP_PRIVILEGE_FULL_NO)) + +#define IS_RTC_PRIVILEGE_BKUP_ZONE(__ZONES__) (((__ZONES__) & ~RTC_PRIVILEGE_BKUP_ZONE_ALL) == 0u) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32MP1xx_HAL_RTC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sd.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sd.h old mode 100644 new mode 100755 diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sd_ex.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sd_ex.h old mode 100644 new mode 100755 diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sram.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sram.h new file mode 100644 index 0000000000..7f35feb84d --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sram.h @@ -0,0 +1,222 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_hal_sram.h + * @author MCD Application Team + * @brief Header file of SRAM HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32MP1xx_HAL_SRAM_H +#define STM32MP1xx_HAL_SRAM_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_ll_fmc.h" + +/** @addtogroup STM32MP1xx_HAL_Driver + * @{ + */ +/** @addtogroup SRAM + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup SRAM_Exported_Types SRAM Exported Types + * @{ + */ +/** + * @brief HAL SRAM State structures definition + */ +typedef enum +{ + HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ + HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ + HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ + HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ + HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ + +} HAL_SRAM_StateTypeDef; + +/** + * @brief SRAM handle Structure definition + */ +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +typedef struct __SRAM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +{ + FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ + + FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ + + FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ + + HAL_LockTypeDef Lock; /*!< SRAM locking object */ + + __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ + + DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */ + void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */ + void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */ +#endif +} SRAM_HandleTypeDef; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SRAM Callback ID enumeration definition + */ +typedef enum +{ + HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */ + HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ + HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ + HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ +}HAL_SRAM_CallbackIDTypeDef; + +/** + * @brief HAL SRAM Callback pointer definition + */ +typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); +typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); +#endif +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup SRAM_Exported_Macros SRAM Exported Macros + * @{ + */ + +/** @brief Reset SRAM handle state + * @param __HANDLE__ SRAM handle + * @retval None + */ +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) +#endif + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions + * @{ + */ + +/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); +void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); +void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); + +/** + * @} + */ + +/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions + * @{ + */ + +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); + +void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +/* SRAM callback registering/unregistering */ +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback); +#endif + +/** + * @} + */ + +/** @addtogroup SRAM_Exported_Functions_Group3 Control functions + * @{ + */ + +/* SRAM Control functions ****************************************************/ +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); + +/** + * @} + */ + +/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions + * @{ + */ + +/* SRAM State functions ******************************************************/ +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32MP1xx_HAL_SRAM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h index 5ec2cec98e..5d8aa45ec0 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h @@ -18,8 +18,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32MP1xx_HAL_UART_H -#define __STM32MP1xx_HAL_UART_H +#ifndef STM32MP1xx_HAL_UART_H +#define STM32MP1xx_HAL_UART_H #ifdef __cplusplus extern "C" { @@ -48,8 +48,6 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: - UART: - ===== - If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, @@ -91,7 +89,7 @@ typedef struct } UART_InitTypeDef; /** - * @brief UART Advanced Features initalization structure definition + * @brief UART Advanced Features initialization structure definition */ typedef struct { @@ -100,10 +98,10 @@ typedef struct This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. - This parameter can be a value of @ref UART_Tx_Inv. */ + This parameter can be a value of @ref UART_Tx_Inv. */ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. - This parameter can be a value of @ref UART_Rx_Inv. */ + This parameter can be a value of @ref UART_Rx_Inv. */ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). @@ -119,7 +117,7 @@ typedef struct This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. - This parameter can be a value of @ref UART_AutoBaudRate_Enable */ + This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate detection is carried out. @@ -129,11 +127,9 @@ typedef struct This parameter can be a value of @ref UART_MSB_First. */ } UART_AdvFeatureInitTypeDef; - - /** - * @brief HAL UART State structures definition - * @note HAL UART State value is a combination of 2 different substates: gState and RxState. + * @brief HAL UART State definition + * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition). * - gState contains UART state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -142,14 +138,14 @@ typedef struct * 01 : (Not Used) * 10 : Timeout * 11 : Error - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized. HAL UART Init function already called) + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) + * 1 : Busy (Peripheral busy with some configuration or internal operations) * b1 (not used) * x : Should be set to 0 * b0 Tx state @@ -159,9 +155,9 @@ typedef struct * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized) + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -170,26 +166,7 @@ typedef struct * b0 (not used) * x : Should be set to 0. */ -typedef enum -{ - HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ - HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ - HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing - Value is allowed for gState only */ - HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing - Value is allowed for gState only */ - HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing - Value is allowed for RxState only */ - HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ - HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state - Value is allowed for gState only */ - HAL_UART_STATE_ERROR = 0xE0U /*!< Error - Value is allowed for gState only */ -} HAL_UART_StateTypeDef; +typedef uint32_t HAL_UART_StateTypeDef; /** * @brief UART clock sources definition @@ -239,20 +216,20 @@ typedef struct __UART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ #ifdef HAL_MDMA_MODULE_ENABLED - MDMA_HandleTypeDef *hmdmatx; /*!< UART Tx MDMA Handle parameters */ + MDMA_HandleTypeDef *hmdmatx; /*!< UART Tx MDMA Handle parameters */ - MDMA_HandleTypeDef *hmdmarx; /*!< UART Rx MDMA Handle parameters */ + MDMA_HandleTypeDef *hmdmarx; /*!< UART Rx MDMA Handle parameters */ +#endif /* HAL_MDMA_MODULE_ENABLED */ -#endif HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management @@ -322,6 +299,30 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @{ */ +/** @defgroup UART_State_Definition UART State Code Definition + * @{ + */ +#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ +#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + /** @defgroup UART_Error_Definition UART Error Definition * @{ */ @@ -331,8 +332,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ #define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ #define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */ + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ +#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} @@ -422,7 +425,6 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ #define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ #define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ - /** * @} */ @@ -438,11 +440,11 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @} */ -/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout * @{ */ -#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */ -#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ /** * @} */ @@ -696,6 +698,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ #define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ #define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ #define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ #define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ #define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ @@ -721,6 +724,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * - 10: CR2 register * - 11: CR3 register * - ZZZZZ : Flag position in the ISR register(5bits) + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ #define UART_IT_PE 0x0028U /*!< UART parity error interruption */ @@ -738,17 +749,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ #define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ #define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ -/* Elements values convention: 000000000XXYYYYYb - - YYYYY : Interrupt source position in the XX register (5bits) - - XX : Interrupt source register (2bits) - - 01: CR1 register - - 10: CR2 register - - 11: CR3 register */ #define UART_IT_ERR 0x0060U /*!< UART error interruption */ -/* Elements values convention: 0000ZZZZ00000000b - - ZZZZ : Flag position in the ISR register(4bits) */ #define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ #define UART_IT_NE 0x0200U /*!< UART noise error interruption */ #define UART_IT_FE 0x0100U /*!< UART frame error interruption */ @@ -770,6 +774,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ /** * @} */ @@ -808,9 +813,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ - } while(0U) + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified UART pending flag. * @param __HANDLE__ specifies the UART Handle. @@ -823,6 +828,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag * @arg @ref UART_CLEAR_CMF Character Match Clear Flag @@ -891,6 +897,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_FLAG_TC Transmission Complete flag * @arg @ref UART_FLAG_RXNE Receive data register not empty flag * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag * @arg @ref UART_FLAG_IDLE Idle Line detection flag * @arg @ref UART_FLAG_ORE Overrun Error flag * @arg @ref UART_FLAG_NE Noise Error flag @@ -917,9 +924,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) * @retval None */ #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ @@ -944,6 +952,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) @@ -970,12 +979,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) /** @brief Check whether the specified UART interrupt source is enabled or not. * @param __HANDLE__ specifies the UART Handle. @@ -994,14 +1005,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the UART Handle. @@ -1013,6 +1025,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag @@ -1034,7 +1047,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request * @retval None */ -#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__)) +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable the UART one bit sample method. * @param __HANDLE__ specifies the UART Handle. @@ -1164,7 +1177,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U) + ((__BAUD__)/2U)) / (__BAUD__)) +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1172,7 +1186,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__))) + ((__BAUD__)/2U)) / (__BAUD__)) +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Check UART Baud rate. @@ -1221,10 +1236,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) */ #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ - (((__CONTROL__) == UART_HWCONTROL_NONE) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS) || \ - ((__CONTROL__) == UART_HWCONTROL_CTS) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) /** * @brief Ensure that UART communication mode is valid. @@ -1272,8 +1287,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __TIMEOUT__ UART receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ -#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ - ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) /** * @brief Ensure that UART LIN state is valid. @@ -1492,7 +1514,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -1541,12 +1564,17 @@ void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); */ /* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + /** * @} */ @@ -1571,10 +1599,13 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); /** @addtogroup UART_Private_Functions UART Private Functions * @{ */ - +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); /** @@ -1593,6 +1624,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); } #endif -#endif /* __STM32MP1xx_HAL_UART_H */ +#endif /* STM32MP1xx_HAL_UART_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart_ex.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart_ex.h index bb7612a294..6c4e326096 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart_ex.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart_ex.h @@ -18,8 +18,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32MP1xx_HAL_UART_EX_H -#define __STM32MP1xx_HAL_UART_EX_H +#ifndef STM32MP1xx_HAL_UART_EX_H +#define STM32MP1xx_HAL_UART_EX_H #ifdef __cplusplus extern "C" { @@ -46,7 +46,7 @@ extern "C" { */ typedef struct { - uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF). + uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must be filled up. */ @@ -69,9 +69,9 @@ typedef struct /** @defgroup UARTEx_Word_Length UARTEx Word Length * @{ */ -#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ /** * @} */ @@ -79,8 +79,8 @@ typedef struct /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length * @{ */ -#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ /** * @} */ @@ -89,8 +89,8 @@ typedef struct * @brief UART FIFO mode * @{ */ -#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ /** * @} */ @@ -138,7 +138,8 @@ typedef struct */ /* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); /** * @} @@ -165,7 +166,9 @@ void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); @@ -321,7 +324,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 case RCC_USART6CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ break; \ - case RCC_USART6CLKSOURCE_PLL4: \ + case RCC_USART6CLKSOURCE_PLL4: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL4Q; \ break; \ case RCC_USART6CLKSOURCE_HSI: \ @@ -386,6 +389,10 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 break; \ } \ } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ } while(0U) /** @brief Report the UART mask to apply to retrieve the received data @@ -399,41 +406,44 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 */ #define UART_MASK_COMPUTATION(__HANDLE__) \ do { \ - if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x01FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x003FU ; \ - } \ - } \ -} while(0U) - + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) /** * @brief Ensure that UART frame length is valid. @@ -494,6 +504,6 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 } #endif -#endif /* __STM32MP1xx_HAL_UART_EX_H */ +#endif /* STM32MP1xx_HAL_UART_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h index 635eb66c5b..8a3980fe45 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h @@ -2338,11 +2338,13 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) } /** - * @brief Set parameter common to several ADC: measurement path to internal - * channels (VrefInt, temperature sensor, ...). + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Configure all paths (overwrite current configuration). * @note One or several values can be selected. * Example: (LL_ADC_PATH_INTERNAL_VREFINT | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * The values not selected are removed from configuration. * @note Stabilization time of measurement path to internal channel: * After enabling internal paths, before starting ADC conversion, * a delay is required for internal voltage reference and @@ -2388,6 +2390,99 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO } } +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Add paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @note On this STM32 serie, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n + * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n + * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE (1) + * + * (1) On STM32MP1, parameter available only on ADC instance: ADC2. + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + if(PathInternal == LL_ADC_PATH_INTERNAL_VDDCORE) + { + /* Feature limited to ADC instance ADC2 */ + SET_BIT(ADC2->OR, ADC2_OR_VDDCOREEN); + } + else + { + SET_BIT(ADCxy_COMMON->CCR, PathInternal); + } +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Remove paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note On this STM32 serie, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n + * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n + * CCR VBATEN LL_ADC_SetCommonPathInternalChRem + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE (1) + * + * (1) On STM32MP1, parameter available only on ADC instance: ADC2. + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + if(PathInternal == LL_ADC_PATH_INTERNAL_VDDCORE) + { + /* Feature limited to ADC instance ADC2 */ + CLEAR_BIT(ADC2->OR, ADC2_OR_VDDCOREEN); + } + else + { + CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal); + } +} + /** * @brief Get parameter common to several ADC: measurement path to internal * channels (VrefInt, temperature sensor, ...). @@ -3527,7 +3622,11 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) * - Transfered to DFSDM data register * @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode * @param ADCx ADC instance - * @param DataTransferMode Select Data Management configuration + * @param DataTransferMode This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_DR_TRANSFER + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + * @arg @ref LL_ADC_REG_DFSDM_TRANSFER * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode) diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_cortex.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_cortex.h new file mode 100644 index 0000000000..b08766bc37 --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_cortex.h @@ -0,0 +1,311 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) API to access to MCU info (CPUID register) + + @endverbatim + ****************************************************************************** +$LICENSE$ + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32MP1xx_LL_CORTEX_H +#define __STM32MP1xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx.h" + +/** @addtogroup STM32MP1xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Architecture number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture + * @retval Value should be equal to 0xC for Cortex-M0 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC20 for Cortex-M0 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32MP1xx_LL_CORTEX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_fmc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_fmc.h new file mode 100644 index 0000000000..4cd0b72ae6 --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_fmc.h @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_ll_fmc.h + * @author MCD Application Team + * @brief Header file of FMC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32MP1xx_LL_FMC_H +#define STM32MP1xx_LL_FMC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_hal_def.h" + +/** @addtogroup STM32MP1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FMC_LL + * @{ + */ + +/** @addtogroup FMC_LL_Private_Macros + * @{ + */ + +#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ + ((__BANK__) == FMC_NORSRAM_BANK2) || \ + ((__BANK__) == FMC_NORSRAM_BANK3) || \ + ((__BANK__) == FMC_NORSRAM_BANK4)) +#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) +#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) +#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16)) +#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ + ((__SIZE__) == FMC_PAGE_SIZE_128) || \ + ((__SIZE__) == FMC_PAGE_SIZE_256) || \ + ((__SIZE__) == FMC_PAGE_SIZE_512) || \ + ((__SIZE__) == FMC_PAGE_SIZE_1024)) +#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ + ((__MODE__) == FMC_ACCESS_MODE_B) || \ + ((__MODE__) == FMC_ACCESS_MODE_C) || \ + ((__MODE__) == FMC_ACCESS_MODE_D)) +#define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ + ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ + ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ + ((__NBL__) == FMC_NBL_SETUPTIME_3)) +#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) +#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) +#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) +#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) +#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) +#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) +#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) +#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) +#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FMC_WRITE_BURST_ENABLE)) +#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ + ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) +#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) +#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) +#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) +#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) +#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) +#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) +#define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U)) + + +/** + * @} + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types + * @{ + */ + +#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef +#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef + +#define FMC_NORSRAM_DEVICE FMC_Bank1_R +#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R + +/** + * @brief FMC NORSRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. + This parameter can be a value of @ref FMC_NORSRAM_Bank */ + + uint32_t DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the data bus or not. + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + + uint32_t MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory device. + This parameter can be a value of @ref FMC_Memory_Type */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + + uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FMC_Burst_Access_Mode */ + + uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + + uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FMC_Wait_Timing */ + + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ + + uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal */ + + uint32_t ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FMC_Extended_Mode */ + + uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FMC_AsynchronousWait */ + + uint32_t WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FMC_Write_Burst */ + + uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. + This parameter is only enabled through the FMC_BCR1 register, and don't care + through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Continous_Clock */ + + uint32_t PageSize; /*!< Specifies the memory page size. + This parameter can be a value of @ref FMC_Page_Size */ + + uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number + This parameter can be a value of @ref FMC_Byte_Lane */ + + FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this NSBank + for PSRAM refresh. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for synchronous + accesses and in HCLK cycles for asynchronous accesses, + valid only if MaxChipSelectPulse is ENABLE. + This parameter can be a value between Min_Data = 1 and Max_Data = 65535. + @note: This parameter is common to all NSBank. */ +}FMC_NORSRAM_InitTypeDef; + +/** + * @brief FMC NORSRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between Min_Data = 1 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between Min_Data = 1 and Max_Data = 255. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed + NOR Flash memories. */ + + uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data hold time. + This parameter can be a value between Min_Data = 0 and Max_Data = 3. + @note This parameter is used for used in asynchronous accesses. */ + + uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is only used for multiplexed NOR Flash memories. */ + + uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of + HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM + accesses. */ + + uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The parameter value depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FMC_Access_Mode */ +}FMC_NORSRAM_TimingTypeDef; + + + + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants + * @{ + */ + +/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller + * @{ + */ + +/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank + * @{ + */ +#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) +#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) +#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) +#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) +/** + * @} + */ + +/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing + * @{ + */ +#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) +#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U) +/** + * @} + */ + +/** @defgroup FMC_Memory_Type FMC Memory Type + * @{ + */ +#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) +#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U) +#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width + * @{ + */ +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access + * @{ + */ +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode + * @{ + */ +#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) +#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity + * @{ + */ +#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Timing FMC Wait Timing + * @{ + */ +#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) +#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U) +/** + * @} + */ + +/** @defgroup FMC_Write_Operation FMC Write Operation + * @{ + */ +#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) +#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal FMC Wait Signal + * @{ + */ +#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) +#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U) +/** + * @} + */ + +/** @defgroup FMC_Extended_Mode FMC Extended Mode + * @{ + */ +#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) +#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U) +/** + * @} + */ + +/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait + * @{ + */ +#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U) +/** + * @} + */ + +/** @defgroup FMC_Page_Size FMC Page Size + * @{ + */ +#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U) +#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0) +#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1) +#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1)) +#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2) +/** + * @} + */ + +/** @defgroup FMC_Write_Burst FMC Write Burst + * @{ + */ +#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) +#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U) +/** + * @} + */ + +/** @defgroup FMC_Continous_Clock FMC Continuous Clock + * @{ + */ +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U) +/** + * @} + */ + + /** @defgroup FMC_Access_Mode FMC Access Mode + * @{ + */ +#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U) +#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U) +#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U) +#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U) +/** + * @} + */ + +/** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup + * @{ + */ +#define FMC_NBL_SETUPTIME_0 ((uint32_t)0x00000000U) +#define FMC_NBL_SETUPTIME_1 ((uint32_t)0x00400000U) +#define FMC_NBL_SETUPTIME_2 ((uint32_t)0x00800000U) +#define FMC_NBL_SETUPTIME_3 ((uint32_t)0x00C00000U) +/** + * @} + */ + +/** + * @} + */ + + + +/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition + * @{ + */ +/** + * @} + */ + +/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros + * @{ + */ + /** + * @brief Enable the FMC Peripheral. + * @retval None + */ +#define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN) + +/** + * @brief Disable the FMC Peripheral. + * @retval None + */ +#define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN) +/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros + * @brief macros to handle NOR device enable/disable and read/write operations + * @{ + */ + +/** + * @brief Enable the NORSRAM device access. + * @param __INSTANCE__ FMC_NORSRAM Instance + * @param __BANK__ FMC_NORSRAM Bank + * @retval None + */ +#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN) + +/** + * @brief Disable the NORSRAM device access. + * @param __INSTANCE__ FMC_NORSRAM Instance + * @param __BANK__ FMC_NORSRAM Bank + * @retval None + */ +#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN) + +/** + * @} + */ + + + + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions + * @{ + */ + +/** @defgroup FMC_LL_NORSRAM NOR SRAM + * @{ + */ +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions + * @{ + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ +/** + * @} + */ + + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32MP1xx_LL_FMC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_gpio.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_gpio.h index bc7a30a132..e779cd0399 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_gpio.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_gpio.h @@ -525,7 +525,7 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. * @note Possible values are from AF0 to AF15 depending on target. * @note Warning: only one pin can be passed as parameter. - * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @rmtoll AFRL AFRy LL_GPIO_SetAFPin_0_7 * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_0 @@ -557,13 +557,13 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) */ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), + MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFR0), ((((Pin * Pin) * Pin) * Pin) * Alternate)); } /** * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @rmtoll AFRL AFRy LL_GPIO_GetAFPin_0_7 * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_0 @@ -595,14 +595,14 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[0], - ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); + ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFR0)) / (((Pin * Pin) * Pin) * Pin)); } /** * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. * @note Possible values are from AF0 to AF15 depending on target. * @note Warning: only one pin can be passed as parameter. - * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @rmtoll AFRH AFRy LL_GPIO_SetAFPin_8_15 * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_8 @@ -634,14 +634,14 @@ __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) */ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), + MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFR8), (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); } /** * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. * @note Possible values are from AF0 to AF15 depending on target. - * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @rmtoll AFRH AFRy LL_GPIO_GetAFPin_8_15 * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_8 @@ -673,7 +673,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[1], - (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFR8)) / ((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); } diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rcc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rcc.h index aa2be745d1..5f7bb05319 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rcc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rcc.h @@ -98,6 +98,10 @@ extern "C" { */ /* Private macros ------------------------------------------------------------*/ +#if !defined (UNUSED) +#define UNUSED(x) ((void)(x)) +#endif + #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_Private_Macros RCC Private Macros * @{ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rtc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rtc.h new file mode 100644 index 0000000000..2585f829e7 --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rtc.h @@ -0,0 +1,4802 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_ll_rtc.h + * @author MCD Application Team + * @brief Header file of RTC LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32MP1xx_LL_RTC_H +#define STM32MP1xx_LL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx.h" + +/** @addtogroup STM32MP1xx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @defgroup RTC_LL RTC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTC_LL_Private_Constants RTC Private Constants + * @{ + */ +/* Masks Definition */ +#define RTC_LL_INIT_MASK 0xFFFFFFFFU +#define RTC_LL_RSF_MASK 0xFFFFFF5FU + +/* Write protection defines */ +#define RTC_WRITE_PROTECTION_DISABLE (uint8_t)0xFF +#define RTC_WRITE_PROTECTION_ENABLE_1 (uint8_t)0xCA +#define RTC_WRITE_PROTECTION_ENABLE_2 (uint8_t)0x53 + +/* Defines used to combine date & time */ +#define RTC_OFFSET_WEEKDAY 24U +#define RTC_OFFSET_DAY 16U +#define RTC_OFFSET_MONTH 8U +#define RTC_OFFSET_HOUR 16U +#define RTC_OFFSET_MINUTE 8U + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_Private_Macros RTC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +#if !defined (UNUSED) +#define UNUSED(x) ((void)(x)) +#endif + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure + * @{ + */ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t HourFormat; /*!< Specifies the RTC Hours Format. + This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetHourFormat(). */ + + uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetAsynchPrescaler(). */ + + uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetSynchPrescaler(). */ +} LL_RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */ + + uint8_t Hours; /*!< Specifies the RTC Time Hours. + This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected. + This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected. + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */ +} LL_RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_LL_EC_WEEKDAY + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */ + + uint8_t Month; /*!< Specifies the RTC Date Month. + This parameter can be a value of @ref RTC_LL_EC_MONTH + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */ + + uint8_t Day; /*!< Specifies the RTC Date Day. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */ +} LL_RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B. + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A + or @ref LL_RTC_ALMB_SetMask() for ALARM B + */ + + uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay. + This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday() + for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B + */ + + uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay. + If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31. + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay() + for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B. + + If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY. + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay() + for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B. + */ +} LL_RTC_AlarmTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants + * @{ + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EC_FORMAT FORMAT + * @{ + */ +#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay + * @{ + */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay + * @{ + */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm B Date is selected */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */ +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RTC_ReadReg function + * @{ + */ +#define LL_RTC_SCR_ITSF RTC_SCR_CITSF +#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF +#define LL_RTC_SCR_TSF RTC_SCR_CTSF +#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF +#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF +#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF + +#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF +#define LL_RTC_ICSR_INITF RTC_ICSR_INITF +#define LL_RTC_ICSR_RSF RTC_ICSR_RSF +#define LL_RTC_ICSR_INITS RTC_ICSR_INITS +#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF +#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF +/** + * @} + */ + +/** @defgroup RTC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions + * @{ + */ +#define LL_RTC_CR_TSIE RTC_CR_TSIE +#define LL_RTC_CR_WUTIE RTC_CR_WUTIE +#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE +#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE +/** + * @} + */ + +/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY + * @{ + */ +#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01 /*!< Monday */ +#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02 /*!< Tuesday */ +#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03 /*!< Wednesday */ +#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04 /*!< Thrusday */ +#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05 /*!< Friday */ +#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06 /*!< Saturday */ +#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07 /*!< Sunday */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_MONTH MONTH + * @{ + */ +#define LL_RTC_MONTH_JANUARY (uint8_t)0x01 /*!< January */ +#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02 /*!< February */ +#define LL_RTC_MONTH_MARCH (uint8_t)0x03 /*!< March */ +#define LL_RTC_MONTH_APRIL (uint8_t)0x04 /*!< April */ +#define LL_RTC_MONTH_MAY (uint8_t)0x05 /*!< May */ +#define LL_RTC_MONTH_JUNE (uint8_t)0x06 /*!< June */ +#define LL_RTC_MONTH_JULY (uint8_t)0x07 /*!< July */ +#define LL_RTC_MONTH_AUGUST (uint8_t)0x08 /*!< August */ +#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09 /*!< September */ +#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10 /*!< October */ +#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11 /*!< November */ +#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12 /*!< December */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT + * @{ + */ +#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */ +#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT + * @{ + */ +#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */ +#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */ +#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */ +#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE + * @{ + */ +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */ +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U /*!< RTC_ALARM is push-pull output */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN + * @{ + */ +#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/ +#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT + * @{ + */ +#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND + * @{ + */ +#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */ +#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK + * @{ + */ +#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/ +#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT + * @{ + */ +#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK + * @{ + */ +#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/ +#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT + * @{ + */ +#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE + * @{ + */ +#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */ +#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT + * @{ + */ +#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER TAMPER + * @{ + */ +#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */ +#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */ +#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */ + +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK + * @{ + */ +#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ +#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE + * @{ + */ +#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */ +#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */ +#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */ + +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION + * @{ + */ +#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER + * @{ + */ +#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ +#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER + * @{ + */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL + * @{ + */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ + +/** + * @} + */ + + +/** @defgroup RTC_LL_EC_INTERNAL INTERNAL TAMPER + * @{ + */ +#define LL_RTC_TAMPER_ITAMP1 TAMP_CR1_ITAMP1E /*!< Internal tamper 1: RTC supply voltage monitoring */ +#define LL_RTC_TAMPER_ITAMP2 TAMP_CR1_ITAMP2E /*!< Internal tamper 2: Temperature monitoring */ +#define LL_RTC_TAMPER_ITAMP3 TAMP_CR1_ITAMP3E /*!< Internal tamper 3: LSE monitoring */ +#define LL_RTC_TAMPER_ITAMP4 TAMP_CR1_ITAMP4E /*!< Internal tamper 4 enable: HSE monitoring */ +#define LL_RTC_TAMPER_ITAMP5 TAMP_CR1_ITAMP5E /*!< Internal tamper 5: RTC calendar overflow */ +#define LL_RTC_TAMPER_ITAMP8 TAMP_CR1_ITAMP8E /*!< Internal tamper 8: Monotonic counter overflow */ +/** + * @} + */ + + +/** @defgroup RTC_LL_EC_ACTIVE_MODE ACTIVE TAMPER MODE + * @{ + */ +#define LL_RTC_TAMPER_ATAMP_TAMP1AM TAMP_ATCR1_TAMP1AM /*!< tamper 1 is active */ +#define LL_RTC_TAMPER_ATAMP_TAMP2AM TAMP_ATCR1_TAMP2AM /*!< tamper 2 is active */ +#define LL_RTC_TAMPER_ATAMP_TAMP3AM TAMP_ATCR1_TAMP3AM /*!< tamper 3 is active */ + +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ACTIVE_ASYNC_PRESCALER ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK + * @{ + */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0u /*!< RTCCLK */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +/** + * @} + */ + + +/** @defgroup RTC_LL_EC_BKP BACKUP + * @{ + */ +#define LL_RTC_BKP_NUMBER RTC_BACKUP_NB +#define LL_RTC_BKP_DR0 0U +#define LL_RTC_BKP_DR1 1U +#define LL_RTC_BKP_DR2 2U +#define LL_RTC_BKP_DR3 3U +#define LL_RTC_BKP_DR4 4U +#define LL_RTC_BKP_DR5 5U +#define LL_RTC_BKP_DR6 6U +#define LL_RTC_BKP_DR7 7U +#define LL_RTC_BKP_DR8 8U +#define LL_RTC_BKP_DR9 9U +#define LL_RTC_BKP_DR10 10U +#define LL_RTC_BKP_DR11 11U +#define LL_RTC_BKP_DR12 12U +#define LL_RTC_BKP_DR13 13U +#define LL_RTC_BKP_DR14 14U +#define LL_RTC_BKP_DR15 15U +#define LL_RTC_BKP_DR16 16U +#define LL_RTC_BKP_DR17 17U +#define LL_RTC_BKP_DR18 18U +#define LL_RTC_BKP_DR19 19U +#define LL_RTC_BKP_DR20 20U +#define LL_RTC_BKP_DR21 21U +#define LL_RTC_BKP_DR22 22U +#define LL_RTC_BKP_DR23 23U +#define LL_RTC_BKP_DR24 24U +#define LL_RTC_BKP_DR25 25U +#define LL_RTC_BKP_DR26 26U +#define LL_RTC_BKP_DR27 27U +#define LL_RTC_BKP_DR28 28U +#define LL_RTC_BKP_DR29 29U +#define LL_RTC_BKP_DR30 30U +#define LL_RTC_BKP_DR31 31U +/** + * @} + */ + +/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV + * @{ + */ +#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0 /*!< RTC/8 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1 /*!< RTC/4 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2 /*!< ck_spre (usually 1 Hz) clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output + * @{ + */ +#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */ +#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */ +#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE /*!< Calibration output is 512 Hz */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion + * @{ + */ +#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */ +#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period + * @{ + */ +#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_LOWPOWER Calibration low power + * @{ + */ +#define LL_RTC_CALIB_LOWPOWER_NONE 0x00000000U /*!< High conso mode */ +#define LL_RTC_CALIB_LOWPOWER_SET RTC_CALR_LPCAL /*!< low power mode */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_SECURE_RTC_FULL Secure full rtc + * @{ + */ +#define LL_RTC_SECURE_FULL_YES 0U /*!< RTC full secure */ +#define LL_RTC_SECURE_FULL_NO RTC_SMCR_DECPROT /*!< RTC is not full secure, features can be unsecure. See RTC_LL_EC_UNSECURE_RTC_FEATURE */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_UNSECURE_RTC_FEATURE UnSecure features rtc in case of LL_RTC_SECURE_FULL_NO. + * @{ + */ +#define LL_RTC_UNSECURE_FEATURE_INIT RTC_SMCR_INITDPROT /*!< Initialization feature is not secure */ +#define LL_RTC_UNSECURE_FEATURE_CAL RTC_SMCR_CALDPROT /*!< Calibration feature is not secure */ +#define LL_RTC_UNSECURE_FEATURE_TS RTC_SMCR_TSDPROT /*!< Time stamp feature is not secure */ +#define LL_RTC_UNSECURE_FEATURE_WUT RTC_SMCR_WUTDPROT /*!< Wake up timer feature is not secure */ +#define LL_RTC_UNSECURE_FEATURE_ALRA RTC_SMCR_ALRADPROT /*!< Alarm A feature is not secure */ +#define LL_RTC_UNSECURE_FEATURE_ALRB RTC_SMCR_ALRBDPROT /*!< Alarm B feature is not secure */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_SECURE_TAMP Secure tamp + * @{ + */ +#define LL_TAMP_SECURE_FULL_YES 0U /*!< TAMP full secure */ +#define LL_TAMP_SECURE_FULL_NO TAMP_SMCR_TAMPDPROT /*!< TAMP is not secure */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Convert Convert helper Macros + * @{ + */ + +/** + * @brief Helper macro to convert a value from 2 digit decimal format to BCD format + * @param __VALUE__ Byte to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) ((uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))) + +/** + * @brief Helper macro to convert a value from BCD format to 2 digit decimal format + * @param __VALUE__ BCD value to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU))) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Date Date helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve weekday. + * @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Year in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Year in BCD format (0x00 . . . 0x99) + */ +#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Month in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Day in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Day in BCD format (0x01 . . . 0x31) + */ +#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Time Time helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve hour in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23) + */ +#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve minute in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Minutes in BCD format (0x00. . .0x59) + */ +#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve second in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Seconds in format (0x00. . .0x59) + */ +#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Set Hours format (24 hour/day or AM/PM hour format) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR FMT LL_RTC_SetHourFormat + * @param RTCx RTC Instance + * @param HourFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_HOURFORMAT_24HOUR + * @arg @ref LL_RTC_HOURFORMAT_AMPM + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat) +{ + MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); +} + +/** + * @brief Get Hours format (24 hour/day or AM/PM hour format) + * @rmtoll RTC_CR FMT LL_RTC_GetHourFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_HOURFORMAT_24HOUR + * @arg @ref LL_RTC_HOURFORMAT_AMPM + */ +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); +} + +/** + * @brief Select the flag to be routed to RTC_ALARM output + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR OSEL LL_RTC_SetAlarmOutEvent + * @param RTCx RTC Instance + * @param AlarmOutput This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_DISABLE + * @arg @ref LL_RTC_ALARMOUT_ALMA + * @arg @ref LL_RTC_ALARMOUT_ALMB + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput) +{ + MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput); +} + +/** + * @brief Get the flag to be routed to RTC_ALARM output + * @rmtoll RTC_CR OSEL LL_RTC_GetAlarmOutEvent + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_DISABLE + * @arg @ref LL_RTC_ALARMOUT_ALMA + * @arg @ref LL_RTC_ALARMOUT_ALMB + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); +} + +/** + * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType + * @param RTCx RTC Instance + * @param Output This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output) +{ + MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output); +} + +/** + * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE)); +} + +/** + * @brief Enable initialization mode + * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) + * and prescaler register (RTC_PRER). + * Counters are stopped and start counting from the new value when INIT is reset. + * @rmtoll RTC_ICSR INIT LL_RTC_EnableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) +{ + /* Set the Initialization mode */ + SET_BIT(RTCx->ICSR, RTC_ICSR_INIT); +} + +/** + * @brief Disable initialization mode (Free running mode) + * @rmtoll RTC_ICSR INIT LL_RTC_DisableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) +{ + /* Exit Initialization mode */ + CLEAR_BIT(RTCx->ICSR, RTC_ICSR_INIT); + +} + +/** + * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR POL LL_RTC_SetOutputPolarity + * @param RTCx RTC Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity) +{ + MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); +} + +/** + * @brief Get Output polarity + * @rmtoll RTC_CR POL LL_RTC_GetOutputPolarity + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + */ +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); +} + +/** + * @brief Enable Bypass the shadow registers + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BYPSHAD LL_RTC_EnableShadowRegBypass + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_BYPSHAD); +} + +/** + * @brief Disable Bypass the shadow registers + * @rmtoll RTC_CR BYPSHAD LL_RTC_DisableShadowRegBypass + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD); +} + +/** + * @brief Check if Shadow registers bypass is enabled or not. + * @rmtoll RTC_CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1U : 0U); +} + +/** + * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR REFCKON LL_RTC_EnableRefClock + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_REFCKON); +} + +/** + * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR REFCKON LL_RTC_DisableRefClock + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON); +} + +/** + * @brief Set Asynchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_A LL_RTC_SetAsynchPrescaler + * @param RTCx RTC Instance + * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) +{ + MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos); +} + +/** + * @brief Set Synchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_S LL_RTC_SetSynchPrescaler + * @param RTCx RTC Instance + * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler) +{ + MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler); +} + +/** + * @brief Get Asynchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_A LL_RTC_GetAsynchPrescaler + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0x7F + */ +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); +} + +/** + * @brief Get Synchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_S LL_RTC_GetSynchPrescaler + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF + */ +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); +} + +/** + * @brief Enable the write protection for RTC registers. + * @rmtoll RTC_WPR KEY LL_RTC_EnableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE); +} + +/** + * @brief Disable the write protection for RTC registers. + * @rmtoll RTC_WPR KEY LL_RTC_DisableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1); + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); +} + +/** + * @brief Enable tamper output. + * @note When the tamper output is enabled, all external and internal tamper flags + * are ORed and routed to the TAMPALRM output. + * @rmtoll RTC_CR TAMPOE LL_RTC_EnableTamperOutput + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Disable tamper output. + * @rmtoll RTC_CR TAMPOE LL_RTC_DisableTamperOutput + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Check if tamper output is enabled or not. + * @rmtoll RTC_CR TAMPOE LL_RTC_IsTamperOutputEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1U : 0U); +} + +/** + * @brief Enable internal pull-up in output mode. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU); +} + +/** + * @brief Disable internal pull-up in output mode. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU); +} + +/** + * @brief Check if internal pull-up in output mode is enabled or not. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_IsAlarmPullUpEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1U : 0U); +} + +/** + * @brief Enable RTC_OUT2 output + * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent) + * and COE (@ref LL_RTC_CAL_SetOutputFreq) settings. + * @note RTC_OUT2 is not available ins VBAT mode. + * @rmtoll RTC_CR OUT2EN LL_RTC_EnableOutput2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Disable RTC_OUT2 output + * @rmtoll RTC_CR OUT2EN LL_RTC_DisableOutput2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Check if RTC_OUT2 output is enabled or not. + * @rmtoll RTC_CR OUT2EN LL_RTC_IsOutput2Enabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Time Time + * @{ + */ + +/** + * @brief Set time format (AM/24-hour or PM notation) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_TR PM LL_RTC_TIME_SetFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); +} + +/** + * @brief Get time format (AM or PM notation) + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @rmtoll RTC_TR PM LL_RTC_TIME_GetFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); +} + +/** + * @brief Set Hours in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format + * @rmtoll RTC_TR HT LL_RTC_TIME_SetHour\n + * RTC_TR HU LL_RTC_TIME_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))); +} + +/** + * @brief Get Hours in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to + * Binary format + * @rmtoll RTC_TR HT LL_RTC_TIME_GetHour\n + * RTC_TR HU LL_RTC_TIME_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); +} + +/** + * @brief Set Minutes in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_TR MNT LL_RTC_TIME_SetMinute\n + * RTC_TR MNU LL_RTC_TIME_SetMinute + * @param RTCx RTC Instance + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU), + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos))); +} + +/** + * @brief Get Minutes in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD + * to Binary format + * @rmtoll RTC_TR MNT LL_RTC_TIME_GetMinute\n + * RTC_TR MNU LL_RTC_TIME_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); +} + +/** + * @brief Set Seconds in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_TR ST LL_RTC_TIME_SetSecond\n + * RTC_TR SU LL_RTC_TIME_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos))); +} + +/** + * @brief Get Seconds in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD + * to Binary format + * @rmtoll RTC_TR ST LL_RTC_TIME_GetSecond\n + * RTC_TR SU LL_RTC_TIME_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); +} + +/** + * @brief Set time (hour, minute and second) in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note TimeFormat and Hours should follow the same format + * @rmtoll RTC_TR PM LL_RTC_TIME_Config\n + * RTC_TR HT LL_RTC_TIME_Config\n + * RTC_TR HU LL_RTC_TIME_Config\n + * RTC_TR MNT LL_RTC_TIME_Config\n + * RTC_TR MNU LL_RTC_TIME_Config\n + * RTC_TR ST LL_RTC_TIME_Config\n + * RTC_TR SU LL_RTC_TIME_Config + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) +{ + register uint32_t temp; + + temp = Format12_24 | \ + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)); + MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp); +} + +/** + * @brief Get time (hour, minute and second) in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_TR HT LL_RTC_TIME_Get\n + * RTC_TR HU LL_RTC_TIME_Get\n + * RTC_TR MNT LL_RTC_TIME_Get\n + * RTC_TR MNU LL_RTC_TIME_Get\n + * RTC_TR ST LL_RTC_TIME_Get\n + * RTC_TR SU LL_RTC_TIME_Get + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +{ + register uint32_t temp; + + temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); + return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ + (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ + ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos))); +} + +/** + * @brief Memorize whether the daylight saving time change has been performed + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BKP LL_RTC_TIME_EnableDayLightStore + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_BKP); +} + +/** + * @brief Disable memorization whether the daylight saving time change has been performed. + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BKP LL_RTC_TIME_DisableDayLightStore + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_BKP); +} + +/** + * @brief Check if RTC Day Light Saving stored operation has been enabled or not + * @rmtoll RTC_CR BKP LL_RTC_TIME_IsDayLightStoreEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1U : 0U); +} + +/** + * @brief Subtract 1 hour (winter time change) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR SUB1H LL_RTC_TIME_DecHour + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_SUB1H); +} + +/** + * @brief Add 1 hour (summer time change) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ADD1H LL_RTC_TIME_IncHour + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ADD1H); +} + +/** + * @brief Get Sub second value in the synchronous prescaler counter. + * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through + * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar + * SubSeconds value in second fraction ratio with time unit following + * generic formula: + * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * This conversion can be performed only if no shift operation is pending + * (ie. SHFP=0) when PREDIV_S >= SS. + * @rmtoll RTC_SSR SS LL_RTC_TIME_GetSubSecond + * @param RTCx RTC Instance + * @retval Sub second value (number between 0 and 65535) + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); +} + +/** + * @brief Synchronize to a remote clock with a high degree of precision. + * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second. + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @rmtoll RTC_SHIFTR ADD1S LL_RTC_TIME_Synchronize\n + * RTC_SHIFTR SUBFS LL_RTC_TIME_Synchronize + * @param RTCx RTC Instance + * @param ShiftSecond This parameter can be one of the following values: + * @arg @ref LL_RTC_SHIFT_SECOND_DELAY + * @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE + * @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF) + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction) +{ + WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Date Date + * @{ + */ + +/** + * @brief Set Year in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format + * @rmtoll RTC_DR YT LL_RTC_DATE_SetYear\n + * RTC_DR YU LL_RTC_DATE_SetYear + * @param RTCx RTC Instance + * @param Year Value between Min_Data=0x00 and Max_Data=0x99 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))); +} + +/** + * @brief Get Year in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format + * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n + * RTC_DR YU LL_RTC_DATE_GetYear + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x99 + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); +} + +/** + * @brief Set Week day + * @rmtoll RTC_DR WDU LL_RTC_DATE_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos); +} + +/** + * @brief Get Week day + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); +} + +/** + * @brief Set Month in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format + * @rmtoll RTC_DR MT LL_RTC_DATE_SetMonth\n + * RTC_DR MU LL_RTC_DATE_SetMonth + * @param RTCx RTC Instance + * @param Month This parameter can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos))); +} + +/** + * @brief Get Month in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format + * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n + * RTC_DR MU LL_RTC_DATE_GetMonth + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); +} + +/** + * @brief Set Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_DR DT LL_RTC_DATE_SetDay\n + * RTC_DR DU LL_RTC_DATE_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos))); +} + +/** + * @brief Get Day in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n + * RTC_DR DU LL_RTC_DATE_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); +} + +/** + * @brief Set date (WeekDay, Day, Month and Year) in BCD format + * @rmtoll RTC_DR WDU LL_RTC_DATE_Config\n + * RTC_DR MT LL_RTC_DATE_Config\n + * RTC_DR MU LL_RTC_DATE_Config\n + * RTC_DR DT LL_RTC_DATE_Config\n + * RTC_DR DU LL_RTC_DATE_Config\n + * RTC_DR YT LL_RTC_DATE_Config\n + * RTC_DR YU LL_RTC_DATE_Config + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @param Month This parameter can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @param Year Value between Min_Data=0x00 and Max_Data=0x99 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year) +{ + register uint32_t temp; + + temp = (WeekDay << RTC_DR_WDU_Pos) | \ + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \ + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)); + + MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp); +} + +/** + * @brief Get date (WeekDay, Day, Month and Year) in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, + * and __LL_RTC_GET_DAY are available to get independently each parameter. + * @rmtoll RTC_DR WDU LL_RTC_DATE_Get\n + * RTC_DR MT LL_RTC_DATE_Get\n + * RTC_DR MU LL_RTC_DATE_Get\n + * RTC_DR DT LL_RTC_DATE_Get\n + * RTC_DR DU LL_RTC_DATE_Get\n + * RTC_DR YT LL_RTC_DATE_Get\n + * RTC_DR YU LL_RTC_DATE_Get + * @param RTCx RTC Instance + * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) +{ + register uint32_t temp; + + temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); + return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ + (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \ + (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \ + ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos))); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARMA ALARMA + * @{ + */ + +/** + * @brief Enable Alarm A + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRAE); +} + +/** + * @brief Disable Alarm A + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE); +} + +/** + * @brief Specify the Alarm A masks. + * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK3 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK2 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK1 LL_RTC_ALMA_SetMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask); +} + +/** + * @brief Get the Alarm A masks. + * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK3 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK2 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK1 LL_RTC_ALMA_GetMask + * @param RTCx RTC Instance + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); +} + +/** + * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) + * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); +} + +/** + * @brief Disable AlarmA Week day selection (DU[3:0] represents the date ) + * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); +} + +/** + * @brief Set ALARM A Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_SetDay\n + * RTC_ALRMAR DU LL_RTC_ALMA_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU), + (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos))); +} + +/** + * @brief Get ALARM A Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_GetDay\n + * RTC_ALRMAR DU LL_RTC_ALMA_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Set ALARM A Weekday + * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Get ALARM A Weekday + * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Set Alarm A time format (AM/24-hour or PM notation) + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_SetTimeFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat); +} + +/** + * @brief Get Alarm A time format (AM or PM notation) + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); +} + +/** + * @brief Set ALARM A Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_SetHour\n + * RTC_ALRMAR HU LL_RTC_ALMA_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU), + (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))); +} + +/** + * @brief Get ALARM A Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetHour\n + * RTC_ALRMAR HU LL_RTC_ALMA_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); +} + +/** + * @brief Set ALARM A Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_SetMinute\n + * RTC_ALRMAR MNU LL_RTC_ALMA_SetMinute + * @param RTCx RTC Instance + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU), + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos))); +} + +/** + * @brief Get ALARM A Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_GetMinute\n + * RTC_ALRMAR MNU LL_RTC_ALMA_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); +} + +/** + * @brief Set ALARM A Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_SetSecond\n + * RTC_ALRMAR SU LL_RTC_ALMA_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU), + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos))); +} + +/** + * @brief Get ALARM A Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_GetSecond\n + * RTC_ALRMAR SU LL_RTC_ALMA_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); +} + +/** + * @brief Set Alarm A Time (hour, minute and second) in BCD format + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR HT LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR HU LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR MNT LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR MNU LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR ST LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR SU LL_RTC_ALMA_ConfigTime + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) +{ + register uint32_t temp; + + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); + + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp); +} + +/** + * @brief Get Alarm B Time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR HU LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR MNT LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR MNU LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR ST LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR SU LL_RTC_ALMA_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx) +{ + return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx)); +} + +/** + * @brief Set Alarm A Mask the most-significant bits starting at this bit + * @note This register can be written only when ALRAE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask + * @param RTCx RTC Instance + * @param Mask Value between Min_Data=0x00 and Max_Data=0xF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @brief Get Alarm A Mask the most-significant bits starting at this bit + * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @brief Set Alarm A Sub seconds value + * @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_SetSubSecond + * @param RTCx RTC Instance + * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) +{ + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond); +} + +/** + * @brief Get Alarm A Sub seconds value + * @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_GetSubSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARMB ALARMB + * @{ + */ + +/** + * @brief Enable Alarm B + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRBE); +} + +/** + * @brief Disable Alarm B + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE); +} + +/** + * @brief Specify the Alarm B masks. + * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK3 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK2 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK1 LL_RTC_ALMB_SetMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMB_MASK_NONE + * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMB_MASK_HOURS + * @arg @ref LL_RTC_ALMB_MASK_MINUTES + * @arg @ref LL_RTC_ALMB_MASK_SECONDS + * @arg @ref LL_RTC_ALMB_MASK_ALL + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask); +} + +/** + * @brief Get the Alarm B masks. + * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK3 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK2 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK1 LL_RTC_ALMB_GetMask + * @param RTCx RTC Instance + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_RTC_ALMB_MASK_NONE + * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMB_MASK_HOURS + * @arg @ref LL_RTC_ALMB_MASK_MINUTES + * @arg @ref LL_RTC_ALMB_MASK_SECONDS + * @arg @ref LL_RTC_ALMB_MASK_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); +} + +/** + * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) + * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); +} + +/** + * @brief Disable AlarmB Week day selection (DU[3:0] represents the date ) + * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); +} + +/** + * @brief Set ALARM B Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_SetDay\n + * RTC_ALRMBR DU LL_RTC_ALMB_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU), + (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos))); +} + +/** + * @brief Get ALARM B Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_GetDay\n + * RTC_ALRMBR DU LL_RTC_ALMB_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Set ALARM B Weekday + * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Get ALARM B Weekday + * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Set ALARM B time format (AM/24-hour or PM notation) + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_SetTimeFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat); +} + +/** + * @brief Get ALARM B time format (AM or PM notation) + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); +} + +/** + * @brief Set ALARM B Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_SetHour\n + * RTC_ALRMBR HU LL_RTC_ALMB_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU), + (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))); +} + +/** + * @brief Get ALARM B Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetHour\n + * RTC_ALRMBR HU LL_RTC_ALMB_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); +} + +/** + * @brief Set ALARM B Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_SetMinute\n + * RTC_ALRMBR MNU LL_RTC_ALMB_SetMinute + * @param RTCx RTC Instance + * @param Minutes between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU), + (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos))); +} + +/** + * @brief Get ALARM B Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_GetMinute\n + * RTC_ALRMBR MNU LL_RTC_ALMB_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); +} + +/** + * @brief Set ALARM B Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_SetSecond\n + * RTC_ALRMBR SU LL_RTC_ALMB_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU), + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos))); +} + +/** + * @brief Get ALARM B Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_GetSecond\n + * RTC_ALRMBR SU LL_RTC_ALMB_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); +} + +/** + * @brief Set Alarm B Time (hour, minute and second) in BCD format + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR HT LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR HU LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR MNT LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR MNU LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR ST LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR SU LL_RTC_ALMB_ConfigTime + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) +{ + register uint32_t temp; + + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)); + + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp); +} + +/** + * @brief Get Alarm B Time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR HU LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR MNT LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR MNU LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR ST LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR SU LL_RTC_ALMB_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx) +{ + return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx)); +} + +/** + * @brief Set Alarm B Mask the most-significant bits starting at this bit + * @note This register can be written only when ALRBE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask + * @param RTCx RTC Instance + * @param Mask Value between Min_Data=0x00 and Max_Data=0xF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos); +} + +/** + * @brief Get Alarm B Mask the most-significant bits starting at this bit + * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); +} + +/** + * @brief Set Alarm B Sub seconds value + * @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_SetSubSecond + * @param RTCx RTC Instance + * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) +{ + MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond); +} + +/** + * @brief Get Alarm B Sub seconds value + * @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_GetSubSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Timestamp Timestamp + * @{ + */ + +/** + * @brief Enable internal event timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ITSE LL_RTC_TS_EnableInternalEvent + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ITSE); +} + +/** + * @brief Disable internal event timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ITSE LL_RTC_TS_DisableInternalEvent + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ITSE); +} + +/** + * @brief Enable Timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSE LL_RTC_TS_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TSE); +} + +/** + * @brief Disable Timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSE LL_RTC_TS_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TSE); +} + +/** + * @brief Set Time-stamp event active edge + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting + * @rmtoll RTC_CR TSEDGE LL_RTC_TS_SetActiveEdge + * @param RTCx RTC Instance + * @param Edge This parameter can be one of the following values: + * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING + * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) +{ + MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge); +} + +/** + * @brief Get Time-stamp event active edge + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSEDGE LL_RTC_TS_GetActiveEdge + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING + * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); +} + +/** + * @brief Get Timestamp AM/PM notation (AM or 24-hour format) + * @rmtoll RTC_TSTR PM LL_RTC_TS_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TS_TIME_FORMAT_AM + * @arg @ref LL_RTC_TS_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); +} + +/** + * @brief Get Timestamp Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_TSTR HT LL_RTC_TS_GetHour\n + * RTC_TSTR HU LL_RTC_TS_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); +} + +/** + * @brief Get Timestamp Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_TSTR MNT LL_RTC_TS_GetMinute\n + * RTC_TSTR MNU LL_RTC_TS_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); +} + +/** + * @brief Get Timestamp Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_TSTR ST LL_RTC_TS_GetSecond\n + * RTC_TSTR SU LL_RTC_TS_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); +} + +/** + * @brief Get Timestamp time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_TSTR HT LL_RTC_TS_GetTime\n + * RTC_TSTR HU LL_RTC_TS_GetTime\n + * RTC_TSTR MNT LL_RTC_TS_GetTime\n + * RTC_TSTR MNU LL_RTC_TS_GetTime\n + * RTC_TSTR ST LL_RTC_TS_GetTime\n + * RTC_TSTR SU LL_RTC_TS_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, + RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); +} + +/** + * @brief Get Timestamp Week day + * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); +} + +/** + * @brief Get Timestamp Month in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format + * @rmtoll RTC_TSDR MT LL_RTC_TS_GetMonth\n + * RTC_TSDR MU LL_RTC_TS_GetMonth + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); +} + +/** + * @brief Get Timestamp Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_TSDR DT LL_RTC_TS_GetDay\n + * RTC_TSDR DU LL_RTC_TS_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); +} + +/** + * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format + * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, + * and __LL_RTC_GET_DAY are available to get independently each parameter. + * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetDate\n + * RTC_TSDR MT LL_RTC_TS_GetDate\n + * RTC_TSDR MU LL_RTC_TS_GetDate\n + * RTC_TSDR DT LL_RTC_TS_GetDate\n + * RTC_TSDR DU LL_RTC_TS_GetDate + * @param RTCx RTC Instance + * @retval Combination of Weekday, Day and Month + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); +} + +/** + * @brief Get time-stamp sub second value + * @rmtoll RTC_TSSSR SS LL_RTC_TS_GetSubSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); +} + +/** + * @brief Activate timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPTS); +} + +/** + * @brief Disable timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS); +} + + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Tamper Tamper + * @{ + */ + +/** + * @brief Enable TAMPx input detection + * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Enable\n + * TAMP_CR1 TAMP2E... LL_RTC_TAMPER_Enable\n + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR1, Tamper); +} + +/** + * @brief Clear TAMPx input detection + * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Disable\n + * TAMP_CR1 TAMP2E... LL_RTC_TAMPER_Disable + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR1, Tamper); +} + +/** + * @brief Enable Tamper mask flag + * @note Associated Tamper IT must not enabled when tamper mask is set. + * @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_EnableMask\n + * TAMP_CR2 TAMP2MF... LL_RTC_TAMPER_EnableMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_MASK + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR2, Mask); +} + +/** + * @brief Disable Tamper mask flag + * @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_DisableMask\n + * TAMP_CR2 TAMP2MF... LL_RTC_TAMPER_DisableMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_MASK + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR2, Mask); +} + +/** + * @brief Enable backup register erase after Tamper event detection + * @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP\n + * TAMP_CR2 TAMP2NOERASE... LL_RTC_TAMPER_EnableEraseBKP + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_NOERASE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Disable backup register erase after Tamper event detection + * @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP\n + * TAMP_CR2 TAMP2NOERASE... LL_RTC_TAMPER_DisableEraseBKP + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_NOERASE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) + * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling) + * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Set RTC_TAMPx precharge duration + * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge + * @param RTCx RTC Instance + * @param Duration This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration); +} + +/** + * @brief Get RTC_TAMPx precharge duration + * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH)); +} + +/** + * @brief Set RTC_TAMPx filter count + * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_SetFilterCount + * @param RTCx RTC Instance + * @param FilterCount This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount); +} + +/** + * @brief Get RTC_TAMPx filter count + * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_GetFilterCount + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT)); +} + +/** + * @brief Set Tamper sampling frequency + * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq + * @param RTCx RTC Instance + * @param SamplingFreq This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq); +} + +/** + * @brief Get Tamper sampling frequency + * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ)); +} + +/** + * @brief Enable Active level for Tamper input + * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n + * TAMP_CR2 TAMP2TRG... LL_RTC_TAMPER_EnableActiveLevel + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_ACTIVELEVEL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Disable Active level for Tamper input + * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n + * TAMP_CR2 TAMP2TRG... LL_RTC_TAMPER_DisableActiveLevel + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_ACTIVELEVEL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR2, Tamper); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Internal_Tamper Internal Tamper + * @{ + */ + +/** + * @brief Enable internal tamper detection. + * @rmtoll TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Enable\n + * TAMP_CR1 ITAMP2E.. LL_RTC_TAMPER_ITAMP_Enable\n + * @param RTCx RTC Instance + * @param InternalTamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_INTERNAL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(RTC_TypeDef *RTCx, uint32_t InternalTamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR1, InternalTamper); +} + +/** + * @brief Disable internal tamper detection. + * @rmtoll TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Disable\n + * TAMP_CR1 ITAMP2E LL_RTC_TAMPER_ITAMP_Disable\n + * TAMP_CR1 ITAMP3E LL_RTC_TAMPER_ITAMP_Disable\n + * TAMP_CR1 ITAMP5E LL_RTC_TAMPER_ITAMP_Disable\n + * TAMP_CR1 ITAMP8E LL_RTC_TAMPER_ITAMP_Disable + * @param RTCx RTC Instance + * @param InternalTamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_INTERNAL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(RTC_TypeDef *RTCx, uint32_t InternalTamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR1, InternalTamper); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Active_Tamper Active Tamper + * @{ + */ +/** + * @brief Enable tamper active mode. + * @rmtoll TAMP_ATCR1 TAMP1AM LL_RTC_TAMPER_ATAMP_EnableActiveMode\n + * @rmtoll TAMP_ATCR1 TAMP2AM LL_RTC_TAMPER_ATAMP_EnableActiveMode\n + * @rmtoll TAMP_ATCR1 TAMPxAM LL_RTC_TAMPER_ATAMP_EnableActiveMode\n + * @param Tamper to configure as active. This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_ACTIVE_MODE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableActiveMode(uint32_t Tamper) +{ + SET_BIT(TAMP->ATCR1, Tamper); +} + +/** + * @brief Disable tamper active mode. + * @rmtoll TAMP_ATCR1 TAMP1AM LL_RTC_TAMPER_ATAMP_DisableActiveMode\n + * @rmtoll TAMP_ATCR1 TAMP2AM LL_RTC_TAMPER_ATAMP_DisableActiveMode\n + * @rmtoll TAMP_ATCR1 TAMPxAM LL_RTC_TAMPER_ATAMP_DisableActiveMode\n + * @param Tamper to configure as active. This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_ACTIVE_MODE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableActiveMode(uint32_t Tamper) +{ + CLEAR_BIT(TAMP->ATCR1, Tamper); +} + +/** + * @brief Enable active tamper filter. + * @rmtoll TAMP_ATCR1 FLTEN LL_RTC_TAMPER_ATAMP_EnableFilter\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableFilter(void) +{ + SET_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN); +} + +/** + * @brief Disable active tamper filter. + * @rmtoll TAMP_ATCR1 FLTEN LL_RTC_TAMPER_ATAMP_DisableFilter\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableFilter(void) +{ + CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN); +} + +/** + * @brief Set Active tamper output change period. + * @rmtoll TAMP_ATCR1 ATPER LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod\n + * @param ActiveOutputChangePeriod This parameter can be a value from 0 to 7 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod(uint32_t ActiveOutputChangePeriod) +{ + MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATPER, (ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos)); +} + +/** + * @brief Get Active tamper output change period. + * @rmtoll TAMP_ATCR1 ATPER LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod\n + * @retval Output change period. This parameter can be a value from 0 to 7. + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod(void) +{ + return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATPER) >> TAMP_ATCR1_ATPER_Pos); +} + +/** + * @brief Set Active tamper asynchronous prescaler clock selection. + * @rmtoll TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler\n + * @param ActiveAsynvPrescaler Specifies the Active Tamper asynchronous Prescaler clock. + This parameter can be a value of the following values: + * @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler(uint32_t ActiveAsynvPrescaler) +{ + MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL, ActiveAsynvPrescaler); +} + +/** + * @brief Get Active tamper asynchronous prescaler clock selection. + * @rmtoll TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler\n + * @retval One of @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler(void) +{ + return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL)); +} + +/** + * @brief Enable active tamper output sharing. + * @rmtoll TAMP_ATCR1 ATOSHARE LL_RTC_TAMPER_ATAMP_EnableOutputSharing\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableOutputSharing(void) +{ + SET_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE); +} + +/** + * @brief Disable active tamper output sharing. + * @rmtoll TAMP_ATCR1 ATOSHARE LL_RTC_TAMPER_ATAMP_DisableOutputSharing\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableOutputSharing(void) +{ + CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE); +} + +/** + * @brief Write active tamper seed. + * @rmtoll TAMP_ATSEEDR SEED LL_RTC_TAMPER_ATAMP_WriteSeed\n + * @param Seed + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_WriteSeed(uint32_t Seed) +{ + WRITE_REG(TAMP->ATSEEDR, Seed); +} + +/** + * @brief Get active tamper initialization status flag. + * @rmtoll TAMP_ATOR INITS LL_RTC_IsActiveFlag_ATAMP_INITS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_INITS(void) +{ + return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == (TAMP_ATOR_INITS)) ? 1U : 0U); +} + +/** + * @brief Get active tamper seed running status flag. + * @rmtoll TAMP_ATOR INITS LL_RTC_IsActiveFlag_ATAMP_INITS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF(void) +{ + return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) == (TAMP_ATOR_SEEDF)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Wakeup Wakeup + * @{ + */ + +/** + * @brief Enable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTE); +} + +/** + * @brief Disable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTE); +} + +/** + * @brief Check if Wakeup timer is enabled or not + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_IsEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1U : 0U); +} + +/** + * @brief Select Wakeup clock + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR WUTWF bit = 1 + * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_SetClock + * @param RTCx RTC Instance + * @param WakeupClock This parameter can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) +{ + MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); +} + +/** + * @brief Get Wakeup clock + * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_GetClock + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); +} + +/** + * @brief Set Wakeup auto-reload value + * @note Bit can be written only when WUTWF is set to 1 in RTC_ICSR + * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_SetAutoReload + * @param RTCx RTC Instance + * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value) +{ + MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); +} + +/** + * @brief Get Wakeup auto-reload value + * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_GetAutoReload + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers + * @{ + */ + +/** + * @brief Writes a data in a specified Backup data register. + * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_SetRegister + * @param RTCx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * ... + * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) +{ + register uint32_t tmp; + + UNUSED(RTCx); + + tmp = (uint32_t)(&(TAMP->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_GetRegister + * @param RTCx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * ... + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) +{ + register uint32_t tmp; + + UNUSED(RTCx); + + tmp = (uint32_t)(&(TAMP->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Calibration Calibration + * @{ + */ + +/** + * @brief Set Calibration output frequency (1 Hz or 512 Hz) + * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR COE LL_RTC_CAL_SetOutputFreq\n + * RTC_CR COSEL LL_RTC_CAL_SetOutputFreq + * @param RTCx RTC Instance + * @param Frequency This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency) +{ + MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency); +} + +/** + * @brief Get Calibration output frequency (1 Hz or 512 Hz) + * @rmtoll RTC_CR COE LL_RTC_CAL_GetOutputFreq\n + * RTC_CR COSEL LL_RTC_CAL_GetOutputFreq + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); +} + +/** + * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + * @rmtoll RTC_CALR CALP LL_RTC_CAL_SetPulse + * @param RTCx RTC Instance + * @param Pulse This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE + * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse); +} + +/** + * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm) + * @rmtoll RTC_CALR CALP LL_RTC_CAL_IsPulseInserted + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1U : 0U); +} + +/** + * @brief Set the calibration cycle period + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_SetPeriod\n + * RTC_CALR CALW16 LL_RTC_CAL_SetPeriod + * @param RTCx RTC Instance + * @param Period This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period); +} + +/** + * @brief Get the calibration cycle period + * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_GetPeriod\n + * RTC_CALR CALW16 LL_RTC_CAL_GetPeriod + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); +} + +/** + * @brief Set Calibration minus + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + * @rmtoll RTC_CALR CALM LL_RTC_CAL_SetMinus + * @param RTCx RTC Instance + * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus); +} + +/** + * @brief Get Calibration minus + * @rmtoll RTC_CALR CALM LL_RTC_CAL_GetMinus + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Internal Time-stamp flag + * @rmtoll RTC_SR ITSF LL_RTC_IsActiveFlag_ITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1U : 0U); +} + +/** + * @brief Get Recalibration pending Flag + * @rmtoll RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp overflow flag + * @rmtoll RTC_SR TSOVF LL_RTC_IsActiveFlag_TSOV + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp flag + * @rmtoll RTC_SR TSF LL_RTC_IsActiveFlag_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1U : 0U); +} + +/** + * @brief Get Wakeup timer flag + * @rmtoll RTC_SR WUTF LL_RTC_IsActiveFlag_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm B flag + * @rmtoll RTC_SR ALRBF LL_RTC_IsActiveFlag_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm A flag + * @rmtoll RTC_SR ALRAF LL_RTC_IsActiveFlag_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1U : 0U); +} + +/** + * @brief Clear Internal Time-stamp flag + * @rmtoll RTC_SCR CITSF LL_RTC_ClearFlag_ITS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CITSF); +} + +/** + * @brief Clear Time-stamp overflow flag + * @rmtoll RTC_SCR CTSOVF LL_RTC_ClearFlag_TSOV + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CTSOVF); +} + +/** + * @brief Clear Time-stamp flag + * @rmtoll RTC_SCR CTSF LL_RTC_ClearFlag_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CTSF); +} + +/** + * @brief Clear Wakeup timer flag + * @rmtoll RTC_SCR CWUTF LL_RTC_ClearFlag_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CWUTF); +} + +/** + * @brief Clear Alarm B flag + * @rmtoll RTC_SCR CALRBF LL_RTC_ClearFlag_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CALRBF); +} + +/** + * @brief Clear Alarm A flag + * @rmtoll RTC_SCR CALRAF LL_RTC_ClearFlag_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CALRAF); +} + +/** + * @brief Get Initialization flag + * @rmtoll RTC_ICSR INITF LL_RTC_IsActiveFlag_INIT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1U : 0U); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll RTC_ICSR RSF LL_RTC_IsActiveFlag_RS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1U : 0U); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll RTC_ICSR RSF LL_RTC_ClearFlag_RS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT))); +} + +/** + * @brief Get Initialization status flag + * @rmtoll RTC_ICSR INITS LL_RTC_IsActiveFlag_INITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1U : 0U); +} + +/** + * @brief Get Shift operation pending flag + * @rmtoll RTC_ICSR SHPF LL_RTC_IsActiveFlag_SHP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1U : 0U); +} + +/** + * @brief Get Wakeup timer write flag + * @rmtoll RTC_ICSR WUTWF LL_RTC_IsActiveFlag_WUTW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm A masked flag. + * @rmtoll RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm B masked flag. + * @rmtoll RTC_MISR ALRBMF LL_RTC_IsActiveFlag_ALRBM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1U : 0U); +} + +/** + * @brief Get Wakeup timer masked flag. + * @rmtoll RTC_MISR WUTMF LL_RTC_IsActiveFlag_WUTM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp masked flag. + * @rmtoll RTC_MISR TSMF LL_RTC_IsActiveFlag_TSM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp overflow masked flag. + * @rmtoll RTC_MISR TSOVMF LL_RTC_IsActiveFlag_TSOVM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1U : 0U); +} + +/** + * @brief Get Internal Time-stamp masked flag. + * @rmtoll RTC_MISR ITSMF LL_RTC_IsActiveFlag_ITSM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 1 detection flag. + * @rmtoll TAMP_SR TAMP1F LL_RTC_IsActiveFlag_TAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 2 detection flag. + * @rmtoll TAMP_SR TAMP2F LL_RTC_IsActiveFlag_TAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 3 detection flag. + * @rmtoll TAMP_SR TAMP3F LL_RTC_IsActiveFlag_TAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 1 detection flag. + * @rmtoll TAMP_SR ITAMP1F LL_RTC_IsActiveFlag_ITAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP1F) == (TAMP_SR_ITAMP1F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 2 detection flag. + * @rmtoll TAMP_SR ITAMP2F LL_RTC_IsActiveFlag_ITAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP2F) == (TAMP_SR_ITAMP2F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 3 detection flag. + * @rmtoll TAMP_SR ITAMP3F LL_RTC_IsActiveFlag_ITAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 4 detection flag. + * @rmtoll TAMP_SR ITAMP5F LL_RTC_IsActiveFlag_ITAMP4 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP4F) == (TAMP_SR_ITAMP4F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 5 detection flag. + * @rmtoll TAMP_SR ITAMP5F LL_RTC_IsActiveFlag_ITAMP5 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP5F) == (TAMP_SR_ITAMP5F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 8 detection flag. + * @rmtoll TAMP_SR ITAMP8F LL_RTC_IsActiveFlag_ITAMP8 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP8F) == (TAMP_SR_ITAMP8F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 1 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP1MF LL_RTC_IsActiveFlag_TAMP1M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 2 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP2MF LL_RTC_IsActiveFlag_TAMP2M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 3 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP3M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 1 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP1MF LL_RTC_IsActiveFlag_ITAMP1M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP1MF) == (TAMP_MISR_ITAMP1MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 2 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP2MF LL_RTC_IsActiveFlag_ITAMP2M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP2MF) == (TAMP_MISR_ITAMP2MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 3 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP3MF LL_RTC_IsActiveFlag_ITAMP3M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP3MF) == (TAMP_MISR_ITAMP3MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 4 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP4MF LL_RTC_IsActiveFlag_ITAMP4M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4M(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP4MF) == (TAMP_MISR_ITAMP4MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 5 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP5MF LL_RTC_IsActiveFlag_ITAMP5M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP5MF) == (TAMP_MISR_ITAMP5MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 8 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP8MF LL_RTC_IsActiveFlag_ITAMP8M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP8MF) == (TAMP_MISR_ITAMP8MF)) ? 1U : 0U); +} + +/** + * @brief Clear tamper 1 detection flag. + * @rmtoll TAMP_SCR CTAMP1F LL_RTC_ClearFlag_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP1F); +} + +/** + * @brief Clear tamper 2 detection flag. + * @rmtoll TAMP_SCR CTAMP2F LL_RTC_ClearFlag_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP2F); +} + +/** + * @brief Clear tamper 3 detection flag. + * @rmtoll TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP3F); +} + +/** + * @brief Clear internal tamper 1 detection flag. + * @rmtoll TAMP_SCR CITAMP1F LL_RTC_ClearFlag_ITAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP1F); +} + +/** + * @brief Clear internal tamper 2 detection flag. + * @rmtoll TAMP_SCR CITAMP2F LL_RTC_ClearFlag_ITAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP2F); +} + +/** + * @brief Clear internal tamper 3 detection flag. + * @rmtoll TAMP_SCR CITAMP3F LL_RTC_ClearFlag_ITAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP3F); +} + +/** + * @brief Clear internal tamper 4 detection flag. + * @rmtoll TAMP_SCR CITAMP4F LL_RTC_ClearFlag_ITAMP4 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP4(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP4F); +} + +/** + * @brief Clear internal tamper 5 detection flag. + * @rmtoll TAMP_SCR CITAMP5F LL_RTC_ClearFlag_ITAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP5F); +} + +/** + * @brief Clear internal tamper 8 detection flag. + * @rmtoll TAMP_SCR CITAMP8F LL_RTC_ClearFlag_ITAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP8F); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_SECURITY SECURITY_Management + * @{ + */ + +#if defined (CORTEX_IN_SECURE_STATE) +/** + * @brief Set RTC secure level. + * @note Unsecure features are relevant if LL_RTC_SECURE_FULL_NO. + * @rmtoll RTC_SMCR DECPROT LL_RTC_SetRtcSecure + * @rmtoll RTC_SMCR INITPROT LL_RTC_SetRtcSecure + * @rmtoll RTC_SMCR CALDPROT LL_RTC_SetRtcSecure + * @rmtoll RTC_SMCR TSDPROT LL_RTC_SetRtcSecure + * @rmtoll RTC_SMCR WUTDPROT LL_RTC_SetRtcSecure + * @rmtoll RTC_SMCR ALRADPROT LL_RTC_SetRtcSecure + * @rmtoll RTC_SMCR ALRBDPROT LL_RTC_SetRtcSecure + * @param RTCx RTC Instance + * @param rtcSecure This parameter can be a combination of the following values: + * @arg @ref LL_RTC_SECURE_FULL_YES + * @arg @ref LL_RTC_SECURE_FULL_NO + * @arg @ref LL_RTC_UNSECURE_FEATURE_INIT + * @arg @ref LL_RTC_UNSECURE_FEATURE_CAL + * @arg @ref LL_RTC_UNSECURE_FEATURE_TS + * @arg @ref LL_RTC_UNSECURE_FEATURE_WUT + * @arg @ref LL_RTC_UNSECURE_FEATURE_ALRA + * @arg @ref LL_RTC_UNSECURE_FEATURE_ALRB + + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetRtcSecure(RTC_TypeDef *RTCx, uint32_t rtcSecure) +{ + MODIFY_REG(RTCx->SMCR, RTC_SMCR_DECPROT | RTC_SMCR_INITDPROT | RTC_SMCR_CALDPROT | RTC_SMCR_TSDPROT | RTC_SMCR_WUTDPROT | RTC_SMCR_ALRADPROT | RTC_SMCR_ALRBDPROT, rtcSecure); +} +#endif /* #if defined (CORTEX_IN_SECURE_STATE) */ + +/** + * @brief Get RTC secure level. + * @note Unsecure features is relevant if LL_RTC_SECURE_FULL_NO. + * @rmtoll RTC_SMCR DECPROT LL_RTC_SetRtcSecure + * @rmtoll RTC_SMCR INITPROT LL_RTC_SetRtcSecure + * @rmtoll RTC_SMCR CALDPROT LL_RTC_SetRtcSecure + * @rmtoll RTC_SMCR TSDPROT LL_RTC_SetRtcSecure + * @rmtoll RTC_SMCR WUTDPROT LL_RTC_SetRtcSecure + * @rmtoll RTC_SMCR ALRADPROT LL_RTC_SetRtcSecure + * @rmtoll RTC_SMCR ALRBDPROT LL_RTC_SetRtcSecure + * @param RTCx RTC Instance + * @retval Combination of the following values: + * @arg @ref LL_RTC_SECURE_FULL_YES + * @arg @ref LL_RTC_SECURE_FULL_NO + * @arg @ref LL_RTC_UNSECURE_FEATURE_INIT + * @arg @ref LL_RTC_UNSECURE_FEATURE_CAL + * @arg @ref LL_RTC_UNSECURE_FEATURE_TS + * @arg @ref LL_RTC_UNSECURE_FEATURE_WUT + * @arg @ref LL_RTC_UNSECURE_FEATURE_ALRA + * @arg @ref LL_RTC_UNSECURE_FEATURE_ALRB + */ +__STATIC_INLINE uint32_t LL_RTC_GetRtcSecure(RTC_TypeDef *RTCx) +{ + return READ_BIT(RTCx->SMCR, RTC_SMCR_DECPROT | RTC_SMCR_INITDPROT | RTC_SMCR_CALDPROT | RTC_SMCR_TSDPROT | RTC_SMCR_WUTDPROT | RTC_SMCR_ALRADPROT | RTC_SMCR_ALRBDPROT); +} + +#if defined (CORTEX_IN_SECURE_STATE) +/** + * @brief Set TAMPER secure level. + * @rmtoll TAMP_SMCR TAMPDPROT LL_RTC_SetTampSecure + * @param RTCx RTC Instance + * @param tampSecure This parameter can be one of the following values: + * @arg @ref LL_TAMP_SECURE_FULL_YES + * @arg @ref LL_TAMP_SECURE_FULL_NO + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetTampSecure(RTC_TypeDef *RTCx, uint32_t tampSecure) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->SMCR, TAMP_SMCR_TAMPDPROT, tampSecure); +} +#endif /* #if defined (CORTEX_IN_SECURE_STATE) */ + +/** + * @brief Get TAMPER secure level. + * @rmtoll TAMP_SMCR TAMPDPROT LL_RTC_GetTampSecure + * @param RTCx RTC Instance + * @retval This parameter can be one of the following values: + * @arg @ref LL_TAMP_SECURE_FULL_YES + * @arg @ref LL_TAMP_SECURE_FULL_NO + */ +__STATIC_INLINE uint32_t LL_RTC_GetTampSecure(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_BIT(TAMP->SMCR, TAMP_SMCR_TAMPDPROT); +} + +/** @defgroup RTC_LL_EF_BACKUP_REG_PROTECTION PROTECTION_BACKUP_REG_Management + * @{ + */ + +/** + * @brief Set Backup registers protection level. + * @note Zone 1 : read protection write protection + * @note Zone 2 : read non-protection write protection + * @note Zone 3 : read non-protection write non-protection + * @note Warning : this parameter is only writable in secure mode or if trustzone is disabled + * @rmtoll TAMP_SMCR BKPWDPROT LL_RTC_SetBackupRegProtection + * @rmtoll TAMP_SMCR BKPRWDPROT LL_RTC_SetBackupRegProtection + * @param RTCx RTC Instance + * @param startZone2 This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * ... + * @param startZone3 This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * ... + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetBackupRegProtection(RTC_TypeDef *RTCx, uint32_t startZone2, uint32_t startZone3) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->SMCR, (TAMP_SMCR_BKPRWDPROT_Msk | TAMP_SMCR_BKPWDPROT_Msk), (startZone2 << TAMP_SMCR_BKPRWDPROT_Pos) | (startZone3 << TAMP_SMCR_BKPWDPROT_Pos)); +} + +/** + * @brief Get Backup registers protection level start zone 2. + * @note Zone 1 : read protection write protection + * @note Zone 2 : read non-protection/non-privile write protection + * @note Zone 3 : read non-protection write non-protection + * @rmtoll TAMP_SMCR BKPRWDPROT LL_RTC_GetBackupRegProtectionStartZone2 + * @param RTCx RTC Instance + * @retval Start zone 2 + */ +__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone2(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_BIT(TAMP->SMCR, TAMP_SMCR_BKPRWDPROT_Msk) >> TAMP_SMCR_BKPRWDPROT_Pos; +} + +/** + * @brief Get Backup registers protection level start zone 3. + * @note Zone 1 : read protection write protection + * @note Zone 2 : read non-protection write protection + * @note Zone 3 : read non-protection write non-protection + * @rmtoll TAMP_SMCR BKPWDPROT LL_RTC_GetBackupRegProtectionStartZone3 + * @param RTCx RTC Instance + * @retval Start zone 2 + */ +__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone3(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_BIT(TAMP->SMCR, TAMP_SMCR_BKPWDPROT_Msk) >> TAMP_SMCR_BKPWDPROT_Pos; +} +/** + * @} + */ + +/** @defgroup RTC_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSIE LL_RTC_EnableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Disable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSIE LL_RTC_DisableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Enable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTIE LL_RTC_EnableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Disable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTIE LL_RTC_DisableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Enable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBIE LL_RTC_EnableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Disable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBIE LL_RTC_DisableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Enable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAIE LL_RTC_EnableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Disable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAIE LL_RTC_DisableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Check if Time-stamp interrupt is enabled or not + * @rmtoll RTC_CR TSIE LL_RTC_IsEnabledIT_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1U : 0U); +} + +/** + * @brief Check if Wakeup timer interrupt is enabled or not + * @rmtoll RTC_CR WUTIE LL_RTC_IsEnabledIT_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1U : 0U); +} + +/** + * @brief Check if Alarm B interrupt is enabled or not + * @rmtoll RTC_CR ALRBIE LL_RTC_IsEnabledIT_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1U : 0U); +} + +/** + * @brief Check if Alarm A interrupt is enabled or not + * @rmtoll RTC_CR ALRAIE LL_RTC_IsEnabledIT_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1U : 0U); +} + +/** + * @brief Enable tamper 1 interrupt. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_EnableIT_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP1IE); +} + +/** + * @brief Disable tamper 1 interrupt. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_DisableIT_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP1IE); +} + +/** + * @brief Enable tamper 2 interrupt. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_EnableIT_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP2IE); +} + +/** + * @brief Disable tamper 2 interrupt. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_DisableIT_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP2IE); +} + +/** + * @brief Enable tamper 3 interrupt. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_EnableIT_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP3IE); +} +/** + * @brief Disable tamper 3 interrupt. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_DisableIT_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP3IE); +} + +/** + * @brief Enable internal tamper 1 interrupt. + * @rmtoll TAMP_IER ITAMP1IE LL_RTC_EnableIT_ITAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP1IE); +} + +/** + * @brief Disable internal tamper 1 interrupt. + * @rmtoll TAMP_IER ITAMP1IE LL_RTC_DisableIT_ITAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP1IE); +} + +/** + * @brief Enable internal tamper 2 interrupt. + * @rmtoll TAMP_IER ITAMP2IE LL_RTC_EnableIT_ITAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP2IE); +} + +/** + * @brief Disable internal tamper 2 interrupt. + * @rmtoll TAMP_IER ITAMP2IE LL_RTC_DisableIT_ITAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP2IE); +} + +/** + * @brief Enable internal tamper 3 interrupt. + * @rmtoll TAMP_IER ITAMP3IE LL_RTC_EnableIT_ITAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP3IE); +} +/** + * @brief Disable internal tamper 3 interrupt. + * @rmtoll TAMP_IER ITAMP3IE LL_RTC_DisableIT_ITAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP3IE); +} + +/** + * @brief Enable internal tamper 4 interrupt. + * @rmtoll TAMP_IER ITAMP4IE LL_RTC_EnableIT_ITAMP4 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP4(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP4IE); +} +/** + * @brief Disable internal tamper 4 interrupt. + * @rmtoll TAMP_IER ITAMP4IE LL_RTC_DisableIT_ITAMP4 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP4(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP4IE); +} + +/** + * @brief Enable internal tamper 5 interrupt. + * @rmtoll TAMP_IER ITAMP5IE LL_RTC_EnableIT_ITAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP5IE); +} +/** + * @brief Disable internal tamper 5 interrupt. + * @rmtoll TAMP_IER ITAMP5IE LL_RTC_DisableIT_ITAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP5IE); +} + +/** + * @brief Enable internal tamper 8 interrupt. + * @rmtoll TAMP_IER ITAMP8IE LL_RTC_EnableIT_ITAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP8IE); +} +/** + * @brief Disable internal tamper 8 interrupt. + * @rmtoll TAMP_IER TAMP8IE LL_RTC_DisableIT_ITAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP8IE); +} + +/** + * @brief Check if tamper 1 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1U : 0U); +} + +/** + * @brief Check if tamper 2 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_IsEnabledIT_TAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1U : 0U); +} + +/** + * @brief Check if tamper 3 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_IsEnabledIT_TAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1U : 0U); +} +/** + * @brief Check if tamper 4 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP4IE LL_RTC_IsEnabledIT_TAMP4 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ + +/** + * @brief Check if internal tamper 1 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP1IE LL_RTC_IsEnabledIT_ITAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP1IE) == (TAMP_IER_ITAMP1IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 2 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP2IE LL_RTC_IsEnabledIT_ITAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP2IE) == (TAMP_IER_ITAMP2IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 3 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP3IE LL_RTC_IsEnabledIT_ITAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP3IE) == (TAMP_IER_ITAMP3IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 4 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP4IE LL_RTC_IsEnabledIT_ITAMP4 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP4(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP4IE) == (TAMP_IER_ITAMP4IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 5 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP5IE LL_RTC_IsEnabledIT_ITAMP5 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP5IE) == (TAMP_IER_ITAMP5IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 8 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP8IE LL_RTC_IsEnabledIT_ITAMP8 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP8IE) == (TAMP_IER_ITAMP8IE)) ? 1U : 0U); +} + + +/** + * @brief Increment Monotonic counter. + * @rmtoll TAMP_COUNTR COUNT LL_RTC_IncrementMonotonicCounter + * @param RTCx RTC Instance + * @retval None. + */ +__STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->COUNTR, 0u); +} + +/** + * @brief Increment Monotonic counter. + * @rmtoll TAMP_COUNTR COUNT LL_RTC_GetMonotonicCounter + * @param RTCx RTC Instance + * @retval Monotonic counter value. + */ +__STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_REG(TAMP->COUNTR); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct); +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct); +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct); +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct); +ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct); +void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct); +ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32MP1xx_LL_RTC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_sdmmc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_sdmmc.h old mode 100644 new mode 100755 diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_tim.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_tim.h index 3de1f93ddc..0941b270f7 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_tim.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_tim.h @@ -238,13 +238,14 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ - uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ } LL_TIM_InitTypeDef; @@ -1763,7 +1764,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_SetRepetitionCounter * @param TIMx Timer instance - * @param RepetitionCounter between Min_Data=0 and Max_Data=255 + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. * @retval None */ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_utils.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_utils.h index 6d6120bff2..a2caec1e33 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_utils.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_utils.h @@ -226,6 +226,8 @@ typedef struct */ #define LL_UTILS_RPN_STM32MP157Cxx 0U /*!< STM32MP157Cxx Part Number */ #define LL_UTILS_RPN_STM32MP157Axx 1U /*!< STM32MP157Axx Part Number */ +#define LL_UTILS_RPN_STM32MP157Fxx 128U /*!< STM32MP157Fxx Part Number */ +#define LL_UTILS_RPN_STM32MP157Dxx 129U /*!< STM32MP157Dxx Part Number */ /** * @} @@ -300,6 +302,8 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void) * @retval Returned value can be one of the following values: * @arg @ref LL_UTILS_RPN_STM32MP157Cxx * @arg @ref LL_UTILS_RPN_STM32MP157Axx + * @arg @ref LL_UTILS_RPN_STM32MP157Fxx + * @arg @ref LL_UTILS_RPN_STM32MP157Dxx */ __STATIC_INLINE uint32_t LL_GetDevicePartNumber(void) { diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html index c27ccb2c9c..4e497c8196 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html @@ -1,210 +1,210 @@ - - - -Release Notes for STM32MP1xx HAL and LL Drivers - - - -Back to Release page -
- -
-

License

-

This software component is licensed under by ST under BSD -3-Clause -license, the "License". You may not use this package except in -compliance with -the License. You may obtain a copy of the License at:

-

https://opensource.org/licenses/BSD-3-Clause

-
-
-

Purpose

-

-
-
-
-
-

V1.1.1 / 14-November-2019

-
-
-

Main changes :

  • Patch release to fix known defects
    • HAL & LL TIM : 
      • Fix TIM Break Source definition

Supported Devices and boards

-
    -
  • STM32MP157C-EV1  revC
    • -
  • STM32MP157C-DK2  revC

    •  - -
-
-
-

-
- -
-
-

For complete -documentation on STM32 Microcontrollers, visit: www.st.com/STM32

-
-
+ + + +Release Notes for STM32MP1xx HAL and LL Drivers + + + +Back to Release page +
+ +
+

License

+

This software component is licensed under by ST under BSD +3-Clause +license, the "License". You may not use this package except in +compliance with +the License. You may obtain a copy of the License at:

+

https://opensource.org/licenses/BSD-3-Clause

+
+
+

Purpose

+

+
+
+
+
+

V1.2.0 / 03-Feb-2020

+
+
+

Main changes :

  • General updates to fix known defects and enhancements implementation
  • Major update of drivers for STM32MP15xx devices:
    • ADC:
        • Update HAL_ADC_Start_DMA() API to enable DMA mode
        • LL : new function to add or remove paths.
          • LL_ADC_SetCommonPathInternalChAdd and LL_ADC_SetCommonPathInternalChAdd : New API
    • CORTEX:
      • Implement LL Driver
    • FMC:
      • Implement PSRAM Driver: New API
    • GENERIC:
      • Add EXTERNAL_CLOCK_VALUE in conf_template file.
    • RTC:
      • HAL&LL : Implement RTC Driver (including TAMP) : New API
    • TIM:
        • HAL&LL: Remove reference to COMP1 and COMP2
        • LL: 
          • Fix TIM Break source definition
          • RepetitionCounter value depends on GP or Advanced tmers
    • UART:
      • HAL: Alignment with  STM32F0/F3/H7 (for inter STM32 families portability)
        • some API's change to take in consideration
    • UTILS:
      • LL: Add new Part Number defines related to LL_GetDevicePartNumber()

Supported Devices and boards

+
    +
  • STM32MP157C-EV1  revC
    • +
  • STM32MP157C-DK2  revC

    •  + +
+
+
+

+
+ +
+
+

For complete +documentation on STM32 Microcontrollers, visit: www.st.com/STM32

+
+
\ No newline at end of file diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c index ffc4849702..ca4d5801a1 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c @@ -54,7 +54,7 @@ * @brief STM32MP1xx HAL Driver version number */ #define __STM32MP1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32MP1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32MP1xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ #define __STM32MP1xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32MP1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32MP1xx_HAL_VERSION ((__STM32MP1xx_HAL_VERSION_MAIN << 24)\ @@ -868,10 +868,17 @@ void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG */ void HAL_SYSCFG_DisableIOCompensation(void) { + uint32_t pmos_val = 0; + uint32_t nmos_val = 0; + + /* Get I/O compensation cell values for PMOS and NMOS transistors */ + pmos_val = __HAL_SYSCFG_GET_PMOS_CMP(); + nmos_val = __HAL_SYSCFG_GET_NMOS_CMP(); + /* Copy actual value of SYSCFG_CMPCR.APSRC[3:0]/ANSRC[3:0] in * SYSCFG_CMPCR.RAPSRC[3:0]/RANSRC[3:0] */ - HAL_SYSCFG_CompensationCodeConfig(__HAL_SYSCFG_GET_PMOS_CMP(), __HAL_SYSCFG_GET_NMOS_CMP()); + HAL_SYSCFG_CompensationCodeConfig(pmos_val, nmos_val); /* Set SYSCFG_CMPCR.SW_CTRL = 1 */ HAL_SYSCFG_CompensationCodeSelect(SYSCFG_REGISTER_CODE); diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c index 1d911e6d58..e3630ff9ee 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c @@ -2087,6 +2087,8 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + /* Enable ADC DMA mode*/ + LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement); /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c index 666ab69305..c3eb2920ae 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c @@ -223,19 +223,32 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t Single HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t* LinearCalib_Buffer) { uint32_t cnt; - HAL_StatusTypeDef tmp_hal_status; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t temp_REG_IsConversionOngoing = 0UL; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */ - tmp_hal_status = ADC_Enable(hadc); + if(LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + tmp_hal_status = ADC_Enable(hadc); + } if (tmp_hal_status == HAL_OK) { - for(cnt = 0UL; cnt < ADC_LINEAR_CALIB_REG_COUNT; cnt++) + if(LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) { - LinearCalib_Buffer[cnt]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> cnt); + LL_ADC_REG_StopConversion(hadc->Instance); + temp_REG_IsConversionOngoing = 1UL; + } + for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL; cnt--) + { + LinearCalib_Buffer[cnt-1U]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt)); + } + if(temp_REG_IsConversionOngoing != 0UL) + { + LL_ADC_REG_StartConversion(hadc->Instance); } } diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_qspi.c old mode 100644 new mode 100755 diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rtc.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rtc.c new file mode 100644 index 0000000000..5348639dd9 --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rtc.c @@ -0,0 +1,1773 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_hal_rtc.c + * @author MCD Application Team + * @brief RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral: + * + Initialization/de-initialization functions + * + Calendar (Time and Date) configuration + * + Alarms (Alarm A and Alarm B) configuration + * + WakeUp Timer configuration + * + TimeStamp configuration + * + Tampers configuration + * + Backup Data Registers configuration + * + RTC Tamper and TimeStamp Pins Selection + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### RTC Operating Condition ##### + =============================================================================== + [..] The real-time clock (RTC) and the RTC backup registers can be powered + from the VBAT voltage when the main VDD supply is powered off. + To retain the content of the RTC backup registers and supply the RTC + when VDD is turned off, VBAT pin can be connected to an optional + standby voltage supplied by a battery or by another source. + + ##### Backup Domain Reset ##### + =============================================================================== + [..] The backup domain reset sets all RTC registers and the RCC_BDCR register + to their reset values. + A backup domain reset is generated when one of the following events occurs: + (#) Software reset, triggered by setting the BDRST bit in the + RCC Backup domain control register (RCC_BDCR). + (#) VDD or VBAT power on, if both supplies have previously been powered off. + (#) Tamper detection event resets all data backup registers. + + ##### Backup Domain Access ##### + ================================================================== + [..] After reset, the backup domain (RTC registers and RTC backup data registers) + is protected against possible unwanted write accesses. + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() function. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. + (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. + + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for + PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32) + (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro. + + ##### How to use RTC Driver ##### + =================================================================== + [..] + (+) Enable the RTC domain access (see description in the section above). + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the HAL_RTC_Init() function. + + *** Time and Date configuration *** + =================================== + [..] + (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() + and HAL_RTC_SetDate() functions. + (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. + + *** Alarm configuration *** + =========================== + [..] + (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. + You can also configure the RTC Alarm with interrupt mode using the + HAL_RTC_SetAlarm_IT() function. + (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. + + ##### RTC and low power modes ##### + ================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate + function. + [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), + RTC wakeup, RTC tamper event detection and RTC time stamp event detection. + These RTC alternate functions can wake up the system from the Stop and + Standby low power modes. + [..] The system can also wake up from low power modes without depending + on an external interrupt (Auto-wakeup mode), by using the RTC alarm + or the RTC wakeup events. + [..] The RTC provides a programmable time base for waking up from the + Stop or Standby mode at regular intervals. + Wakeup from STOP and STANDBY modes is possible only when the RTC clock source + is LSE or LSI. + + *** Callback registration *** + ============================================= + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. This is the recommended configuration + in order to optimize memory/code consumption footprint/performances. + + The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback. + + Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) InternalTamper1EventCallback : RTC InternalTamper 1 Event callback. + (+) InternalTamper2EventCallback : RTC InternalTamper 2 Event callback. + (+) InternalTamper3EventCallback : RTC InternalTamper 3 Event callback. + (+) InternalTamper4EventCallback : RTC InternalTamper 4 Event callback. + (+) InternalTamper5EventCallback : RTC InternalTamper 5 Event callback. + (+) InternalTamper8EventCallback : RTC InternalTamper 8 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) InternalTamper1EventCallback : RTC Internal Tamper 1 Event callback. + (+) InternalTamper2EventCallback : RTC Internal Tamper 2 Event callback. + (+) InternalTamper3EventCallback : RTC Internal Tamper 3 Event callback. + (+) InternalTamper4EventCallback : RTC Internal Tamper 4 Event callback. + (+) InternalTamper5EventCallback : RTC Internal Tamper 5 Event callback. + (+) InternalTamper8EventCallback : RTC Internal Tamper 8 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + + By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, + all callbacks are set to the corresponding weak functions : + examples @ref AlarmAEventCallback(), @ref TimeStampEventCallback(). + Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function + in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null + (not registered beforehand). + If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit() + or @ref HAL_RTC_Init() function. + + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_hal.h" + +/** @addtogroup STM32MP1xx_HAL_Driver + * @{ + */ + + +/** @addtogroup RTC + * @brief RTC HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RTC_Exported_Functions + * @{ + */ + +/** @addtogroup RTC_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + RTC registers Write protection, enter and exit the RTC initialization mode, + RTC registers synchronization check and reference clock detection enable. + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize power consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WPR. + (#) To configure the RTC Calendar, user application should enter + initialization mode. In this mode, the calendar counter is stopped + and its value can be updated. When the initialization sequence is + complete, the calendar restarts counting after 4 RTCCLK cycles. + (#) To read the calendar through the shadow registers after Calendar + initialization, calendar update or after wakeup from low power modes + the software must first clear the RSF flag. The software must then + wait until it is set again before reading the calendar, which means + that the calendar registers have been correctly copied into the + RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function + implements the above software sequence (RSF clear and RSF check). + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the RTC peripheral + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the RTC peripheral state */ + if (hrtc != NULL) + { + /* Check the parameters */ + assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); + assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); + assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap)); + assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); + assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); + assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp)); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ + hrtc->InternalTamper1EventCallback = HAL_RTCEx_InternalTamper1EventCallback; /* Legacy weak InternalTamper1EventCallback */ + hrtc->InternalTamper2EventCallback = HAL_RTCEx_InternalTamper2EventCallback; /* Legacy weak InternalTamper2EventCallback */ + hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; /* Legacy weak InternalTamper3EventCallback */ + hrtc->InternalTamper4EventCallback = HAL_RTCEx_InternalTamper4EventCallback; /* Legacy weak InternalTamper3EventCallback */ + hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback; /* Legacy weak InternalTamper5EventCallback */ + hrtc->InternalTamper8EventCallback = HAL_RTCEx_InternalTamper8EventCallback; /* Legacy weak InternalTamper8EventCallback */ + + if (hrtc->MspInitCallback == NULL) + { + hrtc->MspInitCallback = HAL_RTC_MspInit; + } + /* Init the low level hardware */ + hrtc->MspInitCallback(hrtc); + + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else + if (hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + } +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + /* Set RTC_CR register */ + SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); + + /* Configure the RTC PRER */ + WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + if (status == HAL_OK) + { + MODIFY_REG(RTC->CR, \ + RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } + } + + return status; +} + +/** + * @brief DeInitialize the RTC peripheral. + * @note This function does not reset the RTC Backup Data registers. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status; + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Reset all RTC CR register bits */ + CLEAR_REG(RTC->CR); + WRITE_REG(RTC->DR, (uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + CLEAR_REG(RTC->TR); + WRITE_REG(RTC->WUTR, RTC_WUTR_WUT); + WRITE_REG(RTC->PRER, ((uint32_t)(RTC_PRER_PREDIV_A | 0xFFU))); + CLEAR_REG(RTC->ALRMAR); + CLEAR_REG(RTC->ALRMBR); + CLEAR_REG(RTC->SHIFTR); + CLEAR_REG(RTC->CALR); + CLEAR_REG(RTC->ALRMASSR); + CLEAR_REG(RTC->ALRMBSSR); + WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSOVF | RTC_SCR_CTSF | RTC_SCR_CWUTF | RTC_SCR_CALRBF | RTC_SCR_CALRAF); +#if defined (CORTEX_IN_SECURE_STATE) + WRITE_REG(RTC->SMCR, (RTC_SMCR_DECPROT | RTC_SMCR_INITDPROT | RTC_SMCR_CALDPROT | RTC_SMCR_TSDPROT | RTC_SMCR_WUTDPROT | RTC_SMCR_ALRBDPROT | RTC_SMCR_ALRADPROT)); +#endif + + /* Exit initialization mode */ + status = RTC_ExitInitMode(hrtc); + if (status == HAL_OK) + { + /* Reset TAMP registers */ + WRITE_REG(TAMP->CR1, RTC_INT_TAMPER_ALL); + CLEAR_REG(TAMP->CR2); + CLEAR_REG(TAMP->FLTCR); + WRITE_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL); + CLEAR_REG(TAMP->ATOR); +#if defined (CORTEX_IN_SECURE_STATE) + WRITE_REG(TAMP->SMCR, TAMP_SMCR_TAMPDPROT); +#endif + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hrtc->MspDeInitCallback(hrtc); + +#else + /* De-Initialize RTC MSP */ + HAL_RTC_MspDeInit(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + hrtc->State = HAL_RTC_STATE_RESET; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User RTC Callback + * To be used instead of the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_TAMPER4_EVENT_CB_ID Tamper 4 Callback ID + * @arg @ref HAL_RTC_TAMPER5_EVENT_CB_ID Tamper 5 Callback ID + * @arg @ref HAL_RTC_TAMPER6_EVENT_CB_ID Tamper 6 Callback ID + * @arg @ref HAL_RTC_TAMPER7_EVENT_CB_ID Tamper 7 Callback ID + * @arg @ref HAL_RTC_TAMPER8_EVENT_CB_ID Tamper 8 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hrtc); + + if (HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = pCallback; + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = pCallback; + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = pCallback; + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = pCallback; + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER3_EVENT_CB_ID : + hrtc->Tamper3EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID : + hrtc->InternalTamper1EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID : + hrtc->InternalTamper2EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : + hrtc->InternalTamper3EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : + hrtc->InternalTamper5EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID : + hrtc->InternalTamper8EventCallback = pCallback; + break; + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Unregister an RTC Callback + * RTC callback is redirected to the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_TAMPER4_EVENT_CB_ID Tamper 4 Callback ID + * @arg @ref HAL_RTC_TAMPER5_EVENT_CB_ID Tamper 5 Callback ID + * @arg @ref HAL_RTC_TAMPER6_EVENT_CB_ID Tamper 6 Callback ID + * @arg @ref HAL_RTC_TAMPER7_EVENT_CB_ID Tamper 7 Callback ID + * @arg @ref HAL_RTC_TAMPER8_EVENT_CB_ID Tamper 8 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID Internal Tamper 1 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID Internal Tamper 2 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hrtc); + + if (HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + break; + + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ + break; + + case HAL_RTC_TAMPER3_EVENT_CB_ID : + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ + break; + + case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID : + hrtc->InternalTamper1EventCallback = HAL_RTCEx_InternalTamper1EventCallback; /* Legacy weak InternalTamper1EventCallback */ + break; + + case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID : + hrtc->InternalTamper2EventCallback = HAL_RTCEx_InternalTamper2EventCallback; /* Legacy weak InternalTamper2EventCallback */ + break; + + case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : + hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; /* Legacy weak InternalTamper3EventCallback */ + break; + + case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : + hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback; /* Legacy weak InternalTamper5EventCallback */ + break; + + case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID : + hrtc->InternalTamper8EventCallback = HAL_RTCEx_InternalTamper8EventCallback; /* Legacy weak InternalTamper8EventCallback */ + break; + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @brief Initialize the RTC MSP. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the RTC MSP. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group2 + * @brief RTC Time and Date functions + * +@verbatim + =============================================================================== + ##### RTC Time and Date functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Time and Date features + +@endverbatim + * @{ + */ + +/** + * @brief Set RTC current time. + * @param hrtc RTC handle + * @param sTime Pointer to Time structure + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t tmpreg; + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + if (Format == RTC_FORMAT_BIN) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(sTime->Hours)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sTime->Hours)); + } + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Seconds) << RTC_TR_SU_Pos) | \ + (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos)); + } + else + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t)(sTime->Seconds) << RTC_TR_SU_Pos) | \ + ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos)); + } + + /* Set the RTC_TR register */ + WRITE_REG(RTC->TR, (tmpreg & RTC_TR_RESERVED_MASK)); + + /* Clear the bits to be configured */ + CLEAR_BIT(RTC->CR, RTC_CR_BKP); + + /* Configure the RTC_CR register */ + SET_BIT(RTC->CR, (sTime->DayLightSaving | sTime->StoreOperation)); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Get RTC current time. + * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds + * value in second fraction ratio with time unit following generic formula: + * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * in the higher-order calendar shadow registers to ensure consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers until Current date is read + * to ensure consistency between the time and date values. + * @param hrtc RTC handle + * @param sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned + * with input format (BIN or BCD), also SubSeconds field returning the + * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler + * factor to be used for second fraction ratio computation. + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t tmpreg; + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get subseconds structure field from the corresponding register*/ + sTime->SubSeconds = READ_REG(RTC->SSR); + + /* Get SecondFraction structure field from the corresponding register field*/ + sTime->SecondFraction = (uint32_t)(READ_REG(RTC->PRER) & RTC_PRER_PREDIV_S); + + /* Get the TR register */ + tmpreg = (uint32_t)(READ_REG(RTC->TR) & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos); + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); + sTime->Seconds = (uint8_t)((tmpreg & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos); + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + { + /* Convert the time structure parameters to Binary format */ + sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); + sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); + sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); + } + + return HAL_OK; +} + +/** + * @brief Set RTC current date. + * @param hrtc RTC handle + * @param sDate Pointer to date structure + * @param Format specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t datetmpreg; + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) + { + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); + } + + assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); + + if (Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_YEAR(sDate->Year)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); + + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Date) << RTC_DR_DU_Pos) | \ + ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); + + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + (((uint32_t)sDate->Date) << RTC_DR_DU_Pos) | \ + (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos)); + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Set the RTC_DR register */ + WRITE_REG(RTC->DR, (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK)); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Get RTC current date. + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * in the higher-order calendar shadow registers to ensure consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers until Current date is read. + * @param hrtc RTC handle + * @param sDate Pointer to Date structure + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t datetmpreg; + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the DR register */ + datetmpreg = (uint32_t)(READ_REG(RTC->DR) & RTC_DR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos); + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos); + sDate->Date = (uint8_t)((datetmpreg & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos); + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos); + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + { + /* Convert the date structure parameters to Binary format */ + sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); + sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); + sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); + } + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group3 + * @brief RTC Alarm functions + * +@verbatim + =============================================================================== + ##### RTC Alarm functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Alarm feature + +@endverbatim + * @{ + */ +/** + * @brief Set the specified RTC Alarm. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t tmpreg, subsecondtmpreg; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if (Format == RTC_FORMAT_BIN) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + else /* format BCD */ + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + +#ifdef USE_FULL_ASSERT + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + +#endif /* USE_FULL_ASSERT */ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + + /* Configure the Alarm A or Alarm B Sub Second registers */ + subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Alarm register */ + if (sAlarm->Alarm == RTC_ALARM_A) + { + /* Disable the Alarm A interrupt */ + /* In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + /* Clear flag alarm A */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + /* Configure the Alarm A */ + WRITE_REG(RTC->ALRMAR, (uint32_t)tmpreg); + /* Configure the Alarm A Sub Second register */ + WRITE_REG(RTC->ALRMASSR, subsecondtmpreg); + /* Configure the Alarm state: Enable Alarm */ + SET_BIT(RTC->CR, RTC_CR_ALRAE); + } + else + { + /* Disable the Alarm B interrupt */ + /* In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + /* Clear flag alarm B */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + /* Configure the Alarm A */ + WRITE_REG(RTC->ALRMBR, tmpreg); + /* Configure the Alarm B Sub Second register */ + WRITE_REG(RTC->ALRMBSSR, subsecondtmpreg); + /* Configure the Alarm state: Enable Alarm */ + SET_BIT(RTC->CR, RTC_CR_ALRBE); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Set the specified RTC Alarm with Interrupt. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the HAL_RTC_DeactivateAlarm()). + * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t tmpreg, subsecondtmpreg; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if (Format == RTC_FORMAT_BIN) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + else /* Format BCD */ + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + +#ifdef USE_FULL_ASSERT + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + +#endif /* USE_FULL_ASSERT */ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + /* Configure the Alarm A or Alarm B Sub Second registers */ + subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Alarm register */ + if (sAlarm->Alarm == RTC_ALARM_A) + { + /* Disable the Alarm A interrupt */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE); + /* Clear flag alarm A */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + /* Configure the Alarm A */ + WRITE_REG(RTC->ALRMAR, (uint32_t)tmpreg); + /* Configure the Alarm A Sub Second register */ + WRITE_REG(RTC->ALRMASSR, subsecondtmpreg); + /* Configure the Alarm interrupt : Enable Alarm */ + SET_BIT(RTC->CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + } + else + { + /* Disable the Alarm B interrupt */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBIE); + /* Clear flag alarm B */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + /* Configure the Alarm B */ + WRITE_REG(RTC->ALRMBR, (uint32_t)tmpreg); + /* Configure the Alarm B Sub Second register */ + WRITE_REG(RTC->ALRMBSSR, subsecondtmpreg); + /* Configure the Alarm B interrupt : Enable Alarm */ + SET_BIT(RTC->CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + } + + /* RTC Alarm Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate the specified RTC Alarm. + * @param hrtc RTC handle + * @param Alarm Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALARM(Alarm)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + if (Alarm == RTC_ALARM_A) + { + CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + } + else + { + CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Get the RTC Alarm value and masks. + * @param hrtc RTC handle + * @param sAlarm Pointer to Date structure + * @param Alarm Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) +{ + uint32_t tmpreg, subsecondtmpreg; + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(Alarm)); + + if (Alarm == RTC_ALARM_A) + { + /* AlarmA */ + sAlarm->Alarm = RTC_ALARM_A; + + tmpreg = READ_REG(RTC->ALRMAR); + subsecondtmpreg = (uint32_t)(READ_REG(RTC->ALRMASSR) & RTC_ALRMASSR_SS); + + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)) >> RTC_ALRMAR_SU_Pos); + sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> RTC_ALRMAR_PM_Pos); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + } + else + { + sAlarm->Alarm = RTC_ALARM_B; + + tmpreg = READ_REG(RTC->ALRMBR); + subsecondtmpreg = (uint32_t)(READ_REG(RTC->ALRMBSSR) & RTC_ALRMBSSR_SS); + + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> RTC_ALRMBR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> RTC_ALRMBR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)) >> RTC_ALRMBR_SU_Pos); + sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMBR_PM) >> RTC_ALRMBR_PM_Pos); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> RTC_ALRMBR_DU_Pos); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + } + + if (Format == RTC_FORMAT_BIN) + { + sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); + sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); + sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + } + + return HAL_OK; +} + +#if defined (CORTEX_IN_SECURE_STATE) +/** + * @brief Handle Alarm secure interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get interrupt status */ + uint32_t tmp = READ_REG(RTC->SMISR); + + if ((tmp & RTC_SMISR_ALRAMF) != 0u) + { + /* Clear the AlarmA interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmAEventCallback(hrtc); +#else + HAL_RTC_AlarmAEventCallback(hrtc); +#endif + } + + if ((tmp & RTC_SMISR_ALRBMF) != 0u) + { + /* Clear the AlarmB interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmBEventCallback(hrtc); +#else + HAL_RTCEx_AlarmBEventCallback(hrtc); +#endif + + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +#else /* #if defined (CORTEX_IN_SECURE_STATE) */ + +/** + * @brief Handle Alarm non-secure interrupt request. + * @note Alarm non-secure is available in non-secure driver. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get interrupt status */ + uint32_t tmp = READ_REG(RTC->MISR); + + if ((tmp & RTC_MISR_ALRAMF) != 0U) + { + /* Clear the AlarmA interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmAEventCallback(hrtc); +#else + HAL_RTC_AlarmAEventCallback(hrtc); +#endif + } + + if ((tmp & RTC_MISR_ALRBMF) != 0U) + { + /* Clear the AlarmB interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmBEventCallback(hrtc); +#else + HAL_RTCEx_AlarmBEventCallback(hrtc); +#endif + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} +#endif /* #if defined (CORTEX_IN_SECURE_STATE) */ + +/** + * @brief Alarm A secure secure callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the secure secure callback is needed, + the HAL_RTC_AlarmAEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle AlarmA Polling request. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Alarm interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group4 + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Wait for RTC Time and Date Synchronization + +@endverbatim + * @{ + */ + +/** + * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart; + + UNUSED(hrtc); + /* Clear RSF flag */ + SET_BIT(RTC->ICSR, RTC_RSF_MASK); + + tickstart = HAL_GetTick(); + + /* Wait the registers to be synchronised */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group5 + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Get RTC state + +@endverbatim + * @{ + */ +/** + * @brief Return the RTC handle state. + * @param hrtc RTC handle + * @retval HAL state + */ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) +{ + /* Return RTC handle state */ + return hrtc->State; +} + +/** + * @} + */ +/** + * @} + */ + +/** @addtogroup RTC_Private_Functions + * @{ + */ +/** + * @brief Enter the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + UNUSED(hrtc); + /* Check if the Initialization mode is set */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + /* Set the Initialization mode */ + SET_BIT(RTC->ICSR, RTC_ICSR_INIT); + + tickstart = HAL_GetTick(); + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + status = HAL_TIMEOUT; + hrtc->State = HAL_RTC_STATE_TIMEOUT; + } + } + } + + return status; +} + +/** + * @brief Exit the RTC Initialization mode. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Exit Initialization mode */ + CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT); + + /* If CR_BYPSHAD bit = 0, wait for synchro */ + if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; + } + } + else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry. + Please look at Errata sheet on the internet for details. */ + { + /* Clear BYPSHAD bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; + } + /* Restore BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + } + + return status; +} + +/** + * @brief Convert a 2 digit decimal to BCD format. + * @param Value Byte to be converted + * @retval Converted byte + */ +uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint32_t bcdhigh = 0U; + uint8_t tmp_Value = Value; + + while (tmp_Value >= 10U) + { + bcdhigh++; + tmp_Value -= 10U; + } + + return ((uint8_t)(bcdhigh << 4U) | tmp_Value); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value BCD value to be converted + * @retval Converted word + */ +uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint32_t tmp; + tmp = (((uint32_t)Value & 0xF0U) >> 4) * 10U; + return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU)); +} + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rtc_ex.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rtc_ex.c new file mode 100644 index 0000000000..940fa3fdf9 --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rtc_ex.c @@ -0,0 +1,2472 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_hal_rtc_ex.c + * @author MCD Application Team + * @brief Extended RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real Time Clock (RTC) Extended peripheral: + * + RTC Time Stamp functions + * + RTC Tamper functions + * + RTC Wake-up functions + * + Extended Control functions + * + Extended RTC features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) Enable the RTC domain access. + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the HAL_RTC_Init() function. + + *** RTC Wakeup configuration *** + ================================ + [..] + (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() + function. You can also configure the RTC Wakeup timer with interrupt mode + using the HAL_RTCEx_SetWakeUpTimer_IT() function. + (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() + function. + + *** Outputs configuration *** + ============================= + [..] The RTC has 2 different outputs: + (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B + and WaKeUp signals. + To output the selected RTC signal, use the HAL_RTC_Init() function. + (+) RTC_CALIB: this output is 512Hz signal or 1Hz. + To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function. + (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on + the RTC_OR register. + (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is + automatically configured in output alternate function. + + *** Smooth digital Calibration configuration *** + ================================================ + [..] + (+) Configure the RTC Original Digital Calibration Value and the corresponding + calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib() + function. + + *** TimeStamp configuration *** + =============================== + [..] + (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function. + You can also configure the RTC TimeStamp with interrupt mode using the + HAL_RTCEx_SetTimeStamp_IT() function. + (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() + function. + + *** Internal TimeStamp configuration *** + =============================== + [..] + (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function. + User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG. + (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() + function. + + *** Tamper configuration *** + ============================ + [..] + (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, NoErase, MaskFlag, precharge or discharge and + Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper + with interrupt mode using HAL_RTCEx_SetTamper_IT() function. + (+) The default configuration of the Tamper erases the backup registers. To avoid + erase, enable the NoErase field on the RTC_TAMPCR register. + (+) With new RTC tamper configuration, you have to call HAL_RTC_Init() in order to + perform TAMP base address offset calculation. + (+) If you do not intend to have tamper using RTC clock, you can bypass its initialization + by setting ClockEnable inti field to RTC_CLOCK_DISABLE. + (+) Enable Internal tamper using HAL_RTCEx_SetInternalTamper. IT mode can be chosen using + setting Interrupt field. + + *** Backup Data Registers configuration *** + =========================================== + [..] + (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() + function. + (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() + function. + (+) Before calling these functions you have to call HAL_RTC_Init() in order to + perform TAMP base address offset calculation. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_hal.h" + +/** @addtogroup STM32MP1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RTCEx + * @brief RTC Extended HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E) + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RTCEx_Exported_Functions + * @{ + */ + + +/** @addtogroup RTCEx_Exported_Functions_Group1 + * @brief RTC TimeStamp and Tamper functions + * +@verbatim + =============================================================================== + ##### RTC TimeStamp and Tamper functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure TimeStamp feature + +@endverbatim + * @{ + */ + +/** + * @brief Set TimeStamp. + * @note This API must be called before enabling the TimeStamp feature. + * @param hrtc RTC handle + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * falling edge of the related pin. + * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. + * The RTC TimeStamp Pin is per default PC13, but for reasons of + * compatibility, this parameter is required. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +{ + /* Check the parameters */ + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + UNUSED(RTC_TimeStampPin); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Get the RTC_CR register and clear the bits to be configured */ + CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE)); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Time Stamp TSEDGE and Enable bits */ + SET_BIT(RTC->CR, (uint32_t)TimeStampEdge | RTC_CR_TSE); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Set TimeStamp with Interrupt. + * @note This API must be called before enabling the TimeStamp feature. + * @param hrtc RTC handle + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * falling edge of the related pin. + * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. + * The RTC TimeStamp Pin is per default PC13, but for reasons of + * compatibility, this parameter is required. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +{ + /* Check the parameters */ + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + UNUSED(RTC_TimeStampPin); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* RTC timestamp Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT(); + + /* Get the RTC_CR register and clear the bits to be configured */ + CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE)); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Time Stamp TSEDGE before Enable bit to avoid unwanted TSF setting. */ + SET_BIT(RTC->CR, (uint32_t)TimeStampEdge); + + /* Enable timestamp and IT */ + SET_BIT(RTC->CR, RTC_CR_TSE | RTC_CR_TSIE); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate TimeStamp. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE)); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Set Internal TimeStamp. + * @note This API must be called before enabling the internal TimeStamp feature. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the internal Time Stamp Enable bits */ + SET_BIT(RTC->CR, RTC_CR_ITSE); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate Internal TimeStamp. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the internal Time Stamp Enable bits */ + CLEAR_BIT(RTC->CR, RTC_CR_ITSE); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Get the RTC TimeStamp value. + * @param hrtc RTC handle + * @param sTimeStamp Pointer to Time structure + * @param sTimeStampDate Pointer to Date structure + * @param Format specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format) +{ + uint32_t tmptime, tmpdate; + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = READ_BIT(RTC->TSTR, RTC_TR_RESERVED_MASK); + tmpdate = READ_BIT(RTC->TSDR, RTC_DR_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> RTC_TSTR_HU_Pos); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos); + sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)) >> RTC_TSTR_SU_Pos); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> RTC_TSTR_PM_Pos); + sTimeStamp->SubSeconds = READ_BIT(RTC->TSSSR, RTC_TSSSR_SS); + + /* Fill the Date structure fields with the read parameters */ + sTimeStampDate->Year = 0U; + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos); + sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU)); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> RTC_TSDR_WDU_Pos); + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + { + /* Convert the TimeStamp structure parameters to Binary format */ + sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); + sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); + sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); + + /* Convert the DateTimeStamp structure parameters to Binary format */ + sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); + sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); + sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); + } + + /* Clear the TIMESTAMP Flags */ + WRITE_REG(RTC->SCR, (RTC_SCR_CITSF | RTC_SCR_CTSF)); + + return HAL_OK; +} + +#if defined (CORTEX_IN_SECURE_STATE) +/** + * @brief Handle TimeStamp secure interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if (READ_BIT(RTC->SMISR, RTC_SMISR_TSMF) != 0U) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call TimeStampEvent registered Callback */ + hrtc->TimeStampEventCallback(hrtc); +#else + HAL_RTCEx_TimeStampEventCallback(hrtc); +#endif + /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when TSF bit is reset.*/ + WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSF); + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +#else /* #if defined (CORTEX_IN_SECURE_STATE) */ + +/** + * @brief Handle TimeStamp non-secure interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if (READ_BIT(RTC->MISR, RTC_MISR_TSMF) != 0U) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call TimeStampEvent registered Callback */ + hrtc->TimeStampEventCallback(hrtc); +#else + HAL_RTCEx_TimeStampEventCallback(hrtc); +#endif + /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when TSF bit is reset.*/ + WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSF); + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} +#endif /* #if defined (CORTEX_IN_SECURE_STATE) */ + +/** + * @brief TimeStamp callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle TimeStamp polling request. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U) + { + if (READ_BIT(RTC->SR, RTC_SR_TSOVF) != 0U) + { + /* Clear the TIMESTAMP OverRun Flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF); + + /* Change TIMESTAMP state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group2 + * @brief RTC Wake-up functions + * +@verbatim + =============================================================================== + ##### RTC Wake-up functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Wake-up feature + +@endverbatim + * @{ + */ + +/** + * @brief Set wake up timer. + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Clear WUTE in RTC_CR to disable the wakeup timer */ + CLEAR_BIT(RTC->CR, RTC_CR_WUTE); + + /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload + counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in + calendar initialization mode. */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + tickstart = HAL_GetTick(); + while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + + /* Configure the clock source */ + MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock); + + /* Configure the Wakeup Timer counter */ + WRITE_REG(RTC->WUTR, (uint32_t)WakeUpCounter); + + /* Enable the Wakeup Timer */ + SET_BIT(RTC->CR, RTC_CR_WUTE); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Set wake up timer with interrupt. + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock + * @param WakeUpAutoClr Wake up auto clear value (look at WUTOCLR in reference manual) + * - No effect if WakeUpAutoClr is set to zero + * - This feature is meaningful in case of Low power mode to avoid any RTC software execution after Wake Up. + * That is why when WakeUpAutoClr is set, EXTI is configured as EVENT instead of Interrupt to avoid useless IRQ handler execution. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, uint32_t WakeUpAutoClr) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + /* (0x0000<=WUTOCLR<=WUT) */ + assert_param(WakeUpAutoClr <= WakeUpCounter); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Clear WUTE in RTC_CR to disable the wakeup timer */ + CLEAR_BIT(RTC->CR, RTC_CR_WUTE); + + /* Clear flag Wake-Up */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); + + /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload + counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in + calendar initialization mode. */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + tickstart = HAL_GetTick(); + while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + + /* Configure the Wakeup Timer counter and auto clear value */ + WRITE_REG(RTC->WUTR, (uint32_t)(WakeUpCounter)); + + /* Configure the clock source */ + MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock); + + /* In case of WUT autoclr, the IRQ handler should not be called */ + if (WakeUpAutoClr != 0U) + { + /* RTC WakeUpTimer EXTI Configuration: Event configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT(); + } + else + { + /* RTC WakeUpTimer EXTI Configuration: Interrupt configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); + } + + /* Configure the Interrupt in the RTC_CR register and Enable the Wakeup Timer*/ + SET_BIT(RTC->CR, (RTC_CR_WUTIE | RTC_CR_WUTE)); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate wake up timer counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Disable the Wakeup Timer */ + /* In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, (RTC_CR_WUTE | RTC_CR_WUTIE)); + + tickstart = HAL_GetTick(); + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Get wake up timer counter. + * @param hrtc RTC handle + * @retval Counter value + */ +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + /* Get the counter value */ + return (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT)); +} + +#if defined (CORTEX_IN_SECURE_STATE) +/** + * @brief Handle Wake Up Timer secure interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if ((RTC->SMISR & RTC_SMISR_WUTMF) != 0u) + { + /* Immediatly clear flags */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call wake up timer registered Callback */ + hrtc->WakeUpTimerEventCallback(hrtc); +#else + HAL_RTCEx_WakeUpTimerEventCallback(hrtc); +#endif + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +#else /* #if defined (CORTEX_IN_SECURE_STATE) */ + +/** + * @brief Handle Wake Up Timer non-secure interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get the pending status of the WAKEUPTIMER Interrupt */ + if (READ_BIT(RTC->MISR, RTC_MISR_WUTMF) != 0U) + { + /* Clear the WAKEUPTIMER interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call WakeUpTimerEvent registered Callback */ + hrtc->WakeUpTimerEventCallback(hrtc); +#else + /* WAKEUPTIMER callback */ + HAL_RTCEx_WakeUpTimerEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} +#endif /* #if defined (CORTEX_IN_SECURE_STATE) */ + +/** + * @brief Wake Up Timer callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle Wake Up Timer Polling. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the WAKEUPTIMER Flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group3 + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Write a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register + (+) Set the Coarse calibration parameters. + (+) Deactivate the Coarse calibration parameters + (+) Set the Smooth calibration parameters. + (+) Set Low Power calibration parameter. + (+) Configure the Synchronization Shift Control Settings. + (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Enable the RTC reference clock detection. + (+) Disable the RTC reference clock detection. + (+) Enable the Bypass Shadow feature. + (+) Disable the Bypass Shadow feature. + +@endverbatim + * @{ + */ + +/** + * @brief Set the Smooth calibration parameters. + * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses + * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field + * SmoothCalibMinusPulsesValue must be equal to 0. + * @param hrtc RTC handle + * @param SmoothCalibPeriod Select the Smooth Calibration Period. + * This parameter can be can be one of the following values : + * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. + * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. + * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. + * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. + * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. + * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* check if a calibration is pending*/ + if (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) + { + tickstart = HAL_GetTick(); + + /* check if a calibration is pending*/ + while (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + + /* Configure the Smooth calibration settings */ + MODIFY_REG(RTC->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM), (uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue)); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Configure the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @param hrtc RTC handle + * @param ShiftAdd1S Select to add or not 1 second to the time calendar. + * This parameter can be one of the following values: + * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. + * @arg RTC_SHIFTADD1S_RESET: No effect. + * @param ShiftSubFS Select the number of Second Fractions to substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + tickstart = HAL_GetTick(); + + /* Wait until the shift is completed*/ + while (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Check if the reference clock detection is disabled */ + if (READ_BIT(RTC->CR, RTC_CR_REFCKON) == 0U) + { + /* Configure the Shift settings */ + MODIFY_REG(RTC->SHIFTR, RTC_SHIFTR_SUBFS, (uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S)); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + } + else + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc RTC handle + * @param CalibOutput Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. + * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the RTC_CR register */ + MODIFY_REG(RTC->CR, RTC_CR_COSEL, CalibOutput); + + /* Enable calibration output */ + SET_BIT(RTC->CR, RTC_CR_COE); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Disable calibration output */ + CLEAR_BIT(RTC->CR, RTC_CR_COE); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Enable the RTC reference clock detection. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Enable clockref detection */ + SET_BIT(RTC->CR, RTC_CR_REFCKON); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Disable the RTC reference clock detection. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Disable clockref detection */ + CLEAR_BIT(RTC->CR, RTC_CR_REFCKON); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Enable the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set the BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Disable the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Reset the BYPSHAD bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Increment Monotonic counter. + * @param hrtc RTC handle + * @param Instance Monotonic counter Instance + * This parameter can be can be one of the following values : + * @arg RTC_MONOTONIC_COUNTER_1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance) +{ + UNUSED(hrtc); + UNUSED(Instance); + /* This register is read-only only and is incremented by one when a write access is done to this + register. This register cannot roll-over and is frozen when reaching the maximum value. */ + CLEAR_REG(TAMP->COUNTR); + + return HAL_OK; +} + +/** + * @brief Monotonic counter incrementation. + * @param hrtc RTC handle + * @param Instance Monotonic counter Instance + * This parameter can be can be one of the following values : + * @arg RTC_MONOTONIC_COUNTER_1 + * @param Value Pointer to the counter monotonic counter value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *Value) +{ + UNUSED(hrtc); + UNUSED(Instance); + + /* This register is read-only only and is incremented by one when a write access is done to this + register. This register cannot roll-over and is frozen when reaching the maximum value. */ + *Value = READ_REG(TAMP->COUNTR); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group4 + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) RTC Alarm B callback + (+) RTC Poll for Alarm B request + +@endverbatim + * @{ + */ + +/** + * @brief Alarm B callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle Alarm B Polling request. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Alarm Flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group5 + * @brief Extended RTC Tamper functions + * +@verbatim + ============================================================================== + ##### Tamper functions ##### + ============================================================================== + [..] + (+) Before calling any tamper or internal tamper function, you have to call first + HAL_RTC_Init() function. + (+) In that ine you can select to output tamper event on RTC pin. + [..] + (+) Enable the Tamper and configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, NoErase, MaskFlag, precharge or discharge and + Pull-UP, timestamp using the HAL_RTCEx_SetTamper() function. + You can configure Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function. + (+) The default configuration of the Tamper erases the backup registers. To avoid + erase, enable the NoErase field on the TAMP_TAMPCR register. + [..] + (+) Enable Internal Tamper and configure it with interrupt, timestamp using + the HAL_RTCEx_SetInternalTamper() function. + +@endverbatim + * @{ + */ + + +/** + * @brief Set Tamper + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) +{ + uint32_t tmpreg; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + /* Mask flag only supported by TAMPER 1, 2 and 3 */ + assert_param(!((sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (sTamper->Tamper > RTC_TAMPER_3))); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + /* Trigger and Filter have exclusive configurations */ + assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL))) + || ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)))); + + /* Configuration register 2 */ + tmpreg = READ_REG(TAMP->CR2); + tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); + + if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); + } + + if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos); + } + + if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos); + } + WRITE_REG(TAMP->CR2, tmpreg); + + /* Filter control register */ + WRITE_REG(TAMP->FLTCR, sTamper->Filter | sTamper->SamplingFrequency | sTamper->PrechargeDuration | sTamper->TamperPullUp); + + /* Timestamp on tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection) + { + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + + /* Control register 1 */ + SET_BIT(TAMP->CR1, sTamper->Tamper); + + return HAL_OK; +} + + +/** + * @brief Set Tamper in IT mode + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) +{ + uint32_t tmpreg; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + + /* Configuration register 2 */ + tmpreg = READ_REG(TAMP->CR2); + tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); + + if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); + } + + if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + /* Feature only supported by TAMPER 1, 2 and 3 */ + if (sTamper->Tamper <= RTC_TAMPER_3) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos); + } + else + { + return HAL_ERROR; + } + } + + if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos); + } + WRITE_REG(TAMP->CR2, tmpreg); + + /* Filter control register */ + WRITE_REG(TAMP->FLTCR, sTamper->Filter | sTamper->SamplingFrequency | sTamper->PrechargeDuration | sTamper->TamperPullUp); + + /* Timestamp on tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection) + { + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + + /* RTC Tamper Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TAMPER_EXTI_ENABLE_IT(); + + /* Interrupt enable register */ + SET_BIT(TAMP->IER, sTamper->Tamper); + + /* Control register 1 */ + SET_BIT(TAMP->CR1, sTamper->Tamper); + + return HAL_OK; +} + +/** + * @brief Deactivate Tamper. + * @param hrtc RTC handle + * @param Tamper Selected tamper pin. + * This parameter can be a combination of the following values: + * @arg RTC_TAMPER_1 + * @arg RTC_TAMPER_2 + * @arg RTC_TAMPER_3 + * @arg RTC_TAMPER_4 + * @arg RTC_TAMPER_5 + * @arg RTC_TAMPER_6 + * @arg RTC_TAMPER_7 + * @arg RTC_TAMPER_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) +{ + UNUSED(hrtc); + assert_param(IS_RTC_TAMPER(Tamper)); + + /* Disable the selected Tamper pin */ + CLEAR_BIT(TAMP->CR1, Tamper); + + /* Clear tamper mask/noerase/trigger configuration */ + CLEAR_BIT(TAMP->CR2, (Tamper << TAMP_CR2_TAMP1TRG_Pos) | (Tamper << TAMP_CR2_TAMP1MSK_Pos) | (Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); + + /* Clear tamper interrupt mode configuration */ + CLEAR_BIT(TAMP->IER, Tamper); + + /* Clear tamper interrupt and event flags (WO register) */ + WRITE_REG(TAMP->SCR, Tamper); + + return HAL_OK; +} + +/** + * @brief Set all active Tampers at the same time. + * @param hrtc RTC handle + * @param sAllTamper Pointer to active Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper) +{ + uint32_t IER, CR1, CR2, ATCR1, CR, i, tickstart; + +#ifdef USE_FULL_ASSERT + for (i = 0; i < RTC_TAMP_NB; i++) + { + assert_param(IS_RTC_TAMPER_ERASE_MODE(sAllTamper->TampInput[i].NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sAllTamper->TampInput[i].MaskFlag)); + /* Mask flag only supported by TAMPER 1, 2 and 3 */ + assert_param(!((sAllTamper->TampInput[i].MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (i > RTC_TAMPER_3))); + } + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sAllTamper->TimeStampOnTamperDetection)); +#endif /* #ifdef USE_FULL_ASSERT */ + + /* Active Tampers must not be already enabled */ + if (READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) != 0U) + { + /* Disable all actives tampers with HAL_RTCEx_DeactivateActiveTampers and try again */ + return HAL_ERROR; + } + + /* Set TimeStamp on tamper detection */ + CR = READ_REG(RTC->CR); + if ((CR & RTC_CR_TAMPTS) != (sAllTamper->TimeStampOnTamperDetection)) + { + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sAllTamper->TimeStampOnTamperDetection); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + + CR1 = READ_REG(TAMP->CR1); + CR2 = READ_REG(TAMP->CR2); + IER = READ_REG(TAMP->IER); + + /* Set common parameters */ + ATCR1 = (sAllTamper->ActiveFilter | (sAllTamper->ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos) | sAllTamper->ActiveAsyncPrescaler); + + /* Set specific parameters for each active tamper inputs if enable */ + for (i = 0; i < RTC_TAMP_NB; i++) + { + if (sAllTamper->TampInput[i].Enable != RTC_ATAMP_DISABLE) + { + CR1 |= (TAMP_CR1_TAMP1E << i); + ATCR1 |= (TAMP_ATCR1_TAMP1AM << i); + + if (sAllTamper->TampInput[i].Interrupt != RTC_ATAMP_INTERRUPT_DISABLE) + { + /* RTC Tamper Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TAMPER_EXTI_ENABLE_IT(); + + /* Interrupt enable register */ + IER |= (TAMP_IER_TAMP1IE << i); + } + + if (sAllTamper->TampInput[i].MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + CR2 |= (TAMP_CR2_TAMP1MSK << i); + } + + if (sAllTamper->TampInput[i].NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + CR2 |= (TAMP_CR2_TAMP1NOERASE << i); + } + + if (i != sAllTamper->TampInput[i].Output) + { + ATCR1 |= TAMP_ATCR1_ATOSHARE; + } + } + } + + WRITE_REG(TAMP->IER, IER); + WRITE_REG(TAMP->IER, IER); + WRITE_REG(TAMP->ATCR1, ATCR1); + WRITE_REG(TAMP->CR2, CR2); + WRITE_REG(TAMP->CR1, CR1); + + /* Write seed */ + for (i = 0; i < RTC_ATAMP_SEED_NB_UINT32; i++) + { + WRITE_REG(TAMP->ATSEEDR, sAllTamper->Seed[i]); + } + + /* Wait till RTC SEEDF flag is set and if Time out is reached exit */ + tickstart = HAL_GetTick(); + while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0u) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Write a new seed. Active tamper must be enabled. + * @param hrtc RTC handle + * @param pSeed Pointer to active tamper seed values. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed) +{ + uint32_t i, tickstart; + + /* Active Tampers must be enabled */ + if (READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == 0U) + { + return HAL_ERROR; + } + + for (i = 0; i < RTC_ATAMP_SEED_NB_UINT32; i++) + { + WRITE_REG(TAMP->ATSEEDR, pSeed[i]); + } + + /* Wait till RTC SEEDF flag is set and if Time out is reached exit */ + tickstart = HAL_GetTick(); + while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Deactivate all Active Tampers at the same time. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc) +{ + /* Get Active tampers */ + uint32_t ATamp_mask = READ_BIT(TAMP->ATCR1, TAMP_ALL); + + UNUSED(hrtc); + /* Disable all actives tampers but not passives tampers */ + CLEAR_BIT(TAMP->CR1, ATamp_mask); + /* Disable no erase and mask */ + CLEAR_BIT(TAMP->CR2, (ATamp_mask | ((ATamp_mask & (TAMP_ATCR1_TAMP1AM | TAMP_ATCR1_TAMP2AM | TAMP_ATCR1_TAMP3AM)) << TAMP_CR2_TAMP1MSK_Pos))); + + /* Clear tamper interrupt and event flags (WO register) of all actives tampers but not passives tampers */ + WRITE_REG(TAMP->SCR, ATamp_mask); + + /* Clear all active tampers interrupt mode configuration but not passives tampers */ + CLEAR_BIT(TAMP->IER, ATamp_mask); + + CLEAR_BIT(TAMP->ATCR1, TAMP_ALL | TAMP_ATCR1_ATCKSEL | TAMP_ATCR1_ATPER | \ + TAMP_ATCR1_ATOSHARE | TAMP_ATCR1_FLTEN); + + return HAL_OK; +} + + +/** + * @brief Tamper event polling. + * @param hrtc RTC handle + * @param Tamper Selected tamper pin. + * This parameter can be a combination of the following values: + * @arg RTC_TAMPER_1 + * @arg RTC_TAMPER_2 + * @arg RTC_TAMPER_3 + * @arg RTC_TAMPER_4 + * @arg RTC_TAMPER_5 + * @arg RTC_TAMPER_6 + * @arg RTC_TAMPER_7 + * @arg RTC_TAMPER_8 + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout) +{ + UNUSED(hrtc); + assert_param(IS_RTC_TAMPER(Tamper)); + + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while (READ_BIT(TAMP->SR, Tamper) != Tamper) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + WRITE_REG(TAMP->SCR, Tamper); + + return HAL_OK; +} + + +/** + * @brief Set Internal Tamper in interrupt mode + * @param hrtc RTC handle + * @param sIntTamper Pointer to Internal Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sIntTamper->NoErase)); + + /* timestamp on internal tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection) + { + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + + /* Control register 1 */ + SET_BIT(TAMP->CR1, sIntTamper->IntTamper); + + return HAL_OK; +} + + +/** + * @brief Set Internal Tamper + * @param hrtc RTC handle + * @param sIntTamper Pointer to Internal Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sIntTamper->NoErase)); + + /* timestamp on internal tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection) + { + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + + /* RTC Tamper Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TAMPER_EXTI_ENABLE_IT(); + + /* Interrupt enable register */ + SET_BIT(TAMP->IER, sIntTamper->IntTamper); + + /* Control register 1 */ + SET_BIT(TAMP->CR1, sIntTamper->IntTamper); + + return HAL_OK; +} + +/** + * @brief Deactivate Internal Tamper. + * @param hrtc RTC handle + * @param IntTamper Selected internal tamper event. + * This parameter can be any combination of existing internal tampers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper) +{ + UNUSED(hrtc); + assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper)); + + /* Disable the selected Tamper pin */ + CLEAR_BIT(TAMP->CR1, IntTamper); + + /* Clear internal tamper interrupt mode configuration */ + CLEAR_BIT(TAMP->IER, IntTamper); + + /* Clear internal tamper interrupt */ + WRITE_REG(TAMP->SCR, IntTamper); + + return HAL_OK; +} + + +/** + * @brief Internal Tamper event polling. + * @param hrtc RTC handle + * @param IntTamper selected tamper. + * This parameter can be any combination of existing internal tampers. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout) +{ + UNUSED(hrtc); + assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper)); + + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while (READ_BIT(TAMP->SR, IntTamper) != IntTamper) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + WRITE_REG(TAMP->SCR, IntTamper); + + return HAL_OK; +} + + +#if defined (CORTEX_IN_SECURE_STATE) +/** + * @brief Handle Tamper secure interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) +{ + uint32_t tmp; + + /* Get secure interrupt status */ + tmp = READ_REG(TAMP->SMISR); + + /* Immediatly clear flags */ + WRITE_REG(TAMP->SCR, tmp); + + /* Check Tamper1 status */ + if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 1 Event registered secure Callback */ + hrtc->Tamper1EventCallback(hrtc); +#else + /* Tamper1 secure callback */ + HAL_RTCEx_Tamper1EventCallback(hrtc); +#endif + } + + /* Check Tamper2 status */ + if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 2 Event registered secure Callback */ + hrtc->Tamper2EventCallback(hrtc); +#else + /* Tamper2 secure callback */ + HAL_RTCEx_Tamper2EventCallback(hrtc); +#endif + } + + /* Check Tamper3 status */ + if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 3 Event registered secure Callback */ + hrtc->Tamper3EventCallback(hrtc); +#else + /* Tamper3 secure callback */ + HAL_RTCEx_Tamper3EventCallback(hrtc); +#endif + } + + /* Check Internal Tamper1 status */ + if ((tmp & RTC_INT_TAMPER_1) == RTC_INT_TAMPER_1) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 1 Event registered secure Callback */ + hrtc->InternalTamper1EventCallback(hrtc); +#else + /* Internal Tamper1 secure callback */ + HAL_RTCEx_InternalTamper1EventCallback(hrtc); +#endif + } + + /* Check Internal Tamper2 status */ + if ((tmp & RTC_INT_TAMPER_2) == RTC_INT_TAMPER_2) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 2 Event registered secure Callback */ + hrtc->InternalTamper2EventCallback(hrtc); +#else + /* Internal Tamper2 secure callback */ + HAL_RTCEx_InternalTamper2EventCallback(hrtc); +#endif + } + + /* Check Internal Tamper3 status */ + if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 3 Event registered secure Callback */ + hrtc->InternalTamper3EventCallback(hrtc); +#else + /* Internal Tamper3 secure callback */ + HAL_RTCEx_InternalTamper3EventCallback(hrtc); +#endif + } + + /* Check Internal Tamper4 status */ + if ((tmp & RTC_INT_TAMPER_4) == RTC_INT_TAMPER_4) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 4 Event registered Callback */ + hrtc->InternalTamper4EventCallback(hrtc); +#else + /* Internal Tamper4 callback */ + HAL_RTCEx_InternalTamper4EventCallback(hrtc); +#endif + } + + /* Check Internal Tamper5 status */ + if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 5 Event registered secure Callback */ + hrtc->InternalTamper5EventCallback(hrtc); +#else + /* Internal Tamper5 secure callback */ + HAL_RTCEx_InternalTamper5EventCallback(hrtc); +#endif + } + + /* Check Internal Tamper8 status */ + if ((tmp & RTC_INT_TAMPER_8) == RTC_INT_TAMPER_8) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 8 Event registered secure Callback */ + hrtc->InternalTamper8EventCallback(hrtc); +#else + /* Internal Tamper8 secure callback */ + HAL_RTCEx_InternalTamper8EventCallback(hrtc); +#endif + } +} + +#else /* #if defined (CORTEX_IN_SECURE_STATE) */ + +/** + * @brief Handle Tamper non-secure interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get interrupt status */ + uint32_t tmp = READ_REG(TAMP->MISR); + + /* Immediately clear flags */ + WRITE_REG(TAMP->SCR, tmp); + + /* Check Tamper1 status */ + if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 1 Event registered Callback */ + hrtc->Tamper1EventCallback(hrtc); +#else + /* Tamper1 callback */ + HAL_RTCEx_Tamper1EventCallback(hrtc); +#endif + } + + /* Check Tamper2 status */ + if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 2 Event registered Callback */ + hrtc->Tamper2EventCallback(hrtc); +#else + /* Tamper2 callback */ + HAL_RTCEx_Tamper2EventCallback(hrtc); +#endif + } + + /* Check Tamper3 status */ + if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 3 Event registered Callback */ + hrtc->Tamper3EventCallback(hrtc); +#else + /* Tamper3 callback */ + HAL_RTCEx_Tamper3EventCallback(hrtc); +#endif + } + + /* Check Internal Tamper1 status */ + if ((tmp & RTC_INT_TAMPER_1) == RTC_INT_TAMPER_1) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 1 Event registered Callback */ + hrtc->InternalTamper1EventCallback(hrtc); +#else + /* Internal Tamper1 callback */ + HAL_RTCEx_InternalTamper1EventCallback(hrtc); +#endif + } + + /* Check Internal Tamper2 status */ + if ((tmp & RTC_INT_TAMPER_2) == RTC_INT_TAMPER_2) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 2 Event registered Callback */ + hrtc->InternalTamper2EventCallback(hrtc); +#else + /* Internal Tamper2 callback */ + HAL_RTCEx_InternalTamper2EventCallback(hrtc); +#endif + } + + /* Check Internal Tamper3 status */ + if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 3 Event registered Callback */ + hrtc->InternalTamper3EventCallback(hrtc); +#else + /* Internal Tamper3 callback */ + HAL_RTCEx_InternalTamper3EventCallback(hrtc); +#endif + } + + /* Check Internal Tamper4 status */ + if ((tmp & RTC_INT_TAMPER_4) == RTC_INT_TAMPER_4) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 4 Event registered Callback */ + hrtc->InternalTamper4EventCallback(hrtc); +#else + /* Internal Tamper4 callback */ + HAL_RTCEx_InternalTamper4EventCallback(hrtc); +#endif + } + + /* Check Internal Tamper5 status */ + if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 5 Event registered Callback */ + hrtc->InternalTamper5EventCallback(hrtc); +#else + /* Internal Tamper5 callback */ + HAL_RTCEx_InternalTamper5EventCallback(hrtc); +#endif + } + + /* Check Internal Tamper8 status */ + if ((tmp & RTC_INT_TAMPER_8) == RTC_INT_TAMPER_8) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 8 Event registered Callback */ + hrtc->InternalTamper8EventCallback(hrtc); +#else + /* Internal Tamper8 callback */ + HAL_RTCEx_InternalTamper8EventCallback(hrtc); +#endif + } +} +#endif /* #if defined (CORTEX_IN_SECURE_STATE) */ + +/** + * @brief Tamper 1 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 2 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 3 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file + */ +} + + +/** + * @brief Internal Tamper 1 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper1EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 2 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper2EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 3 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper3EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 4 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper3EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 5 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper5EventCallback could be implemented in the user file + */ +} + + +/** + * @brief Internal Tamper 8 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper8EventCallback could be implemented in the user file + */ +} +/** + * @} + */ + + +/** @addtogroup RTCEx_Exported_Functions_Group6 + * @brief Extended RTC Backup register functions + * +@verbatim + =============================================================================== + ##### Extended RTC Backup register functions ##### + =============================================================================== + [..] + (+) Before calling any tamper or internal tamper function, you have to call first + HAL_RTC_Init() function. + (+) In that ine you can select to output tamper event on RTC pin. + [..] + This subsection provides functions allowing to + (+) Write a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register +@endverbatim + * @{ + */ + + +/** + * @brief Write a data in a specified RTC Backup data register. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. + * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB + * @param Data Data to be written in the specified Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + uint32_t tmp; + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) & (TAMP->BKP0R); + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. + * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB + * @retval Read value + */ +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + uint32_t tmp; + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) & (TAMP->BKP0R); + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + + +/** @addtogroup RTCEx_Exported_Functions_Group7 + * @brief Extended RTC security functions + * +@verbatim + =============================================================================== + ##### Extended RTC security functions ##### + =============================================================================== + [..] + (+) Before calling security function, you have to call first + HAL_RTC_Init() function. +@endverbatim + * @{ + */ + +/** + * @brief Get the security level of the RTC. + * To set the secure level please call HAL_RTCEx_SecureModeSet. + * @param hrtc RTC handle + * @param secureState Secure state + * @retval HAL_StatusTypeDef + */ +HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState) +{ + UNUSED(hrtc); + /* Read registers */ + uint32_t rtc_smcr = READ_REG(RTC->SMCR); + uint32_t tamp_smcr = READ_REG(TAMP->SMCR); + + /* RTC */ + secureState->rtcSecureFull = READ_BIT(rtc_smcr, RTC_SMCR_DECPROT); + + /* Warning, rtcNonSecureFeatures is only relevant if secureState->rtcSecureFull == RTC_SECURE_FULL_NO */ + secureState->rtcNonSecureFeatures = READ_BIT(rtc_smcr, RTC_NONSECURE_FEATURE_ALL); + + /* TAMP */ + secureState->tampSecureFull = READ_BIT(tamp_smcr, TAMP_SMCR_TAMPDPROT); + + /* Backup register start zones + Warning : Backup register start zones are shared with privilege configuration */ + secureState->backupRegisterStartZone2 = READ_BIT(tamp_smcr, TAMP_SMCR_BKPRWDPROT) >> TAMP_SMCR_BKPRWDPROT_Pos; + secureState->backupRegisterStartZone3 = READ_BIT(tamp_smcr, TAMP_SMCR_BKPWDPROT) >> TAMP_SMCR_BKPWDPROT_Pos; + + return HAL_OK; +} + + +#if defined (CORTEX_IN_SECURE_STATE) +/** + * @brief Set the security level of the RTC/TAMP/Backup registers. + * To get the current security level call HAL_RTCEx_SecureModeGet. + * @param hrtc RTC handle + * @param secureState Secure state + * @retval HAL_StatusTypeDef + */ +HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState) +{ + UNUSED(hrtc); + assert_param(IS_RTC_SECURE_FULL(secureState->rtcSecureFull)); + assert_param(IS_RTC_NONSECURE_FEATURES(secureState->rtcNonSecureFeatures)); + assert_param(IS_TAMP_SECURE_FULL(secureState->tampSecureFull)); + assert_param(IS_RTC_BKP(secureState->backupRegisterStartZone2)); + assert_param(IS_RTC_BKP(secureState->backupRegisterStartZone3)); + + /* RTC, rtcNonSecureFeatures is only relevant if secureState->rtcSecureFull == RTC_SECURE_FULL_NO */ + WRITE_REG(RTC->SMCR, secureState->rtcSecureFull | secureState->rtcNonSecureFeatures); + + /* Tamper + Backup register + Warning : Backup register start zone are Shared with privilege configuration */ + WRITE_REG(TAMP->SMCR, + secureState->tampSecureFull | + (TAMP_SMCR_BKPRWDPROT & (secureState->backupRegisterStartZone2 << TAMP_SMCR_BKPRWDPROT_Pos)) | + (TAMP_SMCR_BKPWDPROT & (secureState->backupRegisterStartZone3 << TAMP_SMCR_BKPWDPROT_Pos))); + + return HAL_OK; +} +#endif /* #if defined (CORTEX_IN_SECURE_STATE) */ + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd.c old mode 100644 new mode 100755 diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd_ex.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sd_ex.c old mode 100644 new mode 100755 diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sram.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sram.c new file mode 100644 index 0000000000..34352fb07e --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sram.c @@ -0,0 +1,1113 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_hal_sram.c + * @author MCD Application Team + * @brief SRAM HAL module driver. + * This file provides a generic firmware to drive SRAM memories + * mounted as external device. + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a generic layered driver which contains a set of APIs used to + control SRAM memories. It uses the FMC layer functions to interface + with SRAM devices. + The following sequence should be followed to configure the FMC to interface + with SRAM/PSRAM memories: + + (#) Declare a SRAM_HandleTypeDef handle structure, for example: + SRAM_HandleTypeDef hsram; and: + + (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed + values of the structure member. + + (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined + base register instance for NOR or SRAM device + + (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined + base register instance for NOR or SRAM extended mode + + (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended + mode timings; for example: + FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming; + and fill its fields with the allowed values of the structure member. + + (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function + performs the following sequence: + + (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit() + (##) Control register configuration using the FMC NORSRAM interface function + FMC_NORSRAM_Init() + (##) Timing register configuration using the FMC NORSRAM interface function + FMC_NORSRAM_Timing_Init() + (##) Extended mode Timing register configuration using the FMC NORSRAM interface function + FMC_NORSRAM_Extended_Timing_Init() + (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE() + + (#) At this stage you can perform read/write accesses from/to the memory connected + to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the + following APIs: + (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access + (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer + + (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/ + HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation + + (#) You can continuously monitor the SRAM device HAL state by calling the function + HAL_SRAM_GetState() + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) MspInitCallback : SRAM MspInit. + (+) MspDeInitCallback : SRAM MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) MspInitCallback : SRAM MspInit. + (+) MspDeInitCallback : SRAM MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init + and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit + or @ref HAL_SRAM_Init function. + + When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_hal.h" + + +/** @addtogroup STM32MP1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_SRAM_MODULE_ENABLED + +/** @defgroup SRAM SRAM + * @brief SRAM driver modules + * @{ + */ + +/** + @cond 0 + */ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void SRAM_DMACplt (DMA_HandleTypeDef *hdma); +static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma); +static void SRAM_DMAError (DMA_HandleTypeDef *hdma); +/** + @endcond + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SRAM_Exported_Functions SRAM Exported Functions + * @{ + */ + +/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * + @verbatim + ============================================================================== + ##### SRAM Initialization and de_initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to initialize/de-initialize + the SRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Performs the SRAM device initialization sequence + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param Timing Pointer to SRAM control timing structure + * @param ExtTiming Pointer to SRAM extended mode timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) +{ + /* Check the SRAM handle parameter */ + if (hsram == NULL) + { + return HAL_ERROR; + } + + if (hsram->State == HAL_SRAM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsram->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + if(hsram->MspInitCallback == NULL) + { + hsram->MspInitCallback = HAL_SRAM_MspInit; + } + hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; + hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + + /* Init the low level hardware */ + hsram->MspInitCallback(hsram); +#else + /* Initialize the low level hardware (MSP) */ + HAL_SRAM_MspInit(hsram); +#endif + } + + /* Initialize SRAM control Interface */ + (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); + + /* Initialize SRAM timing Interface */ + (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); + + /* Initialize SRAM extended mode timing Interface */ + (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); + + /* Enable the NORSRAM device */ + __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); + + /* Enable FMC Peripheral */ + __FMC_ENABLE(); + + /* Initialize the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Performs the SRAM device De-initialization sequence. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) +{ +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + if(hsram->MspDeInitCallback == NULL) + { + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + } + + /* DeInit the low level hardware */ + hsram->MspDeInitCallback(hsram); +#else + /* De-Initialize the low level hardware (MSP) */ + HAL_SRAM_MspDeInit(hsram); +#endif + + /* Configure the SRAM registers with their reset values */ + (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); + + /* Reset the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsram); + + return HAL_OK; +} + +/** + * @brief SRAM MSP Init. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsram); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_MspInit could be implemented in the user file + */ +} + +/** + * @brief SRAM MSP DeInit. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsram); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete error callback. + * @param hdma pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval None + */ +__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions + * @brief Input Output and memory control functions + * + @verbatim + ============================================================================== + ##### SRAM Input and Output functions ##### + ============================================================================== + [..] + This section provides functions allowing to use and control the SRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Reads 8-bit buffer from SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) +{ + uint32_t size; + __IO uint8_t *psramaddress = (uint8_t *)pAddress; + uint8_t * pdestbuff = pDstBuffer; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Read data from memory */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *psramaddress; + pdestbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 8-bit buffer to SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) +{ + uint32_t size; + __IO uint8_t *psramaddress = (uint8_t *)pAddress; + uint8_t * psrcbuff = pSrcBuffer; + + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *psramaddress = *psrcbuff; + psrcbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads 16-bit buffer from SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint16_t *pdestbuff = pDstBuffer; + uint8_t limit; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Check if the size is a 32-bits mulitple */ + limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); + + /* Read data from memory */ + for (size = BufferSize; size != limit; size-=2U) + { + *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); + pdestbuff++; + *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U); + pdestbuff++; + psramaddress++; + } + + /* Read last 16-bits if size is not 32-bits multiple */ + if (limit != 0U) + { + *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); + } + + /* Update the SRAM controller state */ + hsram->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 16-bit buffer to SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint16_t * psrcbuff = pSrcBuffer; + uint8_t limit; + + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Check if the size is a 32-bits mulitple */ + limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); + + /* Write data to memory */ + for (size = BufferSize; size != limit; size-=2U) + { + *psramaddress = (uint32_t)(*psrcbuff); + psrcbuff++; + *psramaddress |= ((uint32_t)(*psrcbuff) << 16U); + psrcbuff++; + psramaddress++; + } + + /* Write last 16-bits if size is not 32-bits multiple */ + if (limit != 0U) + { + *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U); + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads 32-bit buffer from SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t * psramaddress = pAddress; + uint32_t * pdestbuff = pDstBuffer; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Read data from memory */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *psramaddress; + pdestbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 32-bit buffer to SRAM memory. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t * psramaddress = pAddress; + uint32_t * psrcbuff = pSrcBuffer; + + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *psramaddress = *psrcbuff; + psrcbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads a Words data from the SRAM memory using DMA transfer. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +{ + HAL_StatusTypeDef status; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + if (state == HAL_SRAM_STATE_READY) + { + hsram->hdma->XferCpltCallback = SRAM_DMACplt; + } + else + { + hsram->hdma->XferCpltCallback = SRAM_DMACpltProt; + } + hsram->hdma->XferErrorCallback = SRAM_DMAError; + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return status; +} + +/** + * @brief Writes a Words data buffer to SRAM memory using DMA transfer. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +{ + HAL_StatusTypeDef status; + + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + hsram->hdma->XferCpltCallback = SRAM_DMACplt; + hsram->hdma->XferErrorCallback = SRAM_DMAError; + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return status; +} + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SRAM Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hsram : SRAM handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID + * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SRAM_StateTypeDef state; + + if(pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsram); + + state = hsram->State; + if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = pCallback; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsram); + return status; +} + +/** + * @brief Unregister a User SRAM Callback + * SRAM Callback is redirected to the weak (surcharged) predefined callback + * @param hsram : SRAM handle + * @param CallbackId : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID + * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID + * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SRAM_StateTypeDef state; + + /* Process locked */ + __HAL_LOCK(hsram); + + state = hsram->State; + if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(state == HAL_SRAM_STATE_RESET) + { + switch (CallbackId) + { + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsram); + return status; +} + +/** + * @brief Register a User SRAM Callback for DMA transfers + * To be used instead of the weak (surcharged) predefined callback + * @param hsram : SRAM handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SRAM_StateTypeDef state; + + if(pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsram); + + state = hsram->State; + if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = pCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsram); + return status; +} +#endif + +/** + * @} + */ + +/** @defgroup SRAM_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### SRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the SRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically SRAM write operation. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) +{ + /* Check the SRAM controller state */ + if(hsram->State == HAL_SRAM_STATE_PROTECTED) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Enable write operation */ + (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disables dynamically SRAM write operation. + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) +{ + /* Check the SRAM controller state */ + if(hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Disable write operation */ + (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_PROTECTED; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### SRAM State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the SRAM controller + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the SRAM controller state + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains + * the configuration information for SRAM module. + * @retval HAL state + */ +HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) +{ + return hsram->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + @cond 0 + */ +/** + * @brief DMA SRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferCpltCallback(hdma); +#else + HAL_SRAM_DMA_XferCpltCallback(hdma); +#endif +} + +/** + * @brief DMA SRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_PROTECTED; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferCpltCallback(hdma); +#else + HAL_SRAM_DMA_XferCpltCallback(hdma); +#endif +} + +/** + * @brief DMA SRAM error callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMAError(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_ERROR; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferErrorCallback(hdma); +#else + HAL_SRAM_DMA_XferErrorCallback(hdma); +#endif +} +/** + @endcond + */ + +/** + * @} + */ + +#endif /* HAL_SRAM_MODULE_ENABLED */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c index 228915a143..d6112522d8 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c @@ -193,9 +193,6 @@ /** @addtogroup UART_Private_Functions * @{ */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_EndRxTransfer(UART_HandleTypeDef *huart); static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -217,7 +214,7 @@ static void UART_MDMATxAbortCallback(MDMA_HandleTypeDef *hmdma); static void UART_MDMARxAbortCallback(MDMA_HandleTypeDef *hmdma); static void UART_MDMATxOnlyAbortCallback(MDMA_HandleTypeDef *hmdma); static void UART_MDMARxOnlyAbortCallback(MDMA_HandleTypeDef *hmdma); -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); @@ -345,7 +342,6 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -365,7 +361,6 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -412,7 +407,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -435,7 +429,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -500,7 +493,6 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -526,7 +518,6 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /* Set the USART LIN Break detection length. */ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -586,7 +577,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -615,7 +605,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Set the wake up method by setting the WAKE bit in the CR1 register */ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -641,7 +630,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); huart->Instance->CR1 = 0x0U; @@ -664,7 +652,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; - /* Process Unlock */ __HAL_UNLOCK(huart); return HAL_OK; @@ -723,18 +710,18 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ + __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_READY) @@ -794,10 +781,8 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } @@ -815,24 +800,19 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } } else { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ __HAL_UNLOCK(huart); return status; @@ -863,7 +843,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ __HAL_LOCK(huart); if (HAL_UART_STATE_READY == huart->gState) @@ -923,10 +902,8 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } @@ -944,24 +921,19 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } } else { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ __HAL_UNLOCK(huart); return status; @@ -1051,20 +1023,24 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR /** * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @note When FIFO mode is enabled, writing a data in the TDR register adds one * data to the TXFIFO. Write operations to the TDR register are performed * when TXFNF flag is set. From hardware perspective, TXFNF flag and * TXE are mapped on the same bit-field. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t *tmp; - uint32_t tickstart = 0U; + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) @@ -1074,7 +1050,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -1086,21 +1061,35 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u huart->TxXferSize = Size; huart->TxXferCount = Size; + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + __HAL_UNLOCK(huart); + while (huart->TxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + if (pdata8bits == NULL) { - tmp = (uint16_t *) pData; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); - pData += 2U; + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; } else { - huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU); + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; } huart->TxXferCount--; } @@ -1113,9 +1102,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -1126,21 +1112,25 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO * is not empty. Read operations from the RDR register are performed when * RXFNE flag is set. From hardware perspective, RXFNE flag and * RXNE are mapped on the same bit-field. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t *tmp; + uint8_t *pdata8bits; + uint16_t *pdata16bits; uint16_t uhMask; - uint32_t tickstart = 0; + uint32_t tickstart; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) @@ -1150,7 +1140,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -1166,6 +1155,20 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui UART_MASK_COMPUTATION(huart); uhMask = huart->Mask; + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + __HAL_UNLOCK(huart); + /* as long as data have to be received */ while (huart->RxXferCount > 0U) { @@ -1173,15 +1176,15 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui { return HAL_TIMEOUT; } - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + if (pdata8bits == NULL) { - tmp = (uint16_t *) pData ; - *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - pData += 2U; + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; } else { - *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; } huart->RxXferCount--; } @@ -1189,9 +1192,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -1202,9 +1202,12 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1217,7 +1220,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pTxBuffPtr = pData; @@ -1241,7 +1243,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxISR = UART_TxISR_8BIT_FIFOEN; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the TX FIFO threshold interrupt */ @@ -1259,7 +1260,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxISR = UART_TxISR_8BIT; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the Transmit Data Register Empty interrupt */ @@ -1276,9 +1276,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1291,7 +1294,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pRxBuffPtr = pData; @@ -1321,7 +1323,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, huart->RxISR = UART_RxISR_8BIT_FIFOEN; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ @@ -1340,7 +1341,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, huart->RxISR = UART_RxISR_8BIT; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ @@ -1357,9 +1357,12 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /** * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1372,7 +1375,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pTxBuffPtr = pData; @@ -1397,7 +1399,18 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat huart->hdmatx->XferAbortCallback = NULL; /* Enable the UART transmit DMA channel */ - HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size); + if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } } #ifdef HAL_MDMA_MODULE_ENABLED if (huart->hmdmatx != NULL) @@ -1412,13 +1425,23 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat huart->hmdmatx->XferAbortCallback = NULL; /* Enable the UART transmit MDMA channel */ - HAL_MDMA_Start_IT(huart->hmdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size, 1); + if (HAL_MDMA_Start_IT(huart->hmdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size, 1) != HAL_OK) + { + /* Set error code to MDMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } } -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the DMA transfer for transmit request by setting the DMAT bit @@ -1437,9 +1460,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat * @brief Receive an amount of data in DMA mode. * @note When the UART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1452,7 +1478,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pRxBuffPtr = pData; @@ -1476,7 +1501,18 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData huart->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size); + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } } #ifdef HAL_MDMA_MODULE_ENABLED if (huart->hmdmarx != NULL) @@ -1491,10 +1527,20 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData huart->hmdmarx->XferAbortCallback = NULL; /* Enable the MDMA channel */ - HAL_MDMA_Start_IT(huart->hmdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size, 1); + if (HAL_MDMA_Start_IT(huart->hmdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size, 1) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } } -#endif - /* Process Unlocked */ +#endif /* HAL_MDMA_MODULE_ENABLED */ __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ @@ -1522,17 +1568,19 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData */ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) { - /* Process Locked */ + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + __HAL_LOCK(huart); - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) { /* Disable the UART DMA Tx request */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); @@ -1542,7 +1590,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1555,7 +1602,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_BUSY_TX) @@ -1576,7 +1622,6 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1590,52 +1635,91 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) { /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / - HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; /* Stop UART DMA Tx request if ongoing */ - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel */ if (huart->hdmatx != NULL) { - HAL_DMA_Abort(huart->hdmatx); + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } #ifdef HAL_MDMA_MODULE_ENABLED /* Abort the UART MDMA Tx channel */ if (huart->hmdmatx != NULL) { - HAL_MDMA_Abort(huart->hmdmatx); + if (HAL_MDMA_Abort(huart->hmdmatx) != HAL_OK) + { + if (HAL_MDMA_GetError(huart->hmdmatx) == HAL_MDMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ UART_EndTxTransfer(huart); } /* Stop UART DMA Rx request if ongoing */ - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) { - HAL_DMA_Abort(huart->hdmarx); + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } #ifdef HAL_MDMA_MODULE_ENABLED /* Abort the UART MDMA Rx channel */ if (huart->hmdmarx != NULL) { - HAL_MDMA_Abort(huart->hmdmarx); + if (HAL_MDMA_Abort(huart->hmdmarx) != HAL_OK) + { + if (HAL_MDMA_GetError(huart->hmdmarx) == HAL_MDMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ UART_EndRxTransfer(huart); } @@ -1654,7 +1738,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1673,7 +1757,16 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; - HAL_DMA_Abort(huart->hdmatx); + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } #ifdef HAL_MDMA_MODULE_ENABLED /* Abort the UART MDMA Tx channel : use blocking DMA Abort API (no callback) */ @@ -1683,9 +1776,18 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) No call back execution at end of MDMA abort procedure */ huart->hmdmatx->XferAbortCallback = NULL; - HAL_MDMA_Abort(huart->hmdmatx); + if (HAL_MDMA_Abort(huart->hmdmatx) != HAL_OK) + { + if (HAL_MDMA_GetError(huart->hmdmatx) == HAL_MDMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ } /* Disable the UART DMA Rx request if enabled */ @@ -1700,7 +1802,16 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; - HAL_DMA_Abort(huart->hdmarx); + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } #ifdef HAL_MDMA_MODULE_ENABLED /* Abort the UART MDMA Rx channel : use blocking DMA Abort API (no callback) */ @@ -1710,9 +1821,18 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) No call back execution at end of DMA abort procedure */ huart->hmdmarx->XferAbortCallback = NULL; - HAL_MDMA_Abort(huart->hmdmarx); + if (HAL_MDMA_Abort(huart->hmdmarx) != HAL_OK) + { + if (HAL_MDMA_GetError(huart->hmdmarx) == HAL_MDMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ } /* Reset Tx and Rx transfer counters */ @@ -1735,7 +1855,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Reset Handle ErrorCode to No Error */ huart->ErrorCode = HAL_UART_ERROR_NONE; return HAL_OK; @@ -1752,7 +1871,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { /* Disable TCIE, TXEIE and TXFTIE interrupts */ @@ -1771,7 +1890,16 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) No call back execution at end of DMA abort procedure */ huart->hdmatx->XferAbortCallback = NULL; - HAL_DMA_Abort(huart->hdmatx); + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } #ifdef HAL_MDMA_MODULE_ENABLED /* Abort the UART MDMA Tx channel : use blocking MDMA Abort API (no callback) */ @@ -1781,9 +1909,18 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) No call back execution at end of MDMA abort procedure */ huart->hmdmatx->XferAbortCallback = NULL; - HAL_MDMA_Abort(huart->hmdmatx); + if (HAL_MDMA_Abort(huart->hmdmatx) != HAL_OK) + { + if (HAL_MDMA_GetError(huart->hmdmatx) == HAL_MDMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ } /* Reset Tx transfer counter */ @@ -1812,7 +1949,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ @@ -1831,7 +1968,16 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) No call back execution at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = NULL; - HAL_DMA_Abort(huart->hdmarx); + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } #ifdef HAL_MDMA_MODULE_ENABLED /* Abort the UART MDMA Rx channel : use blocking MDMA Abort API (no callback) */ @@ -1841,9 +1987,18 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) No call back execution at end of MDMA abort procedure */ huart->hmdmarx->XferAbortCallback = NULL; - HAL_MDMA_Abort(huart->hmdmarx); + if (HAL_MDMA_Abort(huart->hmdmarx) != HAL_OK) + { + if (HAL_MDMA_GetError(huart->hmdmarx) == HAL_MDMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } } -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ } /* Reset Rx transfer counter */ @@ -1874,7 +2029,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { uint32_t abortcplt = 1U; @@ -1942,7 +2097,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) huart->hmdmarx->XferAbortCallback = NULL; } } -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) @@ -1983,7 +2138,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) abortcplt = 0U; } } -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ } /* Disable the UART DMA Rx request if enabled */ @@ -2026,7 +2181,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) abortcplt = 0U; } } -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ } /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ @@ -2085,7 +2240,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { /* Disable interrupts */ @@ -2126,7 +2281,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) huart->hmdmatx->XferAbortCallback(huart->hmdmatx); } } -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ else { /* Reset Tx transfer counter */ @@ -2191,7 +2346,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -2232,7 +2387,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) huart->hmdmarx->XferAbortCallback(huart->hmdmarx); } } -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ else { /* Reset Rx transfer counter */ @@ -2297,16 +2452,18 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) uint32_t isrflags = READ_REG(huart->Instance->ISR); uint32_t cr1its = READ_REG(huart->Instance->CR1); uint32_t cr3its = READ_REG(huart->Instance->CR3); + uint32_t errorflags; + uint32_t errorcode; /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); - if (errorflags == RESET) + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) { /* UART in mode Receiver ---------------------------------------------------*/ - if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET))) + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) { if (huart->RxISR != NULL) { @@ -2317,12 +2474,12 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* If some errors occur */ - if ((errorflags != RESET) - && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET)))) + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) { /* UART parity error interrupt occurred -------------------------------------*/ - if (((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); @@ -2330,7 +2487,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* UART frame error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); @@ -2338,7 +2495,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* UART noise error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); @@ -2346,22 +2503,30 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* UART Over-Run interrupt occurred -----------------------------------------*/ - if (((isrflags & USART_ISR_ORE) != RESET) - && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || - ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET))) + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); huart->ErrorCode |= HAL_UART_ERROR_ORE; } - /* Call UART Error Call back function if need be --------------------------*/ + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) { - /* UART in mode Receiver ---------------------------------------------------*/ - if (((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET))) + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) { if (huart->RxISR != NULL) { @@ -2369,10 +2534,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } } - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, @@ -2413,7 +2582,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->hmdmarx->XferAbortCallback(huart->hmdmarx); } } -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ else { /* Call user error callback */ @@ -2458,7 +2627,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* End if some error occurs */ /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ - if (((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET)) + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); @@ -2476,9 +2645,9 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* UART in mode Transmitter ------------------------------------------------*/ - if (((isrflags & USART_ISR_TXE_TXFNF) != RESET) - && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) - || ((cr3its & USART_CR3_TXFTIE) != RESET))) + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) { if (huart->TxISR != NULL) { @@ -2488,14 +2657,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* UART in mode Transmitter (transmission end) -----------------------------*/ - if (((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) { UART_EndTransmit_IT(huart); return; } /* UART TX Fifo Empty occurred ----------------------------------------------*/ - if (((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ @@ -2508,7 +2677,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* UART RX Fifo Full occurred ----------------------------------------------*/ - if (((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ @@ -2538,7 +2707,7 @@ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Tx Half Transfer completed callback. - * @param huart UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) @@ -2552,8 +2721,8 @@ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) } /** - * @brief Rx Transfer completed callback. - * @param huart UART handle. + * @brief Rx Transfer completed callback. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) @@ -2568,7 +2737,7 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Rx Half Transfer completed callback. - * @param huart UART handle. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) @@ -2582,8 +2751,8 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) } /** - * @brief UART error callback. - * @param huart UART handle. + * @brief UART error callback. + * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) @@ -2654,14 +2823,15 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) =============================================================================== [..] This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode - (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) UART_SetConfig() API configures the UART peripheral (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization - (+) UART_Wakeup_AddressConfig() API configures the wake-up from stop mode parameters (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver (+) HAL_LIN_SendBreak() API transmits the break characters @@ -2670,14 +2840,89 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) */ /** - * @brief Enable UART in mute mode (does not mean UART enters mute mode; - * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). - * @param huart UART handle. + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2691,14 +2936,13 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) } /** - * @brief Disable UART mute mode (does not mean the UART actually exits mute mode - * as it may not have been in mute mode at this very moment). - * @param huart UART handle. + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2724,12 +2968,11 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) /** * @brief Enable the UART transmitter and disable the UART receiver. - * @param huart UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2741,7 +2984,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2749,12 +2991,11 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) /** * @brief Enable the UART receiver and disable the UART transmitter. - * @param huart UART handle. + * @param huart UART handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2766,7 +3007,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2775,7 +3015,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) /** * @brief Transmit break characters. - * @param huart UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) @@ -2783,17 +3023,15 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /* Check the parameters */ assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; /* Send break characters */ - SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST); + __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2804,8 +3042,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) */ /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief UART Peripheral State functions - * + * @brief UART Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -2822,12 +3060,13 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /** * @brief Return the UART handle state. * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. + * the configuration information for the specified UART. * @retval HAL state */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - uint32_t temp1 = 0x00U, temp2 = 0x00U; + uint32_t temp1; + uint32_t temp2; temp1 = huart->gState; temp2 = huart->RxState; @@ -2835,11 +3074,11 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) } /** -* @brief Return the UART handle error code. + * @brief Return the UART handle error code. * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. -* @retval UART Error Code -*/ + * the configuration information for the specified UART. + * @retval UART Error Code + */ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) { return huart->ErrorCode; @@ -2887,13 +3126,14 @@ void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - uint32_t tmpreg = 0x00000000U; - UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; - uint16_t brrtemp = 0x0000U; + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; uint32_t usartdiv = 0x00000000U; HAL_StatusTypeDef ret = HAL_OK; PLL3_ClocksTypeDef pll3_clocks; PLL4_ClocksTypeDef pll4_clocks; + uint32_t pclk; /* Check the parameters */ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); @@ -2947,13 +3187,16 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_PCLK5: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK5Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK5Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_PLL3Q: HAL_RCC_GetPLL3ClockFreq(&pll3_clocks); @@ -2972,7 +3215,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) case UART_CLOCKSOURCE_HSE: usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; - case UART_CLOCKSOURCE_UNDEFINED: default: ret = HAL_ERROR; break; @@ -2981,7 +3223,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) /* USARTDIV must be greater than or equal to 0d16 */ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) { - brrtemp = usartdiv & 0xFFF0U; + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); huart->Instance->BRR = brrtemp; } @@ -2995,13 +3237,16 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_PCLK5: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK5Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK5Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_PLL3Q: HAL_RCC_GetPLL3ClockFreq(&pll3_clocks); @@ -3020,7 +3265,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) case UART_CLOCKSOURCE_HSE: usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; - case UART_CLOCKSOURCE_UNDEFINED: default: ret = HAL_ERROR; break; @@ -3129,7 +3373,7 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -3147,6 +3391,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) return HAL_TIMEOUT; } } + /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { @@ -3162,7 +3407,6 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -3177,7 +3421,8 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) @@ -3185,7 +3430,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); @@ -3194,11 +3439,32 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_TIMEOUT; } + + if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } } } return HAL_OK; @@ -3207,7 +3473,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) @@ -3223,7 +3489,7 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) @@ -3354,17 +3620,20 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + /* Stop UART DMA Tx request if ongoing */ - if ((huart->gState == HAL_UART_STATE_BUSY_TX) - && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) { huart->TxXferCount = 0U; UART_EndTxTransfer(huart); } /* Stop UART DMA Rx request if ongoing */ - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) - && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) { huart->RxXferCount = 0U; UART_EndRxTransfer(huart); @@ -3384,7 +3653,7 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA UART communication abort callback, when initiated by HAL services on Error * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. + * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) @@ -3599,7 +3868,6 @@ static void UART_MDMATransmitCplt(MDMA_HandleTypeDef *hmdma) /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } /** @@ -3672,7 +3940,7 @@ static void UART_MDMAError(MDMA_HandleTypeDef *hmdma) /** * @brief MDMA UART communication abort callback, when initiated by HAL services on Error * (To be called at end of MDMA Abort procedure following error occurrence). - * @param hmdma MDMA handle. + * @param hmdma MDMA handle. * @retval None */ static void UART_MDMAAbortOnError(MDMA_HandleTypeDef *hmdma) @@ -3735,10 +4003,8 @@ static void UART_MDMATxAbortCallback(MDMA_HandleTypeDef *hmdma) /* Call legacy weak Abort complete callback */ HAL_UART_AbortCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - /** * @brief MDMA UART Rx communication abort callback, when initiated by user * (To be called at end of MDMA Rx Abort procedure following user abort request). @@ -3843,7 +4109,7 @@ static void UART_MDMARxOnlyAbortCallback(MDMA_HandleTypeDef *hmdma) HAL_UART_AbortReceiveCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } -#endif +#endif /* HAL_MDMA_MODULE_ENABLED */ /** * @brief TX interrrupt handler for 7 or 8 bits data word length . @@ -3857,7 +4123,7 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { - if (huart->TxXferCount == 0) + if (huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); @@ -3867,7 +4133,8 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) } else { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; huart->TxXferCount--; } } @@ -3887,7 +4154,7 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { - if (huart->TxXferCount == 0) + if (huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); @@ -3898,8 +4165,8 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) else { tmp = (uint16_t *) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - huart->pTxBuffPtr += 2; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; huart->TxXferCount--; } } @@ -3914,12 +4181,12 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) */ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { - uint8_t nb_tx_data; + uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { - for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) { if (huart->TxXferCount == 0U) { @@ -3931,11 +4198,16 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) break; /* force exit loop */ } - else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; huart->TxXferCount--; } + else + { + /* Nothing to do */ + } } } } @@ -3950,12 +4222,12 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { uint16_t *tmp; - uint8_t nb_tx_data; + uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { - for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) { if (huart->TxXferCount == 0U) { @@ -3967,20 +4239,24 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) break; /* force exit loop */ } - else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) { tmp = (uint16_t *) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; } + else + { + /* Nothing to do */ + } } } } /** * @brief Wrap up transmission in non-blocking mode. - * @param huart pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -4018,9 +4294,11 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) if (huart->RxState == HAL_UART_STATE_BUSY_RX) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; - if (--huart->RxXferCount == 0) + if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); @@ -4069,9 +4347,10 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) uhdata = (uint16_t) READ_REG(huart->Instance->RDR); tmp = (uint16_t *) huart->pRxBuffPtr ; *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr += 2; + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; - if (--huart->RxXferCount == 0) + if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); @@ -4112,15 +4391,17 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { uint16_t uhMask = huart->Mask; uint16_t uhdata; - uint8_t nb_rx_data; + uint16_t nb_rx_data; + uint16_t rxdatacount; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) { - for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; huart->RxXferCount--; if (huart->RxXferCount == 0U) @@ -4151,7 +4432,8 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ - if (((huart->RxXferCount != 0U)) && (huart->RxXferCount < huart->NbRxDataToProcess)) + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); @@ -4182,17 +4464,18 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) uint16_t *tmp; uint16_t uhMask = huart->Mask; uint16_t uhdata; - uint8_t nb_rx_data; + uint16_t nb_rx_data; + uint16_t rxdatacount; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) { - for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) + for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); tmp = (uint16_t *) huart->pRxBuffPtr ; *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr += 2; + huart->pRxBuffPtr += 2U; huart->RxXferCount--; if (huart->RxXferCount == 0U) @@ -4223,7 +4506,8 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ - if (((huart->RxXferCount != 0U)) && (huart->RxXferCount < huart->NbRxDataToProcess)) + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c index 3ea0f4f9f1..ae8d4790ff 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c @@ -56,11 +56,17 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @defgroup UARTEX_Private_Constants UARTEx Private Constants + * @{ + */ /* UART RX FIFO depth */ #define RX_FIFO_DEPTH 8U /* UART TX FIFO depth */ #define TX_FIFO_DEPTH 8U +/** + * @} + */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -68,9 +74,6 @@ /** @defgroup UARTEx_Private_Functions UARTEx Private Functions * @{ */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -extern void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); /** @@ -160,9 +163,10 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); * oversampling rate). * @retval HAL status */ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) { - uint32_t temp = 0x0U; + uint32_t temp; /* Check the UART handle allocation */ if (huart == NULL) @@ -236,7 +240,6 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, return (UART_CheckIdleState(huart)); } - /** * @} */ @@ -312,7 +315,7 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions * @brief Extended Peripheral Control functions - * + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -324,7 +327,6 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) trigger: address match, Start Bit detection or RXNE bit status. (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode (+) HAL_UARTEx_DisableStopMode() API disables the above functionality - (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold @@ -334,9 +336,6 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) * @{ */ - - - /** * @brief By default in multiprocessor mode, when the wake up method is set * to address mark, the UART handles only 4-bit long addresses detection; @@ -376,7 +375,6 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua return (UART_CheckIdleState(huart)); } - /** * @brief Set Wakeup from Stop mode interrupt flag selection. * @note It is the application responsibility to enable the interrupt used as @@ -392,7 +390,7 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart = 0U; + uint32_t tickstart; /* check the wake-up from stop mode UART instance */ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); @@ -438,7 +436,6 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar return status; } - /** * @brief Enable UART Stop Mode. * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. @@ -485,7 +482,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); @@ -526,7 +523,7 @@ HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); @@ -572,7 +569,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); @@ -621,7 +618,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint3 */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { - uint32_t tmpcr1 = 0U; + uint32_t tmpcr1; /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); @@ -697,8 +694,8 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) uint8_t tx_fifo_depth; uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U}; + uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) { @@ -711,8 +708,8 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) tx_fifo_depth = TX_FIFO_DEPTH; rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - huart->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold]) / denominator[tx_fifo_threshold]; - huart->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold]) / denominator[rx_fifo_threshold]; + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } /** diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_fmc.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_fmc.c new file mode 100644 index 0000000000..aed647ef9e --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_fmc.c @@ -0,0 +1,502 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_ll_fmc.c + * @author MCD Application Team + * @brief FMC Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Flexible Memory Controller (FMC) peripheral memories: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### FMC peripheral features ##### + ============================================================================== + [..] The Flexible memory controller (FMC) includes following memory controllers: + (+) The NOR/PSRAM memory controller + + [..] The FMC functional block makes the interface with synchronous and asynchronous static + memories. Its main purposes are: + (+) to translate AHB transactions into the appropriate external device protocol + (+) to meet the access time requirements of the external memory devices + + [..] All external memories share the addresses, data and control signals with the controller. + Each external device is accessed by means of a unique Chip Select. The FMC performs + only one access at a time to an external device. + The main features of the FMC controller are the following: + (+) Interface with static-memory mapped devices including: + (++) Static random access memory (SRAM) + (++) Read-only memory (ROM) + (++) NOR Flash memory/OneNAND Flash memory + (++) PSRAM (4 memory banks) + (+) Independent Chip Select control for each memory bank + (+) Independent configuration for each memory bank + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_hal.h" + +/** @addtogroup STM32MP1xx_HAL_Driver + * @{ + */ +#if defined HAL_NOR_MODULE_ENABLED || defined HAL_SRAM_MODULE_ENABLED + +/** @defgroup FMC_LL FMC Low Layer + * @brief FMC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants + * @{ + */ + +/* ----------------------- FMC registers bit mask --------------------------- */ + +/* --- BCR Register ---*/ +/* BCR register clear mask */ + +/* --- BTR Register ---*/ +/* BTR register clear mask */ +#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD |\ + FMC_BTR1_DATAST | FMC_BTR1_BUSTURN |\ + FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT |\ + FMC_BTR1_ACCMOD | FMC_BTR1_DATAHLD)) + +/* --- BWTR Register ---*/ +/* BWTR register clear mask */ +#if defined(FMC_BWTR1_BUSTURN) +#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD |\ + FMC_BWTR1_DATAST | FMC_BWTR1_BUSTURN |\ + FMC_BWTR1_ACCMOD | FMC_BWTR1_DATAHLD)) +#else +#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD |\ + FMC_BWTR1_DATAST | FMC_BWTR1_ACCMOD |\ + FMC_BWTR1_DATAHLD)) +#endif /* FMC_BWTR1_BUSTURN */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions + * @{ + */ + + +/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions + * @brief NORSRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use NORSRAM device driver ##### + ============================================================================== + + [..] + This driver contains a set of APIs to interface with the FMC NORSRAM banks in order + to run the NORSRAM external devices. + + (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() + (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() + (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() + (+) FMC NORSRAM bank extended timing configuration using the function + FMC_NORSRAM_Extended_Timing_Init() + (+) FMC NORSRAM bank enable/disable write operation using the functions + FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() + +@endverbatim + * @{ + */ + +/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC NORSRAM interface + (+) De-initialize the FMC NORSRAM interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the FMC_NORSRAM device according to the specified + * control parameters in the FMC_NORSRAM_InitTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Init Pointer to NORSRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init) +{ + uint32_t flashaccess; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); + assert_param(IS_FMC_MUX(Init->DataAddressMux)); + assert_param(IS_FMC_MEMORY(Init->MemoryType)); + assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); + assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); + assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); + assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); + assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); + assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); + assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); + assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); + assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); + assert_param(IS_FMC_PAGESIZE(Init->PageSize)); + assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime)); + assert_param(IS_FUNCTIONAL_STATE(Init->MaxChipSelectPulse)); + + /* Disable NORSRAM Device */ + __FMC_NORSRAM_DISABLE(Device, Init->NSBank); + + /* Set NORSRAM device control parameters */ + if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) + { + flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE; + } + else + { + flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE; + } + + MODIFY_REG(Device->BTCR[Init->NSBank], + (FMC_BCR1_MBKEN | + FMC_BCR1_MUXEN | + FMC_BCR1_MTYP | + FMC_BCR1_MWID | + FMC_BCR1_FACCEN | + FMC_BCR1_BURSTEN | + FMC_BCR1_WAITPOL | + FMC_BCR1_WAITCFG | + FMC_BCR1_WREN | + FMC_BCR1_WAITEN | + FMC_BCR1_EXTMOD | + FMC_BCR1_ASYNCWAIT | + FMC_BCR1_CBURSTRW | + FMC_BCR1_CCLKEN | + FMC_BCR1_NBLSET | + FMC_BCR1_CPSIZE), + (flashaccess | + Init->DataAddressMux | + Init->MemoryType | + Init->MemoryDataWidth | + Init->BurstAccessMode | + Init->WaitSignalPolarity | + Init->WaitSignalActive | + Init->WriteOperation | + Init->WaitSignal | + Init->ExtendedMode | + Init->AsynchronousWait | + Init->WriteBurst | + Init->ContinuousClock | + Init->NBLSetupTime | + Init->PageSize)); + + /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ + if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) + { + MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); + } + + /* Check PSRAM chip select counter state */ + if(Init->MaxChipSelectPulse == ENABLE) + { + /* Check the parameters */ + assert_param(IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(Init->MaxChipSelectPulseTime)); + + /* Configure PSRAM chip select counter value */ + MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime)); + + /* Enable PSRAM chip select counter for the bank */ + switch (Init->NSBank) + { + case FMC_NORSRAM_BANK1 : + SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); + break; + + case FMC_NORSRAM_BANK2 : + SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); + break; + + case FMC_NORSRAM_BANK3 : + SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); + break; + + case FMC_NORSRAM_BANK4 : + SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); + break; + + default : + break; + } + } + + return HAL_OK; +} + +/** + * @brief DeInitialize the FMC_NORSRAM peripheral + * @param Device Pointer to NORSRAM device instance + * @param ExDevice Pointer to NORSRAM extended mode device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Disable the FMC_NORSRAM device */ + __FMC_NORSRAM_DISABLE(Device, Bank); + + /* De-initialize the FMC_NORSRAM device */ + /* FMC_NORSRAM_BANK1 */ + if (Bank == FMC_NORSRAM_BANK1) + { + Device->BTCR[Bank] = 0x000030DBU; + } + /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ + else + { + Device->BTCR[Bank] = 0x000030D2U; + } + + Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; + ExDevice->BWTR[Bank] = 0x000FFFFFU; + + /* De-initialize PSRAM chip select counter */ + switch (Bank) + { + case FMC_NORSRAM_BANK1 : + CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); + break; + + case FMC_NORSRAM_BANK2 : + CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); + break; + + case FMC_NORSRAM_BANK3 : + CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); + break; + + case FMC_NORSRAM_BANK4 : + CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); + break; + + default : + break; + } + + return HAL_OK; +} + +/** + * @brief Initialize the FMC_NORSRAM Timing according to the specified + * parameters in the FMC_NORSRAM_TimingTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpr; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); + assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Set FMC_NORSRAM device timing parameters */ + MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BTR1_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BTR1_DATAST_Pos) | + ((Timing->DataHoldTime) << FMC_BTR1_DATAHLD_Pos) | + ((Timing->BusTurnAroundDuration) << FMC_BTR1_BUSTURN_Pos) | + (((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos) | + (((Timing->DataLatency) - 2U) << FMC_BTR1_DATLAT_Pos) | + (Timing->AccessMode))); + + /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ + if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) + { + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTR1_CLKDIV_Pos)); + tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos); + MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr); + } + + return HAL_OK; +} + +/** + * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified + * parameters in the FMC_NORSRAM_TimingTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number + * @param ExtendedMode FMC Extended Mode + * This parameter can be one of the following values: + * @arg FMC_EXTENDED_MODE_DISABLE + * @arg FMC_EXTENDED_MODE_ENABLE + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) +{ + /* Check the parameters */ + assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE) + { + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); +#if defined(FMC_BWTR1_BUSTURN) + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); +#endif /* FMC_BWTR1_BUSTURN */ + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BWTR1_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BWTR1_DATAST_Pos) | + ((Timing->DataHoldTime) << FMC_BWTR1_DATAHLD_Pos) | +#if defined(FMC_BWTR1_BUSTURN) + Timing->AccessMode | + ((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos))); +#else + Timing->AccessMode)); +#endif /* FMC_BWTR1_BUSTURN */ + } + else + { + Device->BWTR[Bank] = 0x000FFFFFU; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_NORSRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC NORSRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FMC_NORSRAM write operation. + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Enable write operation */ + SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_NORSRAM write operation. + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Disable write operation */ + CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + + + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_NOR_MODULE_ENABLED */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_rtc.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_rtc.c new file mode 100644 index 0000000000..c8e79f1e8f --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_rtc.c @@ -0,0 +1,878 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_ll_rtc.c + * @author MCD Application Team + * @brief RTC LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_ll_rtc.h" +#include "stm32mp1xx_ll_cortex.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32MP1xx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @addtogroup RTC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RTC_LL_Private_Constants + * @{ + */ +/* Default values used for prescaler */ +#define RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU) +#define RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU) + +/* Values used for timeout */ +#define RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */ +#define RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RTC_LL_Private_Macros + * @{ + */ + +#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \ + || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM)) + +#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU) + +#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU) + +#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \ + || ((__VALUE__) == LL_RTC_FORMAT_BCD)) + +#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \ + || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM)) + +#define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U)) +#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U) +#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U) +#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U) + +#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY)) + +#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U)) + +#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \ + || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \ + || ((__VALUE__) == LL_RTC_MONTH_MARCH) \ + || ((__VALUE__) == LL_RTC_MONTH_APRIL) \ + || ((__VALUE__) == LL_RTC_MONTH_MAY) \ + || ((__VALUE__) == LL_RTC_MONTH_JUNE) \ + || ((__VALUE__) == LL_RTC_MONTH_JULY) \ + || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \ + || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \ + || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \ + || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \ + || ((__VALUE__) == LL_RTC_MONTH_DECEMBER)) + +#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) + +#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL)) + +#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL)) + + +#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \ + ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY)) + +#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \ + ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY)) + + +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RTC_LL_EF_Init + * @{ + */ + +/** + * @brief De-Initializes the RTC registers to their default reset values. + * @note This function does not reset the RTC Clock source and RTC Backup Data + * registers. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are de-initialized + * - ERROR: RTC registers are not de-initialized + */ +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) +{ + ErrorStatus status = ERROR; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Reset TR, DR and CR registers */ + WRITE_REG(RTCx->TR, 0x00000000U); + WRITE_REG(RTCx->WUTR, RTC_WUTR_WUT); + WRITE_REG(RTCx->DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + /* Reset All CR bits except CR[2:0] */ + WRITE_REG(RTCx->CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL)); + WRITE_REG(RTCx->PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); + WRITE_REG(RTCx->ALRMAR, 0x00000000U); + WRITE_REG(RTCx->ALRMBR, 0x00000000U); + WRITE_REG(RTCx->SHIFTR, 0x00000000U); + WRITE_REG(RTCx->CALR, 0x00000000U); + WRITE_REG(RTCx->ALRMASSR, 0x00000000U); + WRITE_REG(RTCx->ALRMBSSR, 0x00000000U); + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + /* Wait till the RTC RSF flag is set */ + status = LL_RTC_WaitForSynchro(RTCx); + } + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + /* DeInitialization of the TAMP */ + /* Reset TAMP CR1 and CR2 registers */ + WRITE_REG(TAMP->CR1, 0xFFFF0000U); + WRITE_REG(TAMP->CR2, 0x00000000U); + WRITE_REG(TAMP->SMCR, 0x00000000U); + WRITE_REG(TAMP->FLTCR, 0x00000000U); + WRITE_REG(TAMP->ATCR1, 0x00000000U); + WRITE_REG(TAMP->IER, 0x00000000U); + WRITE_REG(TAMP->SCR, 0xFFFFFFFFU); + WRITE_REG(TAMP->CFGR, 0x00000000U); + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTCx RTC Instance + * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat)); + assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler)); + assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Set Hour Format */ + LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat); + + /* Configure Synchronous and Asynchronous prescaler factor */ + LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler); + LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler); + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_InitTypeDef field to default value. + * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct) +{ + /* Set RTC_InitStruct fields to default values */ + RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR; + RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT; + RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT; +} + +/** + * @brief Set the RTC current time. + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains + * the time configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat)); + } + else + { + RTC_TimeStruct->TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds)); + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat)); + } + else + { + RTC_TimeStruct->TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + } + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds))); + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Check the input parameters format */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours, + RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds); + } + else + { + LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds)); + } + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTC); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) + { + status = LL_RTC_WaitForSynchro(RTCx); + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec). + * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24; + RTC_TimeStruct->Hours = 0U; + RTC_TimeStruct->Minutes = 0U; + RTC_TimeStruct->Seconds = 0U; +} + +/** + * @brief Set the RTC current date. + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * the date configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Day register is configured + * - ERROR: RTC Day register is not configured + */ +ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + + if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U)) + { + RTC_DateStruct->Month = (uint8_t)((uint32_t) RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU; + } + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year)); + assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month)); + assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day)); + } + else + { + assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year))); + assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month))); + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day))); + } + assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Check the input parameters format */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year); + } + else + { + LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day), + __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year)); + } + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTC); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) + { + status = LL_RTC_WaitForSynchro(RTCx); + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00) + * @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY; + RTC_DateStruct->Day = 1U; + RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY; + RTC_DateStruct->Year = 0U; +} + +/** + * @brief Set the RTC Alarm A. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use @ref LL_RTC_ALMA_Disable function). + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ALARMA registers are configured + * - ERROR: ALARMA registers are not configured + */ +ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask)); + assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + } + + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Select weekday selection */ + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + /* Set the date for ALARM */ + LL_RTC_ALMA_DisableWeekday(RTCx); + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + else + { + LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + /* Set the week day for ALARM */ + LL_RTC_ALMA_EnableWeekday(RTCx); + LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + + /* Configure the Alarm register */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours, + RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); + } + else + { + LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds)); + } + /* Set ALARM mask */ + LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask); + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return SUCCESS; +} + +/** + * @brief Set the RTC Alarm B. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (@ref LL_RTC_ALMB_Disable function). + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ALARMB registers are configured + * - ERROR: ALARMB registers are not configured + */ +ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask)); + assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + } + + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Select weekday selection */ + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + /* Set the date for ALARM */ + LL_RTC_ALMB_DisableWeekday(RTCx); + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + else + { + LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + /* Set the week day for ALARM */ + LL_RTC_ALMB_EnableWeekday(RTCx); + LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + + /* Configure the Alarm register */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours, + RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); + } + else + { + LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds)); + } + /* Set ALARM mask */ + LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask); + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / + * Day = 1st day of the month/Mask = all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM; + RTC_AlarmStruct->AlarmTime.Hours = 0U; + RTC_AlarmStruct->AlarmTime.Minutes = 0U; + RTC_AlarmStruct->AlarmTime.Seconds = 0U; + + /* Alarm Day Settings : Day = 1st day of the month */ + RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE; + RTC_AlarmStruct->AlarmDateWeekDay = 1U; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE; +} + +/** + * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / + * Day = 1st day of the month/Mask = all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM; + RTC_AlarmStruct->AlarmTime.Hours = 0U; + RTC_AlarmStruct->AlarmTime.Minutes = 0U; + RTC_AlarmStruct->AlarmTime.Seconds = 0U; + + /* Alarm Day Settings : Day = 1st day of the month */ + RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE; + RTC_AlarmStruct->AlarmDateWeekDay = 1U; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = LL_RTC_ALMB_MASK_NONE; +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; + ErrorStatus status = SUCCESS; + uint32_t tmp; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Check if the Initialization mode is set */ + if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U) + { + /* Set the Initialization mode */ + LL_RTC_EnableInitMode(RTCx); + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + tmp = LL_RTC_IsActiveFlag_INIT(RTCx); + while ((timeout != 0U) && (tmp != 1U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout --; + } + tmp = LL_RTC_IsActiveFlag_INIT(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + } + return status; +} + +/** + * @brief Exit the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC exited from in Init mode + * - ERROR: Not applicable + */ +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx) +{ + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Disable initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + return SUCCESS; +} + +/** + * @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT; + ErrorStatus status = SUCCESS; + uint32_t tmp; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Clear RSF flag */ + LL_RTC_ClearFlag_RS(RTCx); + + /* Wait the registers to be synchronised */ + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + while ((timeout != 0U) && (tmp != 0U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout--; + } + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + + if (status != ERROR) + { + timeout = RTC_SYNCHRO_TIMEOUT; + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + while ((timeout != 0U) && (tmp != 1U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout--; + } + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + } + + return (status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_sdmmc.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_sdmmc.c old mode 100644 new mode 100755 diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_tim.c b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_tim.c index 7186599d20..744b5c2555 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_tim.c +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_tim.c @@ -346,7 +346,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; TIM_InitStruct->Autoreload = 0xFFFFFFFFU; TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; - TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; + TIM_InitStruct->RepetitionCounter = 0x00000000U; } /** diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 592445ec0d..215f28c6c1 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -12,7 +12,7 @@ * STM32L0: 1.10.2 * STM32L1: 1.4.0 * STM32L4: 1.11.0 - * STM32MP1: 1.1.1 + * STM32MP1: 1.2.0 * STM32WB: 1.4.0 Release notes of each STM32YYxx HAL Drivers available here: From e3b5de5783be4082fcda112e6ad010d9de32e9db Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 12 Feb 2020 14:07:37 +0100 Subject: [PATCH 2/6] [MP1] Update STM32MP1xx CMSIS Drivers to v1.2.0 Included in STM32CubeMP1 FW V1.2.0 Signed-off-by: Frederic Pillon --- .../ST/STM32MP1xx/Include/stm32mp151axx_ca7.h | 2148 +- .../ST/STM32MP1xx/Include/stm32mp151axx_cm4.h | 2148 +- .../ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h | 2148 +- .../ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h | 2148 +- .../ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h | 29042 ++++++++++++++ .../ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h | 29008 ++++++++++++++ .../ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h | 29253 ++++++++++++++ .../ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h | 29219 ++++++++++++++ .../ST/STM32MP1xx/Include/stm32mp153axx_ca7.h | 2148 +- .../ST/STM32MP1xx/Include/stm32mp153axx_cm4.h | 2148 +- .../ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h | 2148 +- .../ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h | 2148 +- .../ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h | 30625 +++++++++++++++ .../ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h | 30591 +++++++++++++++ .../ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h | 30836 +++++++++++++++ .../ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h | 30802 +++++++++++++++ .../ST/STM32MP1xx/Include/stm32mp157axx_ca7.h | 2148 +- .../ST/STM32MP1xx/Include/stm32mp157axx_cm4.h | 2148 +- .../ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h | 2148 +- .../ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h | 2148 +- .../ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h | 31873 +++++++++++++++ .../ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h | 31839 +++++++++++++++ .../ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h | 32084 ++++++++++++++++ .../ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h | 32050 +++++++++++++++ .../Device/ST/STM32MP1xx/Include/stm32mp1xx.h | 58 +- .../ST/STM32MP1xx/Include/system_stm32mp1xx.h | 28 +- .../Device/ST/STM32MP1xx/Release_Notes.html | 9 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 28 files changed, 377971 insertions(+), 15124 deletions(-) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h index 0a6821a6c5..9599588563 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -998,22 +982,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1763,6 +1758,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1793,7 +1794,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1811,7 +1812,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1824,7 +1825,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1858,103 +1859,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -1964,7 +1869,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2200,8 +2104,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2211,31 +2114,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -14622,104 +14521,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -14873,220 +14772,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -20755,20 +21057,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -20863,33 +21151,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -20915,7 +21203,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -20939,9 +21226,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -20992,12 +21279,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -21299,9 +21580,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -21342,9 +21620,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -21365,9 +21640,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -21388,9 +21660,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -21478,22 +21755,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -21504,23 +21769,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -21537,124 +21787,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -21678,72 +21852,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© COPYRIGHT(c) 2017 STMicroelectronics
+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -964,22 +948,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1729,6 +1724,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1759,7 +1760,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1777,7 +1778,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1790,7 +1791,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1824,103 +1825,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -1930,7 +1835,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2166,8 +2070,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2177,31 +2080,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -14588,104 +14487,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -14839,220 +14738,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -20721,20 +21023,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -20829,33 +21117,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -20881,7 +21169,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -20905,9 +21192,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -20958,12 +21245,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -21265,9 +21546,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -21308,9 +21586,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -21331,9 +21606,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -21354,9 +21626,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -21444,22 +21721,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -21470,23 +21735,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -21503,124 +21753,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -21644,72 +21818,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© COPYRIGHT(c) 2017 STMicroelectronics
+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -998,22 +982,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1763,6 +1758,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1793,7 +1794,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1811,7 +1812,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1824,7 +1825,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1858,103 +1859,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -1964,7 +1869,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2200,8 +2104,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2211,31 +2114,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -14819,104 +14718,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -15070,220 +14969,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -20964,20 +21266,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -21072,33 +21360,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -21124,7 +21412,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -21148,9 +21435,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -21201,12 +21488,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -21508,9 +21789,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -21551,9 +21829,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -21574,9 +21849,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -21597,9 +21869,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -21687,22 +21964,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -21713,23 +21978,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -21746,124 +21996,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -21887,72 +22061,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© COPYRIGHT(c) 2017 STMicroelectronics
+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -964,22 +948,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1729,6 +1724,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1759,7 +1760,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1777,7 +1778,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1790,7 +1791,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1824,103 +1825,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -1930,7 +1835,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2166,8 +2070,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2177,31 +2080,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -14785,104 +14684,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -15036,220 +14935,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -20930,20 +21232,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -21038,33 +21326,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -21090,7 +21378,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -21114,9 +21401,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -21167,12 +21454,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -21474,9 +21755,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -21517,9 +21795,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -21540,9 +21815,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -21563,9 +21835,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -21653,22 +21930,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -21679,23 +21944,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -21712,124 +21962,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -21853,72 +22027,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp151dxx_ca7 + * @{ + */ + +#ifndef __STM32MP151Dxx_CA7_H +#define __STM32MP151Dxx_CA7_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-A Processor Specific Interrupt Numbers ***************************************************************/ + /* Software Generated Interrupts */ + SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ + SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ + SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ + SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ + SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ + SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ + SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ + SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ + SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ + SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ + SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ + SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ + SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ + SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ + SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ + SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ + /* Private Peripheral Interrupts */ + VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ + Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ + SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ + NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ + Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ + WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_36 = 36, /*!< RESERVED interrupt */ + RCC_IRQn = 37, /*!< RCC global Interrupt */ + EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 40, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 41, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 42, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 43, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 44, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 45, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 46, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 47, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 48, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 49, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 50, /*!< ADC1 global Interrupts */ + RESERVED_51 = 51, /*!< reserved */ + RESERVED_52 = 52, /*!< reserved */ + RESERVED_53 = 53, /*!< reserved */ + RESERVED_54 = 54, /*!< reserved */ + EXTI5_IRQn = 55, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 56, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 57, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 58, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 59, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 60, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 61, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 62, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 63, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 64, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 65, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 66, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 67, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 68, /*!< SPI2 global Interrupt */ + USART1_IRQn = 69, /*!< USART1 global Interrupt */ + USART2_IRQn = 70, /*!< USART2 global Interrupt */ + USART3_IRQn = 71, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 72, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 73, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 74, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 75, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 76, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 77, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 78, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 79, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 80, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 81, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 82, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 83, /*!< SPI3 global Interrupt */ + UART4_IRQn = 84, /*!< UART4 global Interrupt */ + UART5_IRQn = 85, /*!< UART5 global Interrupt */ + TIM6_IRQn = 86, /*!< TIM6 global */ + TIM7_IRQn = 87, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 88, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 89, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 90, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 91, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 92, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 93, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 94, /*!< Ethernet Wakeup through EXTI line Interrupt */ + RESERVED_95 = 95, /*!< reserved */ + EXTI6_IRQn = 96, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 97, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 98, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 99, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 100, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 101, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 102, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 103, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 106, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 107, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 108, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 109, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 110, /*!< DCMI global interrupt */ + RESERVED_111 = 111, /*!< reserved */ + HASH1_IRQn = 112, /*!< Hash global interrupt */ + RESERVED_113 = 113, /*!< reserved */ + UART7_IRQn = 114, /*!< UART7 global interrupt */ + UART8_IRQn = 115, /*!< UART8 global interrupt */ + SPI4_IRQn = 116, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 117, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 118, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 119, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 120, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 121, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 122, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 123, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 124, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 125, /*!< LP TIM1 interrupt */ + CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 127, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 128, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 130, /*!< USB On The Go global interrupt */ + RESERVED_131 = 131, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 132, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 133, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 134, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 135, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 136, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + RESERVED_137 = 137, /*!< reserved */ + HASH2_IRQn = 138, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 139, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 140, /*!< I2C5 Error Interrupt */ + RESERVED_141 = 141, /*!< reserved */ + DFSDM1_FLT0_IRQn = 142, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 143, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 144, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 145, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 146, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 147, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 148, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 149, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 150, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 151, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 152, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 153, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 154, /*!< MDMA global Interrupt */ + RESERVED_155 = 155, /*!< reserved */ + SDMMC2_IRQn = 156, /*!< SDMMC2 global Interrupt */ + HSEM_IT1_IRQn = 157, /*!< HSEM Semaphore Interrupt 1 */ + DFSDM1_FLT5_IRQn = 158, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 159, /*!< EXTI Line 15 Interrupts */ + MDMA_SEC_IT_IRQn = 160, /*!< MDMA global Secure interrupt */ + SYSRESETQ_IRQn = 161, /*!< MCU local Reset Request */ + TIM13_IRQn = 162, /*!< TIM13 global interrupt */ + TIM14_IRQn = 163, /*!< TIM14 global interrupt */ + DAC_IRQn = 164, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 165, /*!< RNG1 interrupt */ + RNG2_IRQn = 166, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 167, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 168, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 169, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 170, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 171, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 172, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 173, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 174, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + WWDG1_RST = 175, /*!< Window Watchdog 1 Reset through AIEC */ + MCU_SEV_IRQn = 176, /*!< MCU Send Event interrupt */ + RCC_WAKEUP_IRQn = 177, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 178, /*!< SAI4 global interrupt */ + DTS_IRQn = 179, /*!< Temperature sensor Global Interrupt */ + RESERVED_180 = 180, /*!< reserved */ + WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins */ + IWDG1_IRQn = 182, /*!< IWDG1 Early Interrupt */ + IWDG2_IRQn = 183, /*!< IWDG2 Early Interrupt */ + TAMP_SERR_S_IRQn = 229, /*!< TAMP Tamper and Security Error Secure interrupts */ + RTC_WKUP_ALARM_S_IRQn = 230, /*!< RTC Wakeup Timer and Alarms (A and B) Secure interrupt */ + RTC_TS_SERR_S_IRQn = 231, /*!< RTC TimeStamp and Security Error Secure interrupt */ + MAX_IRQ_n, + Force_IRQn_enum_size = 1048 /* Dummy entry to ensure IRQn_Type is more than 8 bits. Otherwise GIC init loop would fail */ + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals ============================ */ +#define __CORTEX_A 7U /*!< Cortex-A# Core */ +#define __CA_REV 0x0005U /*!< Core revision r0p0 */ +#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */ +#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */ +#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */ +#define __L2C_PRESENT 0U /*!< Set to 1 if L2C is present */ + +#define GIC_BASE 0xA0021000 +#define GIC_DISTRIBUTOR_BASE GIC_BASE +#define GIC_INTERFACE_BASE (GIC_BASE+0x1000) + +#include "core_ca.h" +#include "system_stm32mp1xx_A7.h" + + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP151Dxx_CA7_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h new file mode 100644 index 0000000000..bda89a8d73 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h @@ -0,0 +1,29008 @@ +/** + ****************************************************************************** + * @file stm32mp151dxx_cm4.h + * @author MCD Application Team + * @brief CMSIS stm32mp151dxx_cm4 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp151dxx_cm4 + * @{ + */ + +#ifndef __STM32MP151Dxx_CM4_H +#define __STM32MP151Dxx_CM4_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-M Processor Exceptions Numbers *******************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers ************************************************************************/ + WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_4 = 4, /*!< RESERVED interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupts */ + RESERVED_19 = 19, /*!< reserved */ + RESERVED_20 = 20, /*!< reserved */ + RESERVED_21 = 21, /*!< reserved */ + RESERVED_22 = 22, /*!< reserved */ + EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + RESERVED_63 = 63, /*!< RESERVED interrupt */ + EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + RESERVED_79 = 79, /*!< RESERVED interrupt */ + HASH1_IRQn = 80, /*!< Hash global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 90, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 98, /*!< USB On The Go global interrupt */ + RESERVED_99 = 99, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + RESERVED_105 = 105, /*!< RESERVED interrupt */ + HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */ + RESERVED_109 = 109, /*!< RESERVED interrupt */ + DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 114, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 119, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 122, /*!< MDMA global Interrupt */ + RESERVED_123 = 123, /*!< RESERVED interrupt */ + SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */ + HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */ + DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */ + nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */ + nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 133, /*!< RNG1 interrupt */ + RNG2_IRQn = 134, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + RESERVED_143 = 143, /*!< RESERVED interrupt */ + MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */ + RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 146, /*!< SAI4 global interrupt */ + DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */ + RESERVED_148 = 148, /*!< RESERVED interrupt */ + WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */ + MAX_IRQ_n + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_stm32mp1xx.h" + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP151Dxx_CM4_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h new file mode 100644 index 0000000000..bbfc353569 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h @@ -0,0 +1,29253 @@ +/** + ****************************************************************************** + * @file stm32mp151fxx_ca7.h + * @author MCD Application Team + * @brief CMSIS stm32mp151fxx_ca7 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp151fxx_ca7 + * @{ + */ + +#ifndef __STM32MP151Fxx_CA7_H +#define __STM32MP151Fxx_CA7_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-A Processor Specific Interrupt Numbers ***************************************************************/ + /* Software Generated Interrupts */ + SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ + SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ + SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ + SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ + SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ + SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ + SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ + SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ + SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ + SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ + SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ + SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ + SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ + SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ + SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ + SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ + /* Private Peripheral Interrupts */ + VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ + Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ + SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ + NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ + Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ + WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_36 = 36, /*!< RESERVED interrupt */ + RCC_IRQn = 37, /*!< RCC global Interrupt */ + EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 40, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 41, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 42, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 43, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 44, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 45, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 46, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 47, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 48, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 49, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 50, /*!< ADC1 global Interrupts */ + RESERVED_51 = 51, /*!< reserved */ + RESERVED_52 = 52, /*!< reserved */ + RESERVED_53 = 53, /*!< reserved */ + RESERVED_54 = 54, /*!< reserved */ + EXTI5_IRQn = 55, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 56, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 57, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 58, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 59, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 60, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 61, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 62, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 63, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 64, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 65, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 66, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 67, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 68, /*!< SPI2 global Interrupt */ + USART1_IRQn = 69, /*!< USART1 global Interrupt */ + USART2_IRQn = 70, /*!< USART2 global Interrupt */ + USART3_IRQn = 71, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 72, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 73, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 74, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 75, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 76, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 77, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 78, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 79, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 80, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 81, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 82, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 83, /*!< SPI3 global Interrupt */ + UART4_IRQn = 84, /*!< UART4 global Interrupt */ + UART5_IRQn = 85, /*!< UART5 global Interrupt */ + TIM6_IRQn = 86, /*!< TIM6 global */ + TIM7_IRQn = 87, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 88, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 89, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 90, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 91, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 92, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 93, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 94, /*!< Ethernet Wakeup through EXTI line Interrupt */ + RESERVED_95 = 95, /*!< reserved */ + EXTI6_IRQn = 96, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 97, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 98, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 99, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 100, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 101, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 102, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 103, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 106, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 107, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 108, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 109, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 110, /*!< DCMI global interrupt */ + CRYP1_IRQn = 111, /*!< CRYP crypto global interrupt */ + HASH1_IRQn = 112, /*!< Hash global interrupt */ + RESERVED_113 = 113, /*!< reserved */ + UART7_IRQn = 114, /*!< UART7 global interrupt */ + UART8_IRQn = 115, /*!< UART8 global interrupt */ + SPI4_IRQn = 116, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 117, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 118, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 119, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 120, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 121, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 122, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 123, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 124, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 125, /*!< LP TIM1 interrupt */ + CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 127, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 128, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 130, /*!< USB On The Go global interrupt */ + RESERVED_131 = 131, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 132, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 133, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 134, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 135, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 136, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + CRYP2_IRQn = 137, /*!< CRYP2 crypto global interrupt */ + HASH2_IRQn = 138, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 139, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 140, /*!< I2C5 Error Interrupt */ + RESERVED_141 = 141, /*!< reserved */ + DFSDM1_FLT0_IRQn = 142, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 143, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 144, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 145, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 146, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 147, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 148, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 149, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 150, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 151, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 152, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 153, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 154, /*!< MDMA global Interrupt */ + RESERVED_155 = 155, /*!< reserved */ + SDMMC2_IRQn = 156, /*!< SDMMC2 global Interrupt */ + HSEM_IT1_IRQn = 157, /*!< HSEM Semaphore Interrupt 1 */ + DFSDM1_FLT5_IRQn = 158, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 159, /*!< EXTI Line 15 Interrupts */ + MDMA_SEC_IT_IRQn = 160, /*!< MDMA global Secure interrupt */ + SYSRESETQ_IRQn = 161, /*!< MCU local Reset Request */ + TIM13_IRQn = 162, /*!< TIM13 global interrupt */ + TIM14_IRQn = 163, /*!< TIM14 global interrupt */ + DAC_IRQn = 164, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 165, /*!< RNG1 interrupt */ + RNG2_IRQn = 166, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 167, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 168, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 169, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 170, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 171, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 172, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 173, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 174, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + WWDG1_RST = 175, /*!< Window Watchdog 1 Reset through AIEC */ + MCU_SEV_IRQn = 176, /*!< MCU Send Event interrupt */ + RCC_WAKEUP_IRQn = 177, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 178, /*!< SAI4 global interrupt */ + DTS_IRQn = 179, /*!< Temperature sensor Global Interrupt */ + RESERVED_180 = 180, /*!< reserved */ + WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins */ + IWDG1_IRQn = 182, /*!< IWDG1 Early Interrupt */ + IWDG2_IRQn = 183, /*!< IWDG2 Early Interrupt */ + TAMP_SERR_S_IRQn = 229, /*!< TAMP Tamper and Security Error Secure interrupts */ + RTC_WKUP_ALARM_S_IRQn = 230, /*!< RTC Wakeup Timer and Alarms (A and B) Secure interrupt */ + RTC_TS_SERR_S_IRQn = 231, /*!< RTC TimeStamp and Security Error Secure interrupt */ + MAX_IRQ_n, + Force_IRQn_enum_size = 1048 /* Dummy entry to ensure IRQn_Type is more than 8 bits. Otherwise GIC init loop would fail */ + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals ============================ */ +#define __CORTEX_A 7U /*!< Cortex-A# Core */ +#define __CA_REV 0x0005U /*!< Core revision r0p0 */ +#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */ +#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */ +#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */ +#define __L2C_PRESENT 0U /*!< Set to 1 if L2C is present */ + +#define GIC_BASE 0xA0021000 +#define GIC_DISTRIBUTOR_BASE GIC_BASE +#define GIC_INTERFACE_BASE (GIC_BASE+0x1000) + +#include "core_ca.h" +#include "system_stm32mp1xx_A7.h" + + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* CRYP VERSION ********************************/ +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP151Fxx_CA7_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h new file mode 100644 index 0000000000..ff110729cb --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h @@ -0,0 +1,29219 @@ +/** + ****************************************************************************** + * @file stm32mp151fxx_cm4.h + * @author MCD Application Team + * @brief CMSIS stm32mp151fxx_cm4 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp151fxx_cm4 + * @{ + */ + +#ifndef __STM32MP151Fxx_CM4_H +#define __STM32MP151Fxx_CM4_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-M Processor Exceptions Numbers *******************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers ************************************************************************/ + WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_4 = 4, /*!< RESERVED interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupts */ + RESERVED_19 = 19, /*!< reserved */ + RESERVED_20 = 20, /*!< reserved */ + RESERVED_21 = 21, /*!< reserved */ + RESERVED_22 = 22, /*!< reserved */ + EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + RESERVED_63 = 63, /*!< RESERVED interrupt */ + EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP1_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH1_IRQn = 80, /*!< Hash global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 90, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 98, /*!< USB On The Go global interrupt */ + RESERVED_99 = 99, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + CRYP2_IRQn = 105, /*!< CRYP2 crypto global interrupt */ + HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */ + RESERVED_109 = 109, /*!< RESERVED interrupt */ + DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 114, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 119, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 122, /*!< MDMA global Interrupt */ + RESERVED_123 = 123, /*!< RESERVED interrupt */ + SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */ + HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */ + DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */ + nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */ + nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 133, /*!< RNG1 interrupt */ + RNG2_IRQn = 134, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + RESERVED_143 = 143, /*!< RESERVED interrupt */ + MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */ + RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 146, /*!< SAI4 global interrupt */ + DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */ + RESERVED_148 = 148, /*!< RESERVED interrupt */ + WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */ + MAX_IRQ_n + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_stm32mp1xx.h" + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* CRYP VERSION ********************************/ +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP151Fxx_CM4_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h index 47fc68e485..96c40248d2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1099,22 +1083,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1864,6 +1859,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1894,7 +1895,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1912,7 +1913,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1925,7 +1926,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1959,103 +1960,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2065,7 +1970,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2301,8 +2205,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2312,31 +2215,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -16186,104 +16085,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -16437,220 +16336,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -22333,20 +22635,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -22441,33 +22729,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -22493,7 +22781,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -22517,9 +22804,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -22570,12 +22857,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -22877,9 +23158,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -22920,9 +23198,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -22943,9 +23218,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -22966,9 +23238,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -23056,22 +23333,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -23082,23 +23347,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -23115,124 +23365,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23256,72 +23430,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
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+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1065,22 +1049,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1830,6 +1825,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1860,7 +1861,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1878,7 +1879,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1891,7 +1892,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1925,103 +1926,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2031,7 +1936,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2267,8 +2171,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2278,31 +2181,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -16152,104 +16051,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -16403,220 +16302,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -22299,20 +22601,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -22407,33 +22695,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -22459,7 +22747,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -22483,9 +22770,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -22536,12 +22823,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -22843,9 +23124,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -22886,9 +23164,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -22909,9 +23184,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -22932,9 +23204,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -23022,22 +23299,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -23048,23 +23313,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -23081,124 +23331,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23222,72 +23396,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© COPYRIGHT(c) 2017 STMicroelectronics
+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1099,22 +1083,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1864,6 +1859,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1894,7 +1895,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1912,7 +1913,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1925,7 +1926,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1959,103 +1960,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2065,7 +1970,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2301,8 +2205,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2312,31 +2215,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -16383,104 +16282,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -16634,220 +16533,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -22542,20 +22844,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -22650,33 +22938,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -22702,7 +22990,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -22726,9 +23013,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -22779,12 +23066,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -23086,9 +23367,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -23129,9 +23407,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -23152,9 +23427,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -23175,9 +23447,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -23265,22 +23542,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -23291,23 +23556,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -23324,124 +23574,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23465,72 +23639,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© COPYRIGHT(c) 2017 STMicroelectronics
+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1065,22 +1049,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1830,6 +1825,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1860,7 +1861,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1878,7 +1879,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1891,7 +1892,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1925,103 +1926,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2031,7 +1936,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2267,8 +2171,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2278,31 +2181,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -16349,104 +16248,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -16600,220 +16499,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -22508,20 +22810,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -22616,33 +22904,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -22668,7 +22956,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -22692,9 +22979,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -22745,12 +23032,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -23052,9 +23333,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -23095,9 +23373,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -23118,9 +23393,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -23141,9 +23413,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -23231,22 +23508,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -23257,23 +23522,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -23290,124 +23540,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23431,72 +23605,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp153dxx_ca7 + * @{ + */ + +#ifndef __STM32MP153Dxx_CA7_H +#define __STM32MP153Dxx_CA7_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-A Processor Specific Interrupt Numbers ***************************************************************/ + /* Software Generated Interrupts */ + SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ + SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ + SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ + SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ + SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ + SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ + SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ + SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ + SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ + SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ + SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ + SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ + SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ + SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ + SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ + SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ + /* Private Peripheral Interrupts */ + VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ + Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ + SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ + NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ + Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ + WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_36 = 36, /*!< RESERVED interrupt */ + RCC_IRQn = 37, /*!< RCC global Interrupt */ + EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 40, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 41, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 42, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 43, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 44, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 45, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 46, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 47, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 48, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 49, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 50, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 51, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 52, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 53, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 54, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 55, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 56, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 57, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 58, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 59, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 60, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 61, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 62, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 63, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 64, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 65, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 66, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 67, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 68, /*!< SPI2 global Interrupt */ + USART1_IRQn = 69, /*!< USART1 global Interrupt */ + USART2_IRQn = 70, /*!< USART2 global Interrupt */ + USART3_IRQn = 71, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 72, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 73, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 74, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 75, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 76, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 77, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 78, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 79, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 80, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 81, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 82, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 83, /*!< SPI3 global Interrupt */ + UART4_IRQn = 84, /*!< UART4 global Interrupt */ + UART5_IRQn = 85, /*!< UART5 global Interrupt */ + TIM6_IRQn = 86, /*!< TIM6 global */ + TIM7_IRQn = 87, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 88, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 89, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 90, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 91, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 92, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 93, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 94, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 95, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 96, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 97, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 98, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 99, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 100, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 101, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 102, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 103, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 106, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 107, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 108, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 109, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 110, /*!< DCMI global interrupt */ + RESERVED_111 = 111, /*!< reserved */ + HASH1_IRQn = 112, /*!< Hash global interrupt */ + RESERVED_113 = 113, /*!< reserved */ + UART7_IRQn = 114, /*!< UART7 global interrupt */ + UART8_IRQn = 115, /*!< UART8 global interrupt */ + SPI4_IRQn = 116, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 117, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 118, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 119, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 120, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 121, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 122, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 123, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 124, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 125, /*!< LP TIM1 interrupt */ + CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 127, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 128, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 130, /*!< USB On The Go global interrupt */ + RESERVED_131 = 131, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 132, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 133, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 134, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 135, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 136, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + RESERVED_137 = 137, /*!< reserved */ + HASH2_IRQn = 138, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 139, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 140, /*!< I2C5 Error Interrupt */ + RESERVED_141 = 141, /*!< reserved */ + DFSDM1_FLT0_IRQn = 142, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 143, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 144, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 145, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 146, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 147, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 148, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 149, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 150, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 151, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 152, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 153, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 154, /*!< MDMA global Interrupt */ + RESERVED_155 = 155, /*!< reserved */ + SDMMC2_IRQn = 156, /*!< SDMMC2 global Interrupt */ + HSEM_IT1_IRQn = 157, /*!< HSEM Semaphore Interrupt 1 */ + DFSDM1_FLT5_IRQn = 158, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 159, /*!< EXTI Line 15 Interrupts */ + MDMA_SEC_IT_IRQn = 160, /*!< MDMA global Secure interrupt */ + SYSRESETQ_IRQn = 161, /*!< MCU local Reset Request */ + TIM13_IRQn = 162, /*!< TIM13 global interrupt */ + TIM14_IRQn = 163, /*!< TIM14 global interrupt */ + DAC_IRQn = 164, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 165, /*!< RNG1 interrupt */ + RNG2_IRQn = 166, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 167, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 168, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 169, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 170, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 171, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 172, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 173, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 174, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + WWDG1_RST = 175, /*!< Window Watchdog 1 Reset through AIEC */ + MCU_SEV_IRQn = 176, /*!< MCU Send Event interrupt */ + RCC_WAKEUP_IRQn = 177, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 178, /*!< SAI4 global interrupt */ + DTS_IRQn = 179, /*!< Temperature sensor Global Interrupt */ + RESERVED_180 = 180, /*!< reserved */ + WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins */ + IWDG1_IRQn = 182, /*!< IWDG1 Early Interrupt */ + IWDG2_IRQn = 183, /*!< IWDG2 Early Interrupt */ + TAMP_SERR_S_IRQn = 229, /*!< TAMP Tamper and Security Error Secure interrupts */ + RTC_WKUP_ALARM_S_IRQn = 230, /*!< RTC Wakeup Timer and Alarms (A and B) Secure interrupt */ + RTC_TS_SERR_S_IRQn = 231, /*!< RTC TimeStamp and Security Error Secure interrupt */ + MAX_IRQ_n, + Force_IRQn_enum_size = 1048 /* Dummy entry to ensure IRQn_Type is more than 8 bits. Otherwise GIC init loop would fail */ + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals ============================ */ +#define __CORTEX_A 7U /*!< Cortex-A# Core */ +#define __CA_REV 0x0005U /*!< Core revision r0p0 */ +#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */ +#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */ +#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */ +#define __L2C_PRESENT 0U /*!< Set to 1 if L2C is present */ + +#define GIC_BASE 0xA0021000 +#define GIC_DISTRIBUTOR_BASE GIC_BASE +#define GIC_INTERFACE_BASE (GIC_BASE+0x1000) + +#include "core_ca.h" +#include "system_stm32mp1xx_A7.h" + + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP153Dxx_CA7_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h new file mode 100644 index 0000000000..a86122ac4f --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h @@ -0,0 +1,30591 @@ +/** + ****************************************************************************** + * @file stm32mp153dxx_cm4.h + * @author MCD Application Team + * @brief CMSIS stm32mp153dxx_cm4 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp153dxx_cm4 + * @{ + */ + +#ifndef __STM32MP153Dxx_CM4_H +#define __STM32MP153Dxx_CM4_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-M Processor Exceptions Numbers *******************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers ************************************************************************/ + WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_4 = 4, /*!< RESERVED interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + RESERVED_79 = 79, /*!< RESERVED interrupt */ + HASH1_IRQn = 80, /*!< Hash global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 90, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 98, /*!< USB On The Go global interrupt */ + RESERVED_99 = 99, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + RESERVED_105 = 105, /*!< RESERVED interrupt */ + HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */ + RESERVED_109 = 109, /*!< RESERVED interrupt */ + DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 114, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 119, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 122, /*!< MDMA global Interrupt */ + RESERVED_123 = 123, /*!< RESERVED interrupt */ + SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */ + HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */ + DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */ + nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */ + nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 133, /*!< RNG1 interrupt */ + RNG2_IRQn = 134, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + RESERVED_143 = 143, /*!< RESERVED interrupt */ + MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */ + RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 146, /*!< SAI4 global interrupt */ + DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */ + RESERVED_148 = 148, /*!< RESERVED interrupt */ + WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */ + MAX_IRQ_n + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_stm32mp1xx.h" + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP153Dxx_CM4_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h new file mode 100644 index 0000000000..8a21736f8a --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h @@ -0,0 +1,30836 @@ +/** + ****************************************************************************** + * @file stm32mp153fxx_ca7.h + * @author MCD Application Team + * @brief CMSIS stm32mp153fxx_ca7 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp153fxx_ca7 + * @{ + */ + +#ifndef __STM32MP153Fxx_CA7_H +#define __STM32MP153Fxx_CA7_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-A Processor Specific Interrupt Numbers ***************************************************************/ + /* Software Generated Interrupts */ + SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ + SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ + SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ + SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ + SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ + SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ + SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ + SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ + SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ + SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ + SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ + SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ + SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ + SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ + SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ + SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ + /* Private Peripheral Interrupts */ + VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ + Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ + SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ + NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ + Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ + WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_36 = 36, /*!< RESERVED interrupt */ + RCC_IRQn = 37, /*!< RCC global Interrupt */ + EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 40, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 41, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 42, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 43, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 44, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 45, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 46, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 47, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 48, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 49, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 50, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 51, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 52, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 53, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 54, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 55, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 56, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 57, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 58, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 59, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 60, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 61, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 62, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 63, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 64, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 65, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 66, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 67, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 68, /*!< SPI2 global Interrupt */ + USART1_IRQn = 69, /*!< USART1 global Interrupt */ + USART2_IRQn = 70, /*!< USART2 global Interrupt */ + USART3_IRQn = 71, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 72, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 73, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 74, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 75, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 76, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 77, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 78, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 79, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 80, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 81, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 82, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 83, /*!< SPI3 global Interrupt */ + UART4_IRQn = 84, /*!< UART4 global Interrupt */ + UART5_IRQn = 85, /*!< UART5 global Interrupt */ + TIM6_IRQn = 86, /*!< TIM6 global */ + TIM7_IRQn = 87, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 88, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 89, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 90, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 91, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 92, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 93, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 94, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 95, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 96, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 97, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 98, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 99, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 100, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 101, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 102, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 103, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 106, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 107, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 108, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 109, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 110, /*!< DCMI global interrupt */ + CRYP1_IRQn = 111, /*!< CRYP crypto global interrupt */ + HASH1_IRQn = 112, /*!< Hash global interrupt */ + RESERVED_113 = 113, /*!< reserved */ + UART7_IRQn = 114, /*!< UART7 global interrupt */ + UART8_IRQn = 115, /*!< UART8 global interrupt */ + SPI4_IRQn = 116, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 117, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 118, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 119, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 120, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 121, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 122, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 123, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 124, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 125, /*!< LP TIM1 interrupt */ + CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 127, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 128, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 130, /*!< USB On The Go global interrupt */ + RESERVED_131 = 131, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 132, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 133, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 134, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 135, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 136, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + CRYP2_IRQn = 137, /*!< CRYP2 crypto global interrupt */ + HASH2_IRQn = 138, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 139, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 140, /*!< I2C5 Error Interrupt */ + RESERVED_141 = 141, /*!< reserved */ + DFSDM1_FLT0_IRQn = 142, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 143, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 144, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 145, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 146, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 147, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 148, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 149, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 150, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 151, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 152, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 153, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 154, /*!< MDMA global Interrupt */ + RESERVED_155 = 155, /*!< reserved */ + SDMMC2_IRQn = 156, /*!< SDMMC2 global Interrupt */ + HSEM_IT1_IRQn = 157, /*!< HSEM Semaphore Interrupt 1 */ + DFSDM1_FLT5_IRQn = 158, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 159, /*!< EXTI Line 15 Interrupts */ + MDMA_SEC_IT_IRQn = 160, /*!< MDMA global Secure interrupt */ + SYSRESETQ_IRQn = 161, /*!< MCU local Reset Request */ + TIM13_IRQn = 162, /*!< TIM13 global interrupt */ + TIM14_IRQn = 163, /*!< TIM14 global interrupt */ + DAC_IRQn = 164, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 165, /*!< RNG1 interrupt */ + RNG2_IRQn = 166, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 167, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 168, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 169, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 170, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 171, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 172, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 173, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 174, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + WWDG1_RST = 175, /*!< Window Watchdog 1 Reset through AIEC */ + MCU_SEV_IRQn = 176, /*!< MCU Send Event interrupt */ + RCC_WAKEUP_IRQn = 177, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 178, /*!< SAI4 global interrupt */ + DTS_IRQn = 179, /*!< Temperature sensor Global Interrupt */ + RESERVED_180 = 180, /*!< reserved */ + WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins */ + IWDG1_IRQn = 182, /*!< IWDG1 Early Interrupt */ + IWDG2_IRQn = 183, /*!< IWDG2 Early Interrupt */ + TAMP_SERR_S_IRQn = 229, /*!< TAMP Tamper and Security Error Secure interrupts */ + RTC_WKUP_ALARM_S_IRQn = 230, /*!< RTC Wakeup Timer and Alarms (A and B) Secure interrupt */ + RTC_TS_SERR_S_IRQn = 231, /*!< RTC TimeStamp and Security Error Secure interrupt */ + MAX_IRQ_n, + Force_IRQn_enum_size = 1048 /* Dummy entry to ensure IRQn_Type is more than 8 bits. Otherwise GIC init loop would fail */ + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals ============================ */ +#define __CORTEX_A 7U /*!< Cortex-A# Core */ +#define __CA_REV 0x0005U /*!< Core revision r0p0 */ +#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */ +#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */ +#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */ +#define __L2C_PRESENT 0U /*!< Set to 1 if L2C is present */ + +#define GIC_BASE 0xA0021000 +#define GIC_DISTRIBUTOR_BASE GIC_BASE +#define GIC_INTERFACE_BASE (GIC_BASE+0x1000) + +#include "core_ca.h" +#include "system_stm32mp1xx_A7.h" + + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* CRYP VERSION ********************************/ +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP153Fxx_CA7_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h new file mode 100644 index 0000000000..38af1becd2 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h @@ -0,0 +1,30802 @@ +/** + ****************************************************************************** + * @file stm32mp153fxx_cm4.h + * @author MCD Application Team + * @brief CMSIS stm32mp153fxx_cm4 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp153fxx_cm4 + * @{ + */ + +#ifndef __STM32MP153Fxx_CM4_H +#define __STM32MP153Fxx_CM4_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-M Processor Exceptions Numbers *******************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers ************************************************************************/ + WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_4 = 4, /*!< RESERVED interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP1_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH1_IRQn = 80, /*!< Hash global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 90, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 98, /*!< USB On The Go global interrupt */ + RESERVED_99 = 99, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + CRYP2_IRQn = 105, /*!< CRYP2 crypto global interrupt */ + HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */ + RESERVED_109 = 109, /*!< RESERVED interrupt */ + DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 114, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 119, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 122, /*!< MDMA global Interrupt */ + RESERVED_123 = 123, /*!< RESERVED interrupt */ + SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */ + HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */ + DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */ + nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */ + nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 133, /*!< RNG1 interrupt */ + RNG2_IRQn = 134, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + RESERVED_143 = 143, /*!< RESERVED interrupt */ + MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */ + RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 146, /*!< SAI4 global interrupt */ + DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */ + RESERVED_148 = 148, /*!< RESERVED interrupt */ + WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */ + MAX_IRQ_n + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_stm32mp1xx.h" + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* CRYP VERSION ********************************/ +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP153Fxx_CM4_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h index 6f489622a8..45f2fc4739 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1186,22 +1170,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1951,6 +1946,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1981,7 +1982,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1999,7 +2000,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -2012,7 +2013,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -2046,103 +2047,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2152,7 +2057,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2388,8 +2292,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2399,31 +2302,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -17411,104 +17310,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -17662,220 +17561,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -23579,20 +23881,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -23687,33 +23975,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -23739,7 +24027,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -23763,9 +24050,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -23816,12 +24103,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -24123,9 +24404,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -24166,9 +24444,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -24189,9 +24464,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -24212,9 +24484,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -24302,22 +24579,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -24328,23 +24593,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -24361,124 +24611,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24502,72 +24676,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© COPYRIGHT(c) 2017 STMicroelectronics
+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1152,22 +1136,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1917,6 +1912,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1947,7 +1948,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1965,7 +1966,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1978,7 +1979,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -2012,103 +2013,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2118,7 +2023,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2354,8 +2258,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2365,31 +2268,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -17377,104 +17276,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -17628,220 +17527,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -23545,20 +23847,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -23653,33 +23941,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -23705,7 +23993,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -23729,9 +24016,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -23782,12 +24069,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -24089,9 +24370,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -24132,9 +24410,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -24155,9 +24430,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -24178,9 +24450,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -24268,22 +24545,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -24294,23 +24559,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -24327,124 +24577,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24468,72 +24642,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
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+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1186,22 +1170,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1951,6 +1946,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1981,7 +1982,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1999,7 +2000,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -2012,7 +2013,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -2046,103 +2047,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2152,7 +2057,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2388,8 +2292,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2399,31 +2302,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -17608,104 +17507,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -17859,220 +17758,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -23788,20 +24090,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -23896,33 +24184,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -23948,7 +24236,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -23972,9 +24259,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -24025,12 +24312,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -24332,9 +24613,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -24375,9 +24653,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -24398,9 +24673,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -24421,9 +24693,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -24511,22 +24788,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -24537,23 +24802,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -24570,124 +24820,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24711,72 +24885,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© COPYRIGHT(c) 2017 STMicroelectronics
+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1152,22 +1136,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1917,6 +1912,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1947,7 +1948,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1965,7 +1966,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1978,7 +1979,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -2012,103 +2013,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2118,7 +2023,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2354,8 +2258,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2365,31 +2268,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -17574,104 +17473,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -17825,220 +17724,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -23754,20 +24056,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -23862,33 +24150,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -23914,7 +24202,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -23938,9 +24225,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -23991,12 +24278,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -24298,9 +24579,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -24341,9 +24619,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -24364,9 +24639,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -24387,9 +24659,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -24477,22 +24754,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -24503,23 +24768,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -24536,124 +24786,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24677,72 +24851,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp157dxx_ca7 + * @{ + */ + +#ifndef __STM32MP157Dxx_CA7_H +#define __STM32MP157Dxx_CA7_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-A Processor Specific Interrupt Numbers ***************************************************************/ + /* Software Generated Interrupts */ + SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ + SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ + SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ + SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ + SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ + SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ + SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ + SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ + SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ + SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ + SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ + SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ + SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ + SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ + SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ + SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ + /* Private Peripheral Interrupts */ + VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ + Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ + SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ + NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ + Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ + WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_36 = 36, /*!< RESERVED interrupt */ + RCC_IRQn = 37, /*!< RCC global Interrupt */ + EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 40, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 41, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 42, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 43, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 44, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 45, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 46, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 47, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 48, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 49, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 50, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 51, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 52, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 53, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 54, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 55, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 56, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 57, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 58, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 59, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 60, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 61, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 62, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 63, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 64, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 65, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 66, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 67, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 68, /*!< SPI2 global Interrupt */ + USART1_IRQn = 69, /*!< USART1 global Interrupt */ + USART2_IRQn = 70, /*!< USART2 global Interrupt */ + USART3_IRQn = 71, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 72, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 73, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 74, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 75, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 76, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 77, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 78, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 79, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 80, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 81, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 82, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 83, /*!< SPI3 global Interrupt */ + UART4_IRQn = 84, /*!< UART4 global Interrupt */ + UART5_IRQn = 85, /*!< UART5 global Interrupt */ + TIM6_IRQn = 86, /*!< TIM6 global */ + TIM7_IRQn = 87, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 88, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 89, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 90, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 91, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 92, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 93, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 94, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 95, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 96, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 97, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 98, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 99, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 100, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 101, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 102, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 103, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 106, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 107, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 108, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 109, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 110, /*!< DCMI global interrupt */ + RESERVED_111 = 111, /*!< reserved */ + HASH1_IRQn = 112, /*!< Hash global interrupt */ + RESERVED_113 = 113, /*!< reserved */ + UART7_IRQn = 114, /*!< UART7 global interrupt */ + UART8_IRQn = 115, /*!< UART8 global interrupt */ + SPI4_IRQn = 116, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 117, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 118, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 119, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 120, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 121, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 122, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 123, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 124, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 125, /*!< LP TIM1 interrupt */ + CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 127, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 128, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 130, /*!< USB On The Go global interrupt */ + RESERVED_131 = 131, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 132, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 133, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 134, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 135, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 136, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + RESERVED_137 = 137, /*!< reserved */ + HASH2_IRQn = 138, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 139, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 140, /*!< I2C5 Error Interrupt */ + GPU_IRQn = 141, /*!< GPU global Interrupt */ + DFSDM1_FLT0_IRQn = 142, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 143, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 144, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 145, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 146, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 147, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 148, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 149, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 150, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 151, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 152, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 153, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 154, /*!< MDMA global Interrupt */ + DSI_IRQn = 155, /*!< DSI global Interrupt */ + SDMMC2_IRQn = 156, /*!< SDMMC2 global Interrupt */ + HSEM_IT1_IRQn = 157, /*!< HSEM Semaphore Interrupt 1 */ + DFSDM1_FLT5_IRQn = 158, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 159, /*!< EXTI Line 15 Interrupts */ + MDMA_SEC_IT_IRQn = 160, /*!< MDMA global Secure interrupt */ + SYSRESETQ_IRQn = 161, /*!< MCU local Reset Request */ + TIM13_IRQn = 162, /*!< TIM13 global interrupt */ + TIM14_IRQn = 163, /*!< TIM14 global interrupt */ + DAC_IRQn = 164, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 165, /*!< RNG1 interrupt */ + RNG2_IRQn = 166, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 167, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 168, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 169, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 170, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 171, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 172, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 173, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 174, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + WWDG1_RST = 175, /*!< Window Watchdog 1 Reset through AIEC */ + MCU_SEV_IRQn = 176, /*!< MCU Send Event interrupt */ + RCC_WAKEUP_IRQn = 177, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 178, /*!< SAI4 global interrupt */ + DTS_IRQn = 179, /*!< Temperature sensor Global Interrupt */ + RESERVED_180 = 180, /*!< reserved */ + WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins */ + IWDG1_IRQn = 182, /*!< IWDG1 Early Interrupt */ + IWDG2_IRQn = 183, /*!< IWDG2 Early Interrupt */ + TAMP_SERR_S_IRQn = 229, /*!< TAMP Tamper and Security Error Secure interrupts */ + RTC_WKUP_ALARM_S_IRQn = 230, /*!< RTC Wakeup Timer and Alarms (A and B) Secure interrupt */ + RTC_TS_SERR_S_IRQn = 231, /*!< RTC TimeStamp and Security Error Secure interrupt */ + MAX_IRQ_n, + Force_IRQn_enum_size = 1048 /* Dummy entry to ensure IRQn_Type is more than 8 bits. Otherwise GIC init loop would fail */ + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals ============================ */ +#define __CORTEX_A 7U /*!< Cortex-A# Core */ +#define __CA_REV 0x0005U /*!< Core revision r0p0 */ +#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */ +#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */ +#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */ +#define __L2C_PRESENT 0U /*!< Set to 1 if L2C is present */ + +#define GIC_BASE 0xA0021000 +#define GIC_DISTRIBUTOR_BASE GIC_BASE +#define GIC_INTERFACE_BASE (GIC_BASE+0x1000) + +#include "core_ca.h" +#include "system_stm32mp1xx_A7.h" + + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DSI Controller + */ + +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED3[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED4[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED6; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED8[11]; /*!< Reserved, 0x164 - 0x18F */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + uint32_t RESERVED9[155]; /*!< Reserved, 0x194 - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED10; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[2]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-41C */ + uint32_t RESERVED11[4]; /*!< Reserved, 0x420 - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t RESERVED12[239]; /*!< Reserved, 0x434 - 0x7EC */ + __IO uint32_t HWCFGR; /*!< DSI Host hardware configuration register, Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DSI Host version register, Address offset: 0x7F4 */ + __IO uint32_t IPIDR; /*!< DSI Host Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DSI Host Size ID register, Address offset: 0x7FC */ +} DSI_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* DSI VERSION ********************************/ +#define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP157Dxx_CA7_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h new file mode 100644 index 0000000000..738f3c8712 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h @@ -0,0 +1,31839 @@ +/** + ****************************************************************************** + * @file stm32mp157dxx_cm4.h + * @author MCD Application Team + * @brief CMSIS stm32mp157dxx_cm4 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp157dxx_cm4 + * @{ + */ + +#ifndef __STM32MP157Dxx_CM4_H +#define __STM32MP157Dxx_CM4_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-M Processor Exceptions Numbers *******************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers ************************************************************************/ + WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_4 = 4, /*!< RESERVED interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + RESERVED_79 = 79, /*!< RESERVED interrupt */ + HASH1_IRQn = 80, /*!< Hash global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 90, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 98, /*!< USB On The Go global interrupt */ + RESERVED_99 = 99, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + RESERVED_105 = 105, /*!< RESERVED interrupt */ + HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */ + GPU_IRQn = 109, /*!< GPU global Interrupt */ + DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 114, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 119, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 122, /*!< MDMA global Interrupt */ + DSI_IRQn = 123, /*!< DSI global Interrupt */ + SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */ + HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */ + DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */ + nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */ + nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 133, /*!< RNG1 interrupt */ + RNG2_IRQn = 134, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + RESERVED_143 = 143, /*!< RESERVED interrupt */ + MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */ + RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 146, /*!< SAI4 global interrupt */ + DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */ + RESERVED_148 = 148, /*!< RESERVED interrupt */ + WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */ + MAX_IRQ_n + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_stm32mp1xx.h" + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DSI Controller + */ + +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED3[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED4[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED6; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED8[11]; /*!< Reserved, 0x164 - 0x18F */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + uint32_t RESERVED9[155]; /*!< Reserved, 0x194 - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED10; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[2]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-41C */ + uint32_t RESERVED11[4]; /*!< Reserved, 0x420 - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t RESERVED12[239]; /*!< Reserved, 0x434 - 0x7EC */ + __IO uint32_t HWCFGR; /*!< DSI Host hardware configuration register, Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DSI Host version register, Address offset: 0x7F4 */ + __IO uint32_t IPIDR; /*!< DSI Host Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DSI Host Size ID register, Address offset: 0x7FC */ +} DSI_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* DSI VERSION ********************************/ +#define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP157Dxx_CM4_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h new file mode 100644 index 0000000000..60ae69a3f1 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h @@ -0,0 +1,32084 @@ +/** + ****************************************************************************** + * @file stm32mp157fxx_ca7.h + * @author MCD Application Team + * @brief CMSIS stm32mp157fxx_ca7 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp157fxx_ca7 + * @{ + */ + +#ifndef __STM32MP157Fxx_CA7_H +#define __STM32MP157Fxx_CA7_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-A Processor Specific Interrupt Numbers ***************************************************************/ + /* Software Generated Interrupts */ + SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ + SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ + SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ + SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ + SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ + SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ + SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ + SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ + SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ + SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ + SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ + SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ + SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ + SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ + SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ + SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ + /* Private Peripheral Interrupts */ + VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ + Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ + SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ + NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ + Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ + WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_36 = 36, /*!< RESERVED interrupt */ + RCC_IRQn = 37, /*!< RCC global Interrupt */ + EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 40, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 41, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 42, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 43, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 44, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 45, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 46, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 47, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 48, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 49, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 50, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 51, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 52, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 53, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 54, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 55, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 56, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 57, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 58, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 59, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 60, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 61, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 62, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 63, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 64, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 65, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 66, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 67, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 68, /*!< SPI2 global Interrupt */ + USART1_IRQn = 69, /*!< USART1 global Interrupt */ + USART2_IRQn = 70, /*!< USART2 global Interrupt */ + USART3_IRQn = 71, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 72, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 73, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 74, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 75, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 76, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 77, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 78, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 79, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 80, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 81, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 82, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 83, /*!< SPI3 global Interrupt */ + UART4_IRQn = 84, /*!< UART4 global Interrupt */ + UART5_IRQn = 85, /*!< UART5 global Interrupt */ + TIM6_IRQn = 86, /*!< TIM6 global */ + TIM7_IRQn = 87, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 88, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 89, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 90, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 91, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 92, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 93, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 94, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 95, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 96, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 97, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 98, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 99, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 100, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 101, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 102, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 103, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 106, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 107, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 108, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 109, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 110, /*!< DCMI global interrupt */ + CRYP1_IRQn = 111, /*!< CRYP crypto global interrupt */ + HASH1_IRQn = 112, /*!< Hash global interrupt */ + RESERVED_113 = 113, /*!< reserved */ + UART7_IRQn = 114, /*!< UART7 global interrupt */ + UART8_IRQn = 115, /*!< UART8 global interrupt */ + SPI4_IRQn = 116, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 117, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 118, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 119, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 120, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 121, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 122, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 123, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 124, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 125, /*!< LP TIM1 interrupt */ + CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 127, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 128, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 130, /*!< USB On The Go global interrupt */ + RESERVED_131 = 131, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 132, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 133, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 134, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 135, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 136, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + CRYP2_IRQn = 137, /*!< CRYP2 crypto global interrupt */ + HASH2_IRQn = 138, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 139, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 140, /*!< I2C5 Error Interrupt */ + GPU_IRQn = 141, /*!< GPU global Interrupt */ + DFSDM1_FLT0_IRQn = 142, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 143, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 144, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 145, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 146, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 147, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 148, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 149, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 150, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 151, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 152, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 153, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 154, /*!< MDMA global Interrupt */ + DSI_IRQn = 155, /*!< DSI global Interrupt */ + SDMMC2_IRQn = 156, /*!< SDMMC2 global Interrupt */ + HSEM_IT1_IRQn = 157, /*!< HSEM Semaphore Interrupt 1 */ + DFSDM1_FLT5_IRQn = 158, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 159, /*!< EXTI Line 15 Interrupts */ + MDMA_SEC_IT_IRQn = 160, /*!< MDMA global Secure interrupt */ + SYSRESETQ_IRQn = 161, /*!< MCU local Reset Request */ + TIM13_IRQn = 162, /*!< TIM13 global interrupt */ + TIM14_IRQn = 163, /*!< TIM14 global interrupt */ + DAC_IRQn = 164, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 165, /*!< RNG1 interrupt */ + RNG2_IRQn = 166, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 167, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 168, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 169, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 170, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 171, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 172, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 173, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 174, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + WWDG1_RST = 175, /*!< Window Watchdog 1 Reset through AIEC */ + MCU_SEV_IRQn = 176, /*!< MCU Send Event interrupt */ + RCC_WAKEUP_IRQn = 177, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 178, /*!< SAI4 global interrupt */ + DTS_IRQn = 179, /*!< Temperature sensor Global Interrupt */ + RESERVED_180 = 180, /*!< reserved */ + WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins */ + IWDG1_IRQn = 182, /*!< IWDG1 Early Interrupt */ + IWDG2_IRQn = 183, /*!< IWDG2 Early Interrupt */ + TAMP_SERR_S_IRQn = 229, /*!< TAMP Tamper and Security Error Secure interrupts */ + RTC_WKUP_ALARM_S_IRQn = 230, /*!< RTC Wakeup Timer and Alarms (A and B) Secure interrupt */ + RTC_TS_SERR_S_IRQn = 231, /*!< RTC TimeStamp and Security Error Secure interrupt */ + MAX_IRQ_n, + Force_IRQn_enum_size = 1048 /* Dummy entry to ensure IRQn_Type is more than 8 bits. Otherwise GIC init loop would fail */ + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals ============================ */ +#define __CORTEX_A 7U /*!< Cortex-A# Core */ +#define __CA_REV 0x0005U /*!< Core revision r0p0 */ +#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */ +#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */ +#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */ +#define __L2C_PRESENT 0U /*!< Set to 1 if L2C is present */ + +#define GIC_BASE 0xA0021000 +#define GIC_DISTRIBUTOR_BASE GIC_BASE +#define GIC_INTERFACE_BASE (GIC_BASE+0x1000) + +#include "core_ca.h" +#include "system_stm32mp1xx_A7.h" + + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DSI Controller + */ + +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED3[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED4[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED6; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED8[11]; /*!< Reserved, 0x164 - 0x18F */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + uint32_t RESERVED9[155]; /*!< Reserved, 0x194 - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED10; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[2]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-41C */ + uint32_t RESERVED11[4]; /*!< Reserved, 0x420 - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t RESERVED12[239]; /*!< Reserved, 0x434 - 0x7EC */ + __IO uint32_t HWCFGR; /*!< DSI Host hardware configuration register, Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DSI Host version register, Address offset: 0x7F4 */ + __IO uint32_t IPIDR; /*!< DSI Host Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DSI Host Size ID register, Address offset: 0x7FC */ +} DSI_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* CRYP VERSION ********************************/ +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* DSI VERSION ********************************/ +#define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP157Fxx_CA7_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h new file mode 100644 index 0000000000..7e58d59ec3 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h @@ -0,0 +1,32050 @@ +/** + ****************************************************************************** + * @file stm32mp157fxx_cm4.h + * @author MCD Application Team + * @brief CMSIS stm32mp157fxx_cm4 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp157fxx_cm4 + * @{ + */ + +#ifndef __STM32MP157Fxx_CM4_H +#define __STM32MP157Fxx_CM4_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-M Processor Exceptions Numbers *******************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers ************************************************************************/ + WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_4 = 4, /*!< RESERVED interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP1_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH1_IRQn = 80, /*!< Hash global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 90, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 98, /*!< USB On The Go global interrupt */ + RESERVED_99 = 99, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + CRYP2_IRQn = 105, /*!< CRYP2 crypto global interrupt */ + HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */ + GPU_IRQn = 109, /*!< GPU global Interrupt */ + DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 114, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 119, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 122, /*!< MDMA global Interrupt */ + DSI_IRQn = 123, /*!< DSI global Interrupt */ + SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */ + HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */ + DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */ + nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */ + nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 133, /*!< RNG1 interrupt */ + RNG2_IRQn = 134, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + RESERVED_143 = 143, /*!< RESERVED interrupt */ + MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */ + RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 146, /*!< SAI4 global interrupt */ + DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */ + RESERVED_148 = 148, /*!< RESERVED interrupt */ + WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */ + MAX_IRQ_n + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_stm32mp1xx.h" + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DSI Controller + */ + +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED3[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED4[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED6; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED8[11]; /*!< Reserved, 0x164 - 0x18F */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + uint32_t RESERVED9[155]; /*!< Reserved, 0x194 - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED10; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[2]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-41C */ + uint32_t RESERVED11[4]; /*!< Reserved, 0x420 - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t RESERVED12[239]; /*!< Reserved, 0x434 - 0x7EC */ + __IO uint32_t HWCFGR; /*!< DSI Host hardware configuration register, Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DSI Host version register, Address offset: 0x7F4 */ + __IO uint32_t IPIDR; /*!< DSI Host Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DSI Host Size ID register, Address offset: 0x7FC */ +} DSI_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* CRYP VERSION ********************************/ +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* DSI VERSION ********************************/ +#define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP157Fxx_CM4_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h index 528b9b91c3..e42480693f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h @@ -8,37 +8,21 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32MP1xx device used in the target application - * - To use or not the peripheral�s drivers in application code(i.e. - * code will be based on direct access to peripheral�s registers + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -86,7 +70,7 @@ * @brief CMSIS Device version number */ #define __STM32MP1xx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32MP1xx_CMSIS_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32MP1xx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ #define __STM32MP1xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32MP1xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32MP1xx_CMSIS_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ @@ -108,14 +92,26 @@ #include "stm32mp157axx_cm4.h" #elif defined(STM32MP157Cxx) #include "stm32mp157cxx_cm4.h" +#elif defined(STM32MP157Dxx) + #include "stm32mp157dxx_cm4.h" +#elif defined(STM32MP157Fxx) + #include "stm32mp157fxx_cm4.h" #elif defined(STM32MP153Axx) #include "stm32mp153axx_cm4.h" #elif defined(STM32MP153Cxx) #include "stm32mp153cxx_cm4.h" +#elif defined(STM32MP153Dxx) + #include "stm32mp153dxx_cm4.h" +#elif defined(STM32MP153Fxx) + #include "stm32mp153fxx_cm4.h" #elif defined(STM32MP151Axx) #include "stm32mp151axx_cm4.h" #elif defined(STM32MP151Cxx) #include "stm32mp151cxx_cm4.h" +#elif defined(STM32MP151Dxx) + #include "stm32mp151dxx_cm4.h" +#elif defined(STM32MP151Fxx) + #include "stm32mp151fxx_cm4.h" #else #error "Please select first the target STM32MP1xx device used in your application (in stm32mp1xx.h file)" #endif @@ -128,14 +124,26 @@ #include "stm32mp157axx_ca7.h" #elif defined(STM32MP157Cxx) #include "stm32mp157cxx_ca7.h" +#elif defined(STM32MP157Dxx) + #include "stm32mp157dxx_ca7.h" +#elif defined(STM32MP157Fxx) + #include "stm32mp157fxx_ca7.h" #elif defined(STM32MP153Axx) #include "stm32mp153axx_ca7.h" #elif defined(STM32MP153Cxx) #include "stm32mp153cxx_ca7.h" +#elif defined(STM32MP153Dxx) + #include "stm32mp153dxx_ca7.h" +#elif defined(STM32MP153Fxx) + #include "stm32mp153fxx_ca7.h" #elif defined(STM32MP151Axx) #include "stm32mp151axx_ca7.h" #elif defined(STM32MP151Cxx) #include "stm32mp151cxx_ca7.h" +#elif defined(STM32MP151Dxx) + #include "stm32mp151dxx_ca7.h" +#elif defined(STM32MP151Fxx) + #include "stm32mp151fxx_ca7.h" #else #error "Please select first the target STM32MP1xx device used in your application (in stm32mp1xx.h file)" #endif diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h index e9e849fc35..7d22efc319 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html index b848f38881..70a7bf7f9d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html @@ -163,15 +163,16 @@

License

-

V1.1.1 / 14-November-2019

+

V1.2.0 / 03-Feb-2020

-

Main changes

  • Patch release to fix known defects 
    • Align Header file with TIM driver ( Break Source definition)
    • Update Linker Template file to define OpenAMP region ( for EWARM and MDK_ARM)
+

Main changes

+
  • Header files: 
    • Add new Part Number for 800MHz
    • Update license with BSD 3-Clause template
    • Rework CMSIS for RTC/TAMP, GPIO and TIM
    • Rename TIM Break source bit definition
  • Update Linker Template file for KEIL and IAR:
    • Add OpenAMP region ( region present by default, to comment if needed )

Contents

    -
  • CMSIS devices files for STM32MP151Cxx ,STM32MP151Axx, STM32MP153Cxx, STM32MP153Axx, STM32MP157Cxx ,STM32MP157Axx
    +
  • CMSIS devices files for:
    • STM32MP151Cxx ,STM32MP151Axx, STM32MP151Dxx ,STM32MP151Fxx
    • STM32MP153Cxx ,STM32MP153Axx, STM32MP153Dxx ,STM32MP153Fxx
    • STM32MP157Cxx ,STM32MP157Axx, STM32MP157Dxx ,STM32MP157Fxx
@@ -180,7 +181,7 @@

Contents