diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll.h b/cores/arduino/stm32/LL/stm32yyxx_ll.h index 432af97d92..c60b1b8771 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll.h @@ -16,8 +16,8 @@ #include "stm32yyxx_ll_crs.h" #include "stm32yyxx_ll_dac.h" #include "stm32yyxx_ll_delayblock.h" -#include "stm32yyxx_ll_dma.h" #include "stm32yyxx_ll_dma2d.h" +#include "stm32yyxx_ll_dma.h" #include "stm32yyxx_ll_dmamux.h" #include "stm32yyxx_ll_exti.h" #include "stm32yyxx_ll_fmac.h" diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_cortex.h b/cores/arduino/stm32/LL/stm32yyxx_ll_cortex.h index 8f044ca5a2..ffdc5f97f1 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_cortex.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_cortex.h @@ -41,6 +41,9 @@ #ifdef STM32L4xx #include "stm32l4xx_ll_cortex.h" #endif +#ifdef STM32MP1xx +#include "stm32mp1xx_ll_cortex.h" +#endif #ifdef STM32WBxx #include "stm32wbxx_ll_cortex.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_fmc.h b/cores/arduino/stm32/LL/stm32yyxx_ll_fmc.h index 7911d11004..0053a7fe32 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_fmc.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_fmc.h @@ -23,5 +23,8 @@ #ifdef STM32L4xx #include "stm32l4xx_ll_fmc.h" #endif +#ifdef STM32MP1xx +#include "stm32mp1xx_ll_fmc.h" +#endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_FMC_H_ */ diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_rtc.h b/cores/arduino/stm32/LL/stm32yyxx_ll_rtc.h index 1cabae4e7b..bca606afc7 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_rtc.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_rtc.h @@ -41,6 +41,9 @@ #ifdef STM32L4xx #include "stm32l4xx_ll_rtc.h" #endif +#ifdef STM32MP1xx +#include "stm32mp1xx_ll_rtc.h" +#endif #ifdef STM32WBxx #include "stm32wbxx_ll_rtc.h" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c index def659b1b7..5bfdd69875 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c @@ -34,6 +34,9 @@ #ifdef STM32L4xx #include "stm32l4xx_hal_rtc.c" #endif +#ifdef STM32MP1xx +#include "stm32mp1xx_hal_rtc.c" +#endif #ifdef STM32WBxx #include "stm32wbxx_hal_rtc.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c index 73e7008ca5..6109308498 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c @@ -34,6 +34,9 @@ #ifdef STM32L4xx #include "stm32l4xx_hal_rtc_ex.c" #endif +#ifdef STM32MP1xx +#include "stm32mp1xx_hal_rtc_ex.c" +#endif #ifdef STM32WBxx #include "stm32wbxx_hal_rtc_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sram.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sram.c index 54215b5881..1d076e3d78 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sram.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sram.c @@ -25,3 +25,6 @@ #ifdef STM32L4xx #include "stm32l4xx_hal_sram.c" #endif +#ifdef STM32MP1xx +#include "stm32mp1xx_hal_sram.c" +#endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_fmc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_fmc.c index ac46630377..c3fd5cc92a 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_fmc.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_fmc.c @@ -16,3 +16,6 @@ #ifdef STM32L4xx #include "stm32l4xx_ll_fmc.c" #endif +#ifdef STM32MP1xx +#include "stm32mp1xx_ll_fmc.c" +#endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c index ab6ebe15ec..b8b062efc2 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c @@ -34,6 +34,9 @@ #ifdef STM32L4xx #include "stm32l4xx_ll_rtc.c" #endif +#ifdef STM32MP1xx +#include "stm32mp1xx_ll_rtc.c" +#endif #ifdef STM32WBxx #include "stm32wbxx_ll_rtc.c" #endif diff --git a/libraries/SrcWrapper/src/stm32/clock.c b/libraries/SrcWrapper/src/stm32/clock.c index bf99493283..bea7adcdbc 100644 --- a/libraries/SrcWrapper/src/stm32/clock.c +++ b/libraries/SrcWrapper/src/stm32/clock.c @@ -43,16 +43,6 @@ extern "C" { #endif -#if defined(STM32MP1xx) -#include "stm32mp1xx_hal.h" -/* STM32MP1xx does not have own stm32mp1xx_ll_cortex.h so define functions manually. - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) -{ - return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); -} -#endif - /** * @brief Function called to read the current micro second * @param None diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h index 0a6821a6c5..9599588563 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -998,22 +982,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1763,6 +1758,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1793,7 +1794,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1811,7 +1812,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1824,7 +1825,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1858,103 +1859,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -1964,7 +1869,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2200,8 +2104,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2211,31 +2114,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -14622,104 +14521,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -14873,220 +14772,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -20755,20 +21057,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -20863,33 +21151,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -20915,7 +21203,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -20939,9 +21226,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -20992,12 +21279,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -21299,9 +21580,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -21342,9 +21620,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -21365,9 +21640,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -21388,9 +21660,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -21478,22 +21755,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -21504,23 +21769,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -21537,124 +21787,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -21678,72 +21852,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© COPYRIGHT(c) 2017 STMicroelectronics
+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -964,22 +948,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1729,6 +1724,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1759,7 +1760,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1777,7 +1778,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1790,7 +1791,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1824,103 +1825,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -1930,7 +1835,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2166,8 +2070,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2177,31 +2080,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -14588,104 +14487,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -14839,220 +14738,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -20721,20 +21023,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -20829,33 +21117,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -20881,7 +21169,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -20905,9 +21192,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -20958,12 +21245,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -21265,9 +21546,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -21308,9 +21586,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -21331,9 +21606,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -21354,9 +21626,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -21444,22 +21721,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -21470,23 +21735,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -21503,124 +21753,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -21644,72 +21818,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© COPYRIGHT(c) 2017 STMicroelectronics
+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -998,22 +982,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1763,6 +1758,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1793,7 +1794,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1811,7 +1812,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1824,7 +1825,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1858,103 +1859,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -1964,7 +1869,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2200,8 +2104,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2211,31 +2114,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -14819,104 +14718,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -15070,220 +14969,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -20964,20 +21266,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -21072,33 +21360,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -21124,7 +21412,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -21148,9 +21435,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -21201,12 +21488,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -21508,9 +21789,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -21551,9 +21829,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -21574,9 +21849,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -21597,9 +21869,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -21687,22 +21964,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -21713,23 +21978,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -21746,124 +21996,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -21887,72 +22061,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© COPYRIGHT(c) 2017 STMicroelectronics
+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -964,22 +948,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1729,6 +1724,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1759,7 +1760,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1777,7 +1778,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1790,7 +1791,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1824,103 +1825,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -1930,7 +1835,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2166,8 +2070,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2177,31 +2080,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -14785,104 +14684,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -15036,220 +14935,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -20930,20 +21232,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -21038,33 +21326,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -21090,7 +21378,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -21114,9 +21401,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -21167,12 +21454,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -21474,9 +21755,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -21517,9 +21795,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -21540,9 +21815,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -21563,9 +21835,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -21653,22 +21930,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -21679,23 +21944,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -21712,124 +21962,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -21853,72 +22027,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp151dxx_ca7 + * @{ + */ + +#ifndef __STM32MP151Dxx_CA7_H +#define __STM32MP151Dxx_CA7_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-A Processor Specific Interrupt Numbers ***************************************************************/ + /* Software Generated Interrupts */ + SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ + SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ + SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ + SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ + SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ + SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ + SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ + SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ + SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ + SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ + SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ + SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ + SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ + SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ + SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ + SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ + /* Private Peripheral Interrupts */ + VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ + Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ + SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ + NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ + Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ + WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_36 = 36, /*!< RESERVED interrupt */ + RCC_IRQn = 37, /*!< RCC global Interrupt */ + EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 40, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 41, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 42, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 43, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 44, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 45, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 46, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 47, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 48, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 49, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 50, /*!< ADC1 global Interrupts */ + RESERVED_51 = 51, /*!< reserved */ + RESERVED_52 = 52, /*!< reserved */ + RESERVED_53 = 53, /*!< reserved */ + RESERVED_54 = 54, /*!< reserved */ + EXTI5_IRQn = 55, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 56, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 57, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 58, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 59, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 60, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 61, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 62, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 63, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 64, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 65, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 66, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 67, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 68, /*!< SPI2 global Interrupt */ + USART1_IRQn = 69, /*!< USART1 global Interrupt */ + USART2_IRQn = 70, /*!< USART2 global Interrupt */ + USART3_IRQn = 71, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 72, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 73, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 74, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 75, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 76, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 77, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 78, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 79, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 80, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 81, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 82, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 83, /*!< SPI3 global Interrupt */ + UART4_IRQn = 84, /*!< UART4 global Interrupt */ + UART5_IRQn = 85, /*!< UART5 global Interrupt */ + TIM6_IRQn = 86, /*!< TIM6 global */ + TIM7_IRQn = 87, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 88, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 89, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 90, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 91, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 92, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 93, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 94, /*!< Ethernet Wakeup through EXTI line Interrupt */ + RESERVED_95 = 95, /*!< reserved */ + EXTI6_IRQn = 96, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 97, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 98, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 99, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 100, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 101, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 102, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 103, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 106, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 107, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 108, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 109, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 110, /*!< DCMI global interrupt */ + RESERVED_111 = 111, /*!< reserved */ + HASH1_IRQn = 112, /*!< Hash global interrupt */ + RESERVED_113 = 113, /*!< reserved */ + UART7_IRQn = 114, /*!< UART7 global interrupt */ + UART8_IRQn = 115, /*!< UART8 global interrupt */ + SPI4_IRQn = 116, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 117, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 118, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 119, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 120, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 121, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 122, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 123, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 124, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 125, /*!< LP TIM1 interrupt */ + CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 127, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 128, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 130, /*!< USB On The Go global interrupt */ + RESERVED_131 = 131, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 132, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 133, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 134, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 135, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 136, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + RESERVED_137 = 137, /*!< reserved */ + HASH2_IRQn = 138, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 139, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 140, /*!< I2C5 Error Interrupt */ + RESERVED_141 = 141, /*!< reserved */ + DFSDM1_FLT0_IRQn = 142, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 143, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 144, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 145, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 146, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 147, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 148, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 149, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 150, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 151, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 152, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 153, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 154, /*!< MDMA global Interrupt */ + RESERVED_155 = 155, /*!< reserved */ + SDMMC2_IRQn = 156, /*!< SDMMC2 global Interrupt */ + HSEM_IT1_IRQn = 157, /*!< HSEM Semaphore Interrupt 1 */ + DFSDM1_FLT5_IRQn = 158, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 159, /*!< EXTI Line 15 Interrupts */ + MDMA_SEC_IT_IRQn = 160, /*!< MDMA global Secure interrupt */ + SYSRESETQ_IRQn = 161, /*!< MCU local Reset Request */ + TIM13_IRQn = 162, /*!< TIM13 global interrupt */ + TIM14_IRQn = 163, /*!< TIM14 global interrupt */ + DAC_IRQn = 164, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 165, /*!< RNG1 interrupt */ + RNG2_IRQn = 166, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 167, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 168, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 169, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 170, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 171, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 172, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 173, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 174, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + WWDG1_RST = 175, /*!< Window Watchdog 1 Reset through AIEC */ + MCU_SEV_IRQn = 176, /*!< MCU Send Event interrupt */ + RCC_WAKEUP_IRQn = 177, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 178, /*!< SAI4 global interrupt */ + DTS_IRQn = 179, /*!< Temperature sensor Global Interrupt */ + RESERVED_180 = 180, /*!< reserved */ + WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins */ + IWDG1_IRQn = 182, /*!< IWDG1 Early Interrupt */ + IWDG2_IRQn = 183, /*!< IWDG2 Early Interrupt */ + TAMP_SERR_S_IRQn = 229, /*!< TAMP Tamper and Security Error Secure interrupts */ + RTC_WKUP_ALARM_S_IRQn = 230, /*!< RTC Wakeup Timer and Alarms (A and B) Secure interrupt */ + RTC_TS_SERR_S_IRQn = 231, /*!< RTC TimeStamp and Security Error Secure interrupt */ + MAX_IRQ_n, + Force_IRQn_enum_size = 1048 /* Dummy entry to ensure IRQn_Type is more than 8 bits. Otherwise GIC init loop would fail */ + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals ============================ */ +#define __CORTEX_A 7U /*!< Cortex-A# Core */ +#define __CA_REV 0x0005U /*!< Core revision r0p0 */ +#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */ +#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */ +#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */ +#define __L2C_PRESENT 0U /*!< Set to 1 if L2C is present */ + +#define GIC_BASE 0xA0021000 +#define GIC_DISTRIBUTOR_BASE GIC_BASE +#define GIC_INTERFACE_BASE (GIC_BASE+0x1000) + +#include "core_ca.h" +#include "system_stm32mp1xx_A7.h" + + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP151Dxx_CA7_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h new file mode 100644 index 0000000000..bda89a8d73 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h @@ -0,0 +1,29008 @@ +/** + ****************************************************************************** + * @file stm32mp151dxx_cm4.h + * @author MCD Application Team + * @brief CMSIS stm32mp151dxx_cm4 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp151dxx_cm4 + * @{ + */ + +#ifndef __STM32MP151Dxx_CM4_H +#define __STM32MP151Dxx_CM4_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-M Processor Exceptions Numbers *******************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers ************************************************************************/ + WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_4 = 4, /*!< RESERVED interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupts */ + RESERVED_19 = 19, /*!< reserved */ + RESERVED_20 = 20, /*!< reserved */ + RESERVED_21 = 21, /*!< reserved */ + RESERVED_22 = 22, /*!< reserved */ + EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + RESERVED_63 = 63, /*!< RESERVED interrupt */ + EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + RESERVED_79 = 79, /*!< RESERVED interrupt */ + HASH1_IRQn = 80, /*!< Hash global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 90, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 98, /*!< USB On The Go global interrupt */ + RESERVED_99 = 99, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + RESERVED_105 = 105, /*!< RESERVED interrupt */ + HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */ + RESERVED_109 = 109, /*!< RESERVED interrupt */ + DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 114, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 119, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 122, /*!< MDMA global Interrupt */ + RESERVED_123 = 123, /*!< RESERVED interrupt */ + SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */ + HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */ + DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */ + nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */ + nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 133, /*!< RNG1 interrupt */ + RNG2_IRQn = 134, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + RESERVED_143 = 143, /*!< RESERVED interrupt */ + MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */ + RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 146, /*!< SAI4 global interrupt */ + DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */ + RESERVED_148 = 148, /*!< RESERVED interrupt */ + WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */ + MAX_IRQ_n + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_stm32mp1xx.h" + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP151Dxx_CM4_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h new file mode 100644 index 0000000000..bbfc353569 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h @@ -0,0 +1,29253 @@ +/** + ****************************************************************************** + * @file stm32mp151fxx_ca7.h + * @author MCD Application Team + * @brief CMSIS stm32mp151fxx_ca7 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp151fxx_ca7 + * @{ + */ + +#ifndef __STM32MP151Fxx_CA7_H +#define __STM32MP151Fxx_CA7_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-A Processor Specific Interrupt Numbers ***************************************************************/ + /* Software Generated Interrupts */ + SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ + SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ + SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ + SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ + SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ + SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ + SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ + SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ + SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ + SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ + SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ + SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ + SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ + SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ + SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ + SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ + /* Private Peripheral Interrupts */ + VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ + Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ + SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ + NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ + Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ + WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_36 = 36, /*!< RESERVED interrupt */ + RCC_IRQn = 37, /*!< RCC global Interrupt */ + EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 40, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 41, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 42, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 43, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 44, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 45, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 46, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 47, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 48, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 49, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 50, /*!< ADC1 global Interrupts */ + RESERVED_51 = 51, /*!< reserved */ + RESERVED_52 = 52, /*!< reserved */ + RESERVED_53 = 53, /*!< reserved */ + RESERVED_54 = 54, /*!< reserved */ + EXTI5_IRQn = 55, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 56, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 57, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 58, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 59, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 60, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 61, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 62, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 63, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 64, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 65, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 66, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 67, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 68, /*!< SPI2 global Interrupt */ + USART1_IRQn = 69, /*!< USART1 global Interrupt */ + USART2_IRQn = 70, /*!< USART2 global Interrupt */ + USART3_IRQn = 71, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 72, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 73, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 74, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 75, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 76, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 77, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 78, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 79, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 80, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 81, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 82, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 83, /*!< SPI3 global Interrupt */ + UART4_IRQn = 84, /*!< UART4 global Interrupt */ + UART5_IRQn = 85, /*!< UART5 global Interrupt */ + TIM6_IRQn = 86, /*!< TIM6 global */ + TIM7_IRQn = 87, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 88, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 89, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 90, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 91, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 92, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 93, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 94, /*!< Ethernet Wakeup through EXTI line Interrupt */ + RESERVED_95 = 95, /*!< reserved */ + EXTI6_IRQn = 96, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 97, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 98, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 99, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 100, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 101, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 102, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 103, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 106, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 107, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 108, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 109, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 110, /*!< DCMI global interrupt */ + CRYP1_IRQn = 111, /*!< CRYP crypto global interrupt */ + HASH1_IRQn = 112, /*!< Hash global interrupt */ + RESERVED_113 = 113, /*!< reserved */ + UART7_IRQn = 114, /*!< UART7 global interrupt */ + UART8_IRQn = 115, /*!< UART8 global interrupt */ + SPI4_IRQn = 116, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 117, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 118, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 119, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 120, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 121, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 122, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 123, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 124, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 125, /*!< LP TIM1 interrupt */ + CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 127, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 128, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 130, /*!< USB On The Go global interrupt */ + RESERVED_131 = 131, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 132, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 133, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 134, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 135, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 136, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + CRYP2_IRQn = 137, /*!< CRYP2 crypto global interrupt */ + HASH2_IRQn = 138, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 139, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 140, /*!< I2C5 Error Interrupt */ + RESERVED_141 = 141, /*!< reserved */ + DFSDM1_FLT0_IRQn = 142, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 143, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 144, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 145, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 146, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 147, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 148, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 149, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 150, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 151, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 152, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 153, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 154, /*!< MDMA global Interrupt */ + RESERVED_155 = 155, /*!< reserved */ + SDMMC2_IRQn = 156, /*!< SDMMC2 global Interrupt */ + HSEM_IT1_IRQn = 157, /*!< HSEM Semaphore Interrupt 1 */ + DFSDM1_FLT5_IRQn = 158, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 159, /*!< EXTI Line 15 Interrupts */ + MDMA_SEC_IT_IRQn = 160, /*!< MDMA global Secure interrupt */ + SYSRESETQ_IRQn = 161, /*!< MCU local Reset Request */ + TIM13_IRQn = 162, /*!< TIM13 global interrupt */ + TIM14_IRQn = 163, /*!< TIM14 global interrupt */ + DAC_IRQn = 164, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 165, /*!< RNG1 interrupt */ + RNG2_IRQn = 166, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 167, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 168, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 169, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 170, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 171, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 172, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 173, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 174, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + WWDG1_RST = 175, /*!< Window Watchdog 1 Reset through AIEC */ + MCU_SEV_IRQn = 176, /*!< MCU Send Event interrupt */ + RCC_WAKEUP_IRQn = 177, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 178, /*!< SAI4 global interrupt */ + DTS_IRQn = 179, /*!< Temperature sensor Global Interrupt */ + RESERVED_180 = 180, /*!< reserved */ + WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins */ + IWDG1_IRQn = 182, /*!< IWDG1 Early Interrupt */ + IWDG2_IRQn = 183, /*!< IWDG2 Early Interrupt */ + TAMP_SERR_S_IRQn = 229, /*!< TAMP Tamper and Security Error Secure interrupts */ + RTC_WKUP_ALARM_S_IRQn = 230, /*!< RTC Wakeup Timer and Alarms (A and B) Secure interrupt */ + RTC_TS_SERR_S_IRQn = 231, /*!< RTC TimeStamp and Security Error Secure interrupt */ + MAX_IRQ_n, + Force_IRQn_enum_size = 1048 /* Dummy entry to ensure IRQn_Type is more than 8 bits. Otherwise GIC init loop would fail */ + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals ============================ */ +#define __CORTEX_A 7U /*!< Cortex-A# Core */ +#define __CA_REV 0x0005U /*!< Core revision r0p0 */ +#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */ +#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */ +#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */ +#define __L2C_PRESENT 0U /*!< Set to 1 if L2C is present */ + +#define GIC_BASE 0xA0021000 +#define GIC_DISTRIBUTOR_BASE GIC_BASE +#define GIC_INTERFACE_BASE (GIC_BASE+0x1000) + +#include "core_ca.h" +#include "system_stm32mp1xx_A7.h" + + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* CRYP VERSION ********************************/ +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP151Fxx_CA7_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h new file mode 100644 index 0000000000..ff110729cb --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h @@ -0,0 +1,29219 @@ +/** + ****************************************************************************** + * @file stm32mp151fxx_cm4.h + * @author MCD Application Team + * @brief CMSIS stm32mp151fxx_cm4 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp151fxx_cm4 + * @{ + */ + +#ifndef __STM32MP151Fxx_CM4_H +#define __STM32MP151Fxx_CM4_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-M Processor Exceptions Numbers *******************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers ************************************************************************/ + WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_4 = 4, /*!< RESERVED interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupts */ + RESERVED_19 = 19, /*!< reserved */ + RESERVED_20 = 20, /*!< reserved */ + RESERVED_21 = 21, /*!< reserved */ + RESERVED_22 = 22, /*!< reserved */ + EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + RESERVED_63 = 63, /*!< RESERVED interrupt */ + EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP1_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH1_IRQn = 80, /*!< Hash global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 90, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 98, /*!< USB On The Go global interrupt */ + RESERVED_99 = 99, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + CRYP2_IRQn = 105, /*!< CRYP2 crypto global interrupt */ + HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */ + RESERVED_109 = 109, /*!< RESERVED interrupt */ + DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 114, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 119, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 122, /*!< MDMA global Interrupt */ + RESERVED_123 = 123, /*!< RESERVED interrupt */ + SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */ + HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */ + DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */ + nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */ + nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 133, /*!< RNG1 interrupt */ + RNG2_IRQn = 134, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + RESERVED_143 = 143, /*!< RESERVED interrupt */ + MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */ + RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 146, /*!< SAI4 global interrupt */ + DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */ + RESERVED_148 = 148, /*!< RESERVED interrupt */ + WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */ + MAX_IRQ_n + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_stm32mp1xx.h" + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* CRYP VERSION ********************************/ +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP151Fxx_CM4_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h index 47fc68e485..96c40248d2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1099,22 +1083,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1864,6 +1859,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1894,7 +1895,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1912,7 +1913,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1925,7 +1926,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1959,103 +1960,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2065,7 +1970,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2301,8 +2205,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2312,31 +2215,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -16186,104 +16085,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -16437,220 +16336,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -22333,20 +22635,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -22441,33 +22729,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -22493,7 +22781,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -22517,9 +22804,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -22570,12 +22857,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -22877,9 +23158,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -22920,9 +23198,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -22943,9 +23218,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -22966,9 +23238,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -23056,22 +23333,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -23082,23 +23347,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -23115,124 +23365,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23256,72 +23430,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
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+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1065,22 +1049,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1830,6 +1825,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1860,7 +1861,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1878,7 +1879,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1891,7 +1892,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1925,103 +1926,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2031,7 +1936,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2267,8 +2171,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2278,31 +2181,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -16152,104 +16051,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -16403,220 +16302,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -22299,20 +22601,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -22407,33 +22695,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -22459,7 +22747,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -22483,9 +22770,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -22536,12 +22823,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -22843,9 +23124,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -22886,9 +23164,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -22909,9 +23184,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -22932,9 +23204,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -23022,22 +23299,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -23048,23 +23313,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -23081,124 +23331,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23222,72 +23396,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© COPYRIGHT(c) 2017 STMicroelectronics
+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1099,22 +1083,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1864,6 +1859,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1894,7 +1895,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1912,7 +1913,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1925,7 +1926,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1959,103 +1960,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2065,7 +1970,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2301,8 +2205,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2312,31 +2215,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -16383,104 +16282,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -16634,220 +16533,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -22542,20 +22844,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -22650,33 +22938,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -22702,7 +22990,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -22726,9 +23013,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -22779,12 +23066,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -23086,9 +23367,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -23129,9 +23407,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -23152,9 +23427,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -23175,9 +23447,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -23265,22 +23542,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -23291,23 +23556,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -23324,124 +23574,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23465,72 +23639,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© COPYRIGHT(c) 2017 STMicroelectronics
+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1065,22 +1049,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1830,6 +1825,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1860,7 +1861,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1878,7 +1879,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1891,7 +1892,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -1925,103 +1926,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2031,7 +1936,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2267,8 +2171,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2278,31 +2181,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -16349,104 +16248,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -16600,220 +16499,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -22508,20 +22810,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -22616,33 +22904,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -22668,7 +22956,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -22692,9 +22979,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -22745,12 +23032,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -23052,9 +23333,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -23095,9 +23373,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -23118,9 +23393,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -23141,9 +23413,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -23231,22 +23508,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -23257,23 +23522,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -23290,124 +23540,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23431,72 +23605,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp153dxx_ca7 + * @{ + */ + +#ifndef __STM32MP153Dxx_CA7_H +#define __STM32MP153Dxx_CA7_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-A Processor Specific Interrupt Numbers ***************************************************************/ + /* Software Generated Interrupts */ + SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ + SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ + SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ + SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ + SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ + SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ + SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ + SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ + SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ + SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ + SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ + SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ + SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ + SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ + SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ + SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ + /* Private Peripheral Interrupts */ + VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ + Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ + SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ + NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ + Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ + WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_36 = 36, /*!< RESERVED interrupt */ + RCC_IRQn = 37, /*!< RCC global Interrupt */ + EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 40, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 41, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 42, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 43, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 44, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 45, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 46, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 47, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 48, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 49, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 50, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 51, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 52, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 53, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 54, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 55, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 56, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 57, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 58, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 59, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 60, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 61, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 62, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 63, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 64, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 65, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 66, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 67, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 68, /*!< SPI2 global Interrupt */ + USART1_IRQn = 69, /*!< USART1 global Interrupt */ + USART2_IRQn = 70, /*!< USART2 global Interrupt */ + USART3_IRQn = 71, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 72, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 73, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 74, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 75, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 76, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 77, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 78, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 79, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 80, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 81, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 82, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 83, /*!< SPI3 global Interrupt */ + UART4_IRQn = 84, /*!< UART4 global Interrupt */ + UART5_IRQn = 85, /*!< UART5 global Interrupt */ + TIM6_IRQn = 86, /*!< TIM6 global */ + TIM7_IRQn = 87, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 88, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 89, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 90, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 91, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 92, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 93, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 94, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 95, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 96, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 97, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 98, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 99, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 100, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 101, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 102, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 103, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 106, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 107, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 108, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 109, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 110, /*!< DCMI global interrupt */ + RESERVED_111 = 111, /*!< reserved */ + HASH1_IRQn = 112, /*!< Hash global interrupt */ + RESERVED_113 = 113, /*!< reserved */ + UART7_IRQn = 114, /*!< UART7 global interrupt */ + UART8_IRQn = 115, /*!< UART8 global interrupt */ + SPI4_IRQn = 116, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 117, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 118, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 119, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 120, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 121, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 122, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 123, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 124, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 125, /*!< LP TIM1 interrupt */ + CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 127, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 128, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 130, /*!< USB On The Go global interrupt */ + RESERVED_131 = 131, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 132, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 133, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 134, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 135, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 136, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + RESERVED_137 = 137, /*!< reserved */ + HASH2_IRQn = 138, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 139, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 140, /*!< I2C5 Error Interrupt */ + RESERVED_141 = 141, /*!< reserved */ + DFSDM1_FLT0_IRQn = 142, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 143, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 144, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 145, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 146, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 147, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 148, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 149, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 150, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 151, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 152, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 153, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 154, /*!< MDMA global Interrupt */ + RESERVED_155 = 155, /*!< reserved */ + SDMMC2_IRQn = 156, /*!< SDMMC2 global Interrupt */ + HSEM_IT1_IRQn = 157, /*!< HSEM Semaphore Interrupt 1 */ + DFSDM1_FLT5_IRQn = 158, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 159, /*!< EXTI Line 15 Interrupts */ + MDMA_SEC_IT_IRQn = 160, /*!< MDMA global Secure interrupt */ + SYSRESETQ_IRQn = 161, /*!< MCU local Reset Request */ + TIM13_IRQn = 162, /*!< TIM13 global interrupt */ + TIM14_IRQn = 163, /*!< TIM14 global interrupt */ + DAC_IRQn = 164, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 165, /*!< RNG1 interrupt */ + RNG2_IRQn = 166, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 167, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 168, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 169, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 170, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 171, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 172, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 173, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 174, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + WWDG1_RST = 175, /*!< Window Watchdog 1 Reset through AIEC */ + MCU_SEV_IRQn = 176, /*!< MCU Send Event interrupt */ + RCC_WAKEUP_IRQn = 177, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 178, /*!< SAI4 global interrupt */ + DTS_IRQn = 179, /*!< Temperature sensor Global Interrupt */ + RESERVED_180 = 180, /*!< reserved */ + WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins */ + IWDG1_IRQn = 182, /*!< IWDG1 Early Interrupt */ + IWDG2_IRQn = 183, /*!< IWDG2 Early Interrupt */ + TAMP_SERR_S_IRQn = 229, /*!< TAMP Tamper and Security Error Secure interrupts */ + RTC_WKUP_ALARM_S_IRQn = 230, /*!< RTC Wakeup Timer and Alarms (A and B) Secure interrupt */ + RTC_TS_SERR_S_IRQn = 231, /*!< RTC TimeStamp and Security Error Secure interrupt */ + MAX_IRQ_n, + Force_IRQn_enum_size = 1048 /* Dummy entry to ensure IRQn_Type is more than 8 bits. Otherwise GIC init loop would fail */ + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals ============================ */ +#define __CORTEX_A 7U /*!< Cortex-A# Core */ +#define __CA_REV 0x0005U /*!< Core revision r0p0 */ +#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */ +#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */ +#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */ +#define __L2C_PRESENT 0U /*!< Set to 1 if L2C is present */ + +#define GIC_BASE 0xA0021000 +#define GIC_DISTRIBUTOR_BASE GIC_BASE +#define GIC_INTERFACE_BASE (GIC_BASE+0x1000) + +#include "core_ca.h" +#include "system_stm32mp1xx_A7.h" + + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP153Dxx_CA7_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h new file mode 100644 index 0000000000..a86122ac4f --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h @@ -0,0 +1,30591 @@ +/** + ****************************************************************************** + * @file stm32mp153dxx_cm4.h + * @author MCD Application Team + * @brief CMSIS stm32mp153dxx_cm4 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp153dxx_cm4 + * @{ + */ + +#ifndef __STM32MP153Dxx_CM4_H +#define __STM32MP153Dxx_CM4_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-M Processor Exceptions Numbers *******************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers ************************************************************************/ + WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_4 = 4, /*!< RESERVED interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + RESERVED_79 = 79, /*!< RESERVED interrupt */ + HASH1_IRQn = 80, /*!< Hash global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 90, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 98, /*!< USB On The Go global interrupt */ + RESERVED_99 = 99, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + RESERVED_105 = 105, /*!< RESERVED interrupt */ + HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */ + RESERVED_109 = 109, /*!< RESERVED interrupt */ + DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 114, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 119, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 122, /*!< MDMA global Interrupt */ + RESERVED_123 = 123, /*!< RESERVED interrupt */ + SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */ + HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */ + DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */ + nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */ + nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 133, /*!< RNG1 interrupt */ + RNG2_IRQn = 134, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + RESERVED_143 = 143, /*!< RESERVED interrupt */ + MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */ + RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 146, /*!< SAI4 global interrupt */ + DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */ + RESERVED_148 = 148, /*!< RESERVED interrupt */ + WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */ + MAX_IRQ_n + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_stm32mp1xx.h" + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP153Dxx_CM4_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h new file mode 100644 index 0000000000..8a21736f8a --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h @@ -0,0 +1,30836 @@ +/** + ****************************************************************************** + * @file stm32mp153fxx_ca7.h + * @author MCD Application Team + * @brief CMSIS stm32mp153fxx_ca7 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp153fxx_ca7 + * @{ + */ + +#ifndef __STM32MP153Fxx_CA7_H +#define __STM32MP153Fxx_CA7_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-A Processor Specific Interrupt Numbers ***************************************************************/ + /* Software Generated Interrupts */ + SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ + SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ + SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ + SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ + SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ + SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ + SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ + SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ + SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ + SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ + SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ + SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ + SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ + SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ + SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ + SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ + /* Private Peripheral Interrupts */ + VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ + Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ + SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ + NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ + Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ + WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_36 = 36, /*!< RESERVED interrupt */ + RCC_IRQn = 37, /*!< RCC global Interrupt */ + EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 40, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 41, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 42, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 43, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 44, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 45, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 46, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 47, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 48, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 49, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 50, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 51, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 52, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 53, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 54, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 55, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 56, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 57, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 58, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 59, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 60, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 61, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 62, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 63, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 64, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 65, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 66, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 67, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 68, /*!< SPI2 global Interrupt */ + USART1_IRQn = 69, /*!< USART1 global Interrupt */ + USART2_IRQn = 70, /*!< USART2 global Interrupt */ + USART3_IRQn = 71, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 72, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 73, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 74, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 75, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 76, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 77, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 78, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 79, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 80, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 81, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 82, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 83, /*!< SPI3 global Interrupt */ + UART4_IRQn = 84, /*!< UART4 global Interrupt */ + UART5_IRQn = 85, /*!< UART5 global Interrupt */ + TIM6_IRQn = 86, /*!< TIM6 global */ + TIM7_IRQn = 87, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 88, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 89, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 90, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 91, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 92, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 93, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 94, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 95, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 96, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 97, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 98, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 99, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 100, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 101, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 102, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 103, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 106, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 107, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 108, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 109, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 110, /*!< DCMI global interrupt */ + CRYP1_IRQn = 111, /*!< CRYP crypto global interrupt */ + HASH1_IRQn = 112, /*!< Hash global interrupt */ + RESERVED_113 = 113, /*!< reserved */ + UART7_IRQn = 114, /*!< UART7 global interrupt */ + UART8_IRQn = 115, /*!< UART8 global interrupt */ + SPI4_IRQn = 116, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 117, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 118, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 119, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 120, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 121, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 122, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 123, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 124, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 125, /*!< LP TIM1 interrupt */ + CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 127, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 128, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 130, /*!< USB On The Go global interrupt */ + RESERVED_131 = 131, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 132, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 133, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 134, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 135, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 136, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + CRYP2_IRQn = 137, /*!< CRYP2 crypto global interrupt */ + HASH2_IRQn = 138, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 139, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 140, /*!< I2C5 Error Interrupt */ + RESERVED_141 = 141, /*!< reserved */ + DFSDM1_FLT0_IRQn = 142, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 143, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 144, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 145, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 146, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 147, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 148, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 149, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 150, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 151, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 152, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 153, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 154, /*!< MDMA global Interrupt */ + RESERVED_155 = 155, /*!< reserved */ + SDMMC2_IRQn = 156, /*!< SDMMC2 global Interrupt */ + HSEM_IT1_IRQn = 157, /*!< HSEM Semaphore Interrupt 1 */ + DFSDM1_FLT5_IRQn = 158, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 159, /*!< EXTI Line 15 Interrupts */ + MDMA_SEC_IT_IRQn = 160, /*!< MDMA global Secure interrupt */ + SYSRESETQ_IRQn = 161, /*!< MCU local Reset Request */ + TIM13_IRQn = 162, /*!< TIM13 global interrupt */ + TIM14_IRQn = 163, /*!< TIM14 global interrupt */ + DAC_IRQn = 164, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 165, /*!< RNG1 interrupt */ + RNG2_IRQn = 166, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 167, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 168, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 169, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 170, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 171, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 172, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 173, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 174, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + WWDG1_RST = 175, /*!< Window Watchdog 1 Reset through AIEC */ + MCU_SEV_IRQn = 176, /*!< MCU Send Event interrupt */ + RCC_WAKEUP_IRQn = 177, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 178, /*!< SAI4 global interrupt */ + DTS_IRQn = 179, /*!< Temperature sensor Global Interrupt */ + RESERVED_180 = 180, /*!< reserved */ + WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins */ + IWDG1_IRQn = 182, /*!< IWDG1 Early Interrupt */ + IWDG2_IRQn = 183, /*!< IWDG2 Early Interrupt */ + TAMP_SERR_S_IRQn = 229, /*!< TAMP Tamper and Security Error Secure interrupts */ + RTC_WKUP_ALARM_S_IRQn = 230, /*!< RTC Wakeup Timer and Alarms (A and B) Secure interrupt */ + RTC_TS_SERR_S_IRQn = 231, /*!< RTC TimeStamp and Security Error Secure interrupt */ + MAX_IRQ_n, + Force_IRQn_enum_size = 1048 /* Dummy entry to ensure IRQn_Type is more than 8 bits. Otherwise GIC init loop would fail */ + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals ============================ */ +#define __CORTEX_A 7U /*!< Cortex-A# Core */ +#define __CA_REV 0x0005U /*!< Core revision r0p0 */ +#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */ +#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */ +#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */ +#define __L2C_PRESENT 0U /*!< Set to 1 if L2C is present */ + +#define GIC_BASE 0xA0021000 +#define GIC_DISTRIBUTOR_BASE GIC_BASE +#define GIC_INTERFACE_BASE (GIC_BASE+0x1000) + +#include "core_ca.h" +#include "system_stm32mp1xx_A7.h" + + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* CRYP VERSION ********************************/ +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP153Fxx_CA7_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h new file mode 100644 index 0000000000..38af1becd2 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h @@ -0,0 +1,30802 @@ +/** + ****************************************************************************** + * @file stm32mp153fxx_cm4.h + * @author MCD Application Team + * @brief CMSIS stm32mp153fxx_cm4 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp153fxx_cm4 + * @{ + */ + +#ifndef __STM32MP153Fxx_CM4_H +#define __STM32MP153Fxx_CM4_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-M Processor Exceptions Numbers *******************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers ************************************************************************/ + WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_4 = 4, /*!< RESERVED interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP1_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH1_IRQn = 80, /*!< Hash global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 90, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 98, /*!< USB On The Go global interrupt */ + RESERVED_99 = 99, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + CRYP2_IRQn = 105, /*!< CRYP2 crypto global interrupt */ + HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */ + RESERVED_109 = 109, /*!< RESERVED interrupt */ + DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 114, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 119, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 122, /*!< MDMA global Interrupt */ + RESERVED_123 = 123, /*!< RESERVED interrupt */ + SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */ + HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */ + DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */ + nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */ + nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 133, /*!< RNG1 interrupt */ + RNG2_IRQn = 134, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + RESERVED_143 = 143, /*!< RESERVED interrupt */ + MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */ + RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 146, /*!< SAI4 global interrupt */ + DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */ + RESERVED_148 = 148, /*!< RESERVED interrupt */ + WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */ + MAX_IRQ_n + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_stm32mp1xx.h" + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* CRYP VERSION ********************************/ +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP153Fxx_CM4_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h index 6f489622a8..45f2fc4739 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1186,22 +1170,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1951,6 +1946,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1981,7 +1982,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1999,7 +2000,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -2012,7 +2013,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -2046,103 +2047,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2152,7 +2057,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2388,8 +2292,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2399,31 +2302,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -17411,104 +17310,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -17662,220 +17561,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -23579,20 +23881,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -23687,33 +23975,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -23739,7 +24027,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -23763,9 +24050,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -23816,12 +24103,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -24123,9 +24404,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -24166,9 +24444,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -24189,9 +24464,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -24212,9 +24484,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -24302,22 +24579,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -24328,23 +24593,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -24361,124 +24611,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24502,72 +24676,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© COPYRIGHT(c) 2017 STMicroelectronics
+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1152,22 +1136,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1917,6 +1912,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1947,7 +1948,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1965,7 +1966,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1978,7 +1979,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -2012,103 +2013,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2118,7 +2023,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2354,8 +2258,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2365,31 +2268,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -17377,104 +17276,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -17628,220 +17527,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -23545,20 +23847,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -23653,33 +23941,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -23705,7 +23993,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -23729,9 +24016,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -23782,12 +24069,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -24089,9 +24370,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -24132,9 +24410,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -24155,9 +24430,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -24178,9 +24450,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -24268,22 +24545,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -24294,23 +24559,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -24327,124 +24577,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24468,72 +24642,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
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+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1186,22 +1170,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1951,6 +1946,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1981,7 +1982,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1999,7 +2000,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -2012,7 +2013,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -2046,103 +2047,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2152,7 +2057,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2388,8 +2292,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2399,31 +2302,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -17608,104 +17507,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -17859,220 +17758,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -23788,20 +24090,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -23896,33 +24184,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -23948,7 +24236,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -23972,9 +24259,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -24025,12 +24312,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -24332,9 +24613,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -24375,9 +24653,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -24398,9 +24673,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -24421,9 +24693,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -24511,22 +24788,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -24537,23 +24802,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -24570,124 +24820,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24711,72 +24885,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© COPYRIGHT(c) 2017 STMicroelectronics
+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1152,22 +1136,33 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x28-0x2C */ - __IO uint32_t SECR; /*!< GPIO security register, Address offset: 0x30 */ - uint32_t RESERVED1[240];/*!< Reserved, 0x24->0x3F4 */ - __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< GPIO version register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< GPIO version register, Address offset: 0x3FC */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ } GPIO_TypeDef; @@ -1917,6 +1912,12 @@ typedef struct } BSEC_TypeDef; +/** + * @brief RTC Specific device feature definitions + */ +#define RTC_BACKUP_NB 32u /* Backup registers implemented */ +#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */ + /** * @brief Real-Time Clock */ @@ -1947,7 +1948,7 @@ typedef struct __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ uint32_t RESERVED2[227]; /*!< Reserved */ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ @@ -1965,7 +1966,7 @@ typedef struct __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */ uint32_t RESERVED; /*!< Reserved */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR; /*!< TAMP active tamper control register, Address offset: 0x10 */ + __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved */ @@ -1978,7 +1979,7 @@ typedef struct __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */ - __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ @@ -2012,103 +2013,7 @@ typedef struct __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ - __IO uint32_t BKP32R; /*!< TAMP backup register 32, Address offset: 0x180 */ - __IO uint32_t BKP33R; /*!< TAMP backup register 33, Address offset: 0x184 */ - __IO uint32_t BKP34R; /*!< TAMP backup register 34, Address offset: 0x188 */ - __IO uint32_t BKP35R; /*!< TAMP backup register 35, Address offset: 0x18C */ - __IO uint32_t BKP36R; /*!< TAMP backup register 36, Address offset: 0x190 */ - __IO uint32_t BKP37R; /*!< TAMP backup register 37, Address offset: 0x194 */ - __IO uint32_t BKP38R; /*!< TAMP backup register 38, Address offset: 0x198 */ - __IO uint32_t BKP39R; /*!< TAMP backup register 39, Address offset: 0x19C */ - __IO uint32_t BKP40R; /*!< TAMP backup register 40, Address offset: 0x1A0 */ - __IO uint32_t BKP41R; /*!< TAMP backup register 41, Address offset: 0x1A4 */ - __IO uint32_t BKP42R; /*!< TAMP backup register 42, Address offset: 0x1A8 */ - __IO uint32_t BKP43R; /*!< TAMP backup register 43, Address offset: 0x1AC */ - __IO uint32_t BKP44R; /*!< TAMP backup register 44, Address offset: 0x1B0 */ - __IO uint32_t BKP45R; /*!< TAMP backup register 45, Address offset: 0x1B4 */ - __IO uint32_t BKP46R; /*!< TAMP backup register 46, Address offset: 0x1B8 */ - __IO uint32_t BKP47R; /*!< TAMP backup register 47, Address offset: 0x1BC */ - __IO uint32_t BKP48R; /*!< TAMP backup register 48, Address offset: 0x1C0 */ - __IO uint32_t BKP49R; /*!< TAMP backup register 49, Address offset: 0x1C4 */ - __IO uint32_t BKP50R; /*!< TAMP backup register 50, Address offset: 0x1C8 */ - __IO uint32_t BKP51R; /*!< TAMP backup register 51, Address offset: 0x1CC */ - __IO uint32_t BKP52R; /*!< TAMP backup register 52, Address offset: 0x1D0 */ - __IO uint32_t BKP53R; /*!< TAMP backup register 53, Address offset: 0x1D4 */ - __IO uint32_t BKP54R; /*!< TAMP backup register 54, Address offset: 0x1D8 */ - __IO uint32_t BKP55R; /*!< TAMP backup register 55, Address offset: 0x1DC */ - __IO uint32_t BKP56R; /*!< TAMP backup register 56, Address offset: 0x1E0 */ - __IO uint32_t BKP57R; /*!< TAMP backup register 57, Address offset: 0x1E4 */ - __IO uint32_t BKP58R; /*!< TAMP backup register 58, Address offset: 0x1E8 */ - __IO uint32_t BKP59R; /*!< TAMP backup register 59, Address offset: 0x1EC */ - __IO uint32_t BKP60R; /*!< TAMP backup register 60, Address offset: 0x1F0 */ - __IO uint32_t BKP61R; /*!< TAMP backup register 61, Address offset: 0x1F4 */ - __IO uint32_t BKP62R; /*!< TAMP backup register 62, Address offset: 0x1F8 */ - __IO uint32_t BKP63R; /*!< TAMP backup register 63, Address offset: 0x1FC */ - __IO uint32_t BKP64R; /*!< TAMP backup register 64, Address offset: 0x200 */ - __IO uint32_t BKP65R; /*!< TAMP backup register 65, Address offset: 0x204 */ - __IO uint32_t BKP66R; /*!< TAMP backup register 66, Address offset: 0x208 */ - __IO uint32_t BKP67R; /*!< TAMP backup register 67, Address offset: 0x20C */ - __IO uint32_t BKP68R; /*!< TAMP backup register 68, Address offset: 0x210 */ - __IO uint32_t BKP69R; /*!< TAMP backup register 69, Address offset: 0x214 */ - __IO uint32_t BKP70R; /*!< TAMP backup register 70, Address offset: 0x218 */ - __IO uint32_t BKP71R; /*!< TAMP backup register 71, Address offset: 0x21C */ - __IO uint32_t BKP72R; /*!< TAMP backup register 72, Address offset: 0x220 */ - __IO uint32_t BKP73R; /*!< TAMP backup register 73, Address offset: 0x224 */ - __IO uint32_t BKP74R; /*!< TAMP backup register 74, Address offset: 0x228 */ - __IO uint32_t BKP75R; /*!< TAMP backup register 75, Address offset: 0x22C */ - __IO uint32_t BKP76R; /*!< TAMP backup register 76, Address offset: 0x230 */ - __IO uint32_t BKP77R; /*!< TAMP backup register 77, Address offset: 0x234 */ - __IO uint32_t BKP78R; /*!< TAMP backup register 78, Address offset: 0x238 */ - __IO uint32_t BKP79R; /*!< TAMP backup register 79, Address offset: 0x23C */ - __IO uint32_t BKP80R; /*!< TAMP backup register 80, Address offset: 0x240 */ - __IO uint32_t BKP81R; /*!< TAMP backup register 81, Address offset: 0x244 */ - __IO uint32_t BKP82R; /*!< TAMP backup register 82, Address offset: 0x248 */ - __IO uint32_t BKP83R; /*!< TAMP backup register 83, Address offset: 0x24C */ - __IO uint32_t BKP84R; /*!< TAMP backup register 84, Address offset: 0x250 */ - __IO uint32_t BKP85R; /*!< TAMP backup register 85, Address offset: 0x254 */ - __IO uint32_t BKP86R; /*!< TAMP backup register 86, Address offset: 0x258 */ - __IO uint32_t BKP87R; /*!< TAMP backup register 87, Address offset: 0x25C */ - __IO uint32_t BKP88R; /*!< TAMP backup register 88, Address offset: 0x260 */ - __IO uint32_t BKP89R; /*!< TAMP backup register 89, Address offset: 0x264 */ - __IO uint32_t BKP90R; /*!< TAMP backup register 90, Address offset: 0x268 */ - __IO uint32_t BKP91R; /*!< TAMP backup register 91, Address offset: 0x26C */ - __IO uint32_t BKP92R; /*!< TAMP backup register 92, Address offset: 0x270 */ - __IO uint32_t BKP93R; /*!< TAMP backup register 93, Address offset: 0x274 */ - __IO uint32_t BKP94R; /*!< TAMP backup register 94, Address offset: 0x278 */ - __IO uint32_t BKP95R; /*!< TAMP backup register 95, Address offset: 0x27C */ - __IO uint32_t BKP96R; /*!< TAMP backup register 96, Address offset: 0x280 */ - __IO uint32_t BKP97R; /*!< TAMP backup register 97, Address offset: 0x284 */ - __IO uint32_t BKP98R; /*!< TAMP backup register 98, Address offset: 0x288 */ - __IO uint32_t BKP99R; /*!< TAMP backup register 99, Address offset: 0x28C */ - __IO uint32_t BKP100R; /*!< TAMP backup register 100, Address offset: 0x290 */ - __IO uint32_t BKP101R; /*!< TAMP backup register 101, Address offset: 0x294 */ - __IO uint32_t BKP102R; /*!< TAMP backup register 102, Address offset: 0x298 */ - __IO uint32_t BKP103R; /*!< TAMP backup register 103, Address offset: 0x29C */ - __IO uint32_t BKP104R; /*!< TAMP backup register 104, Address offset: 0x2A0 */ - __IO uint32_t BKP105R; /*!< TAMP backup register 105, Address offset: 0x2A4 */ - __IO uint32_t BKP106R; /*!< TAMP backup register 106, Address offset: 0x2A8 */ - __IO uint32_t BKP107R; /*!< TAMP backup register 107, Address offset: 0x2AC */ - __IO uint32_t BKP108R; /*!< TAMP backup register 108, Address offset: 0x2B0 */ - __IO uint32_t BKP109R; /*!< TAMP backup register 109, Address offset: 0x2B4 */ - __IO uint32_t BKP110R; /*!< TAMP backup register 110, Address offset: 0x2B8 */ - __IO uint32_t BKP111R; /*!< TAMP backup register 111, Address offset: 0x2BC */ - __IO uint32_t BKP112R; /*!< TAMP backup register 112, Address offset: 0x2C0 */ - __IO uint32_t BKP113R; /*!< TAMP backup register 113, Address offset: 0x2C4 */ - __IO uint32_t BKP114R; /*!< TAMP backup register 114, Address offset: 0x2C8 */ - __IO uint32_t BKP115R; /*!< TAMP backup register 115, Address offset: 0x2CC */ - __IO uint32_t BKP116R; /*!< TAMP backup register 116, Address offset: 0x2D0 */ - __IO uint32_t BKP117R; /*!< TAMP backup register 117, Address offset: 0x2D4 */ - __IO uint32_t BKP118R; /*!< TAMP backup register 118, Address offset: 0x2D8 */ - __IO uint32_t BKP119R; /*!< TAMP backup register 119, Address offset: 0x2DC */ - __IO uint32_t BKP120R; /*!< TAMP backup register 120, Address offset: 0x2E0 */ - __IO uint32_t BKP121R; /*!< TAMP backup register 121, Address offset: 0x2E4 */ - __IO uint32_t BKP122R; /*!< TAMP backup register 122, Address offset: 0x2E8 */ - __IO uint32_t BKP123R; /*!< TAMP backup register 123, Address offset: 0x2EC */ - __IO uint32_t BKP124R; /*!< TAMP backup register 124, Address offset: 0x2F0 */ - __IO uint32_t BKP125R; /*!< TAMP backup register 125, Address offset: 0x2F4 */ - __IO uint32_t BKP126R; /*!< TAMP backup register 126, Address offset: 0x2F8 */ - __IO uint32_t BKP127R; /*!< TAMP backup register 127, Address offset: 0x2FC */ - uint32_t RESERVED5[59]; /*!< Reserved, 0x0300 - 0x3E8 */ + uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ @@ -2118,7 +2023,6 @@ typedef struct } TAMP_TypeDef; - /** * @brief Serial Audio Interface */ @@ -2354,8 +2258,7 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ @@ -2365,31 +2268,27 @@ typedef struct __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - uint16_t RESERVED14; /*!< Reserved, 0x50 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ - uint32_t RESERVED2[226]; /*!< Reserved, 0x6C-0x3F0 */ - __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ + uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */ + __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */ } TIM_TypeDef; /** @@ -17574,104 +17473,104 @@ typedef struct #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) -#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ -#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) -#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ -#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) -#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ -#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) -#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ -#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) -#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ -#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) -#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ -#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) -#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ -#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) -#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ -#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) -#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ -#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) -#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ -#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) -#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ -#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) -#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ -#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) -#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ -#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) -#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ -#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) -#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ -#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) -#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ -#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) -#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ -#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) -#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ -#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) -#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ -#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) -#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ -#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) -#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ -#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) -#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ -#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) -#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ -#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) -#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ -#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) -#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ -#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) -#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ -#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) -#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ -#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) -#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ -#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) -#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ -#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) -#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ -#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) -#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ -#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) -#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ -#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) @@ -17825,220 +17724,623 @@ typedef struct #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) -#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ -#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk -#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ -#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ -#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ -#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) -#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk -#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ -#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ -#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ -#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) -#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk -#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ -#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ -#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ -#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) -#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk -#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ -#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ -#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ -#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) -#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk -#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ -#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ -#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ -#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) -#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk -#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ -#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ -#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ -#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) -#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk -#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ -#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ -#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ -#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) -#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk -#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ -#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ -#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ -#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ +#define GPIO_AFRL_AFR0_Pos (0U) +#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk +#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFR1_Pos (4U) +#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk +#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFR2_Pos (8U) +#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk +#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFR3_Pos (12U) +#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk +#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFR4_Pos (16U) +#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk +#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFR5_Pos (20U) +#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk +#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFR6_Pos (24U) +#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk +#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFR7_Pos (28U) +#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk +#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) -#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ -#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk -#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ -#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ -#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ -#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) -#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ -#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk -#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ -#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ -#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ -#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) -#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ -#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk -#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ -#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ -#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ -#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) -#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ -#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk -#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ -#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ -#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ -#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) -#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ -#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk -#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ -#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ -#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ -#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) -#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ -#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk -#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ -#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ -#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ -#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) -#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ -#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk -#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ -#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ -#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ -#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) -#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ -#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ -#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ -#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ -#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ +#define GPIO_AFRH_AFR8_Pos (0U) +#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk +#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFR9_Pos (4U) +#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk +#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFR10_Pos (8U) +#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk +#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFR11_Pos (12U) +#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk +#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFR12_Pos (16U) +#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk +#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFR13_Pos (20U) +#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk +#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFR14_Pos (24U) +#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk +#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFR15_Pos (28U) +#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk +#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) -#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) -#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) -#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) -#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) -#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) -#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) -#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) -#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) -#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) -#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) -#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) -#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) -#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) -#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) -#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) -#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk -/****************** Bits definition for GPIO_SECR register ******************/ -#define GPIO_SECR_SEC0_Pos (0U) -#define GPIO_SECR_SEC0_Msk (0x1U << GPIO_SECR_SEC0_Pos) /*!< 0x00000001 */ -#define GPIO_SECR_SEC0 GPIO_SECR_SEC0_Msk -#define GPIO_SECR_SEC1_Pos (1U) -#define GPIO_SECR_SEC1_Msk (0x1U << GPIO_SECR_SEC1_Pos) /*!< 0x00000002 */ -#define GPIO_SECR_SEC1 GPIO_SECR_SEC1_Msk -#define GPIO_SECR_SEC2_Pos (2U) -#define GPIO_SECR_SEC2_Msk (0x1U << GPIO_SECR_SEC2_Pos) /*!< 0x00000004 */ -#define GPIO_SECR_SEC2 GPIO_SECR_SEC2_Msk -#define GPIO_SECR_SEC3_Pos (3U) -#define GPIO_SECR_SEC3_Msk (0x1U << GPIO_SECR_SEC3_Pos) /*!< 0x00000008 */ -#define GPIO_SECR_SEC3 GPIO_SECR_SEC3_Msk -#define GPIO_SECR_SEC4_Pos (4U) -#define GPIO_SECR_SEC4_Msk (0x1U << GPIO_SECR_SEC4_Pos) /*!< 0x00000010 */ -#define GPIO_SECR_SEC4 GPIO_SECR_SEC4_Msk -#define GPIO_SECR_SEC5_Pos (5U) -#define GPIO_SECR_SEC5_Msk (0x1U << GPIO_SECR_SEC5_Pos) /*!< 0x00000020 */ -#define GPIO_SECR_SEC5 GPIO_SECR_SEC5_Msk -#define GPIO_SECR_SEC6_Pos (6U) -#define GPIO_SECR_SEC6_Msk (0x1U << GPIO_SECR_SEC6_Pos) /*!< 0x00000040 */ -#define GPIO_SECR_SEC6 GPIO_SECR_SEC6_Msk -#define GPIO_SECR_SEC7_Pos (7U) -#define GPIO_SECR_SEC7_Msk (0x1U << GPIO_SECR_SEC7_Pos) /*!< 0x00000080 */ -#define GPIO_SECR_SEC7 GPIO_SECR_SEC7_Msk -#define GPIO_SECR_SEC8_Pos (8U) -#define GPIO_SECR_SEC8_Msk (0x1U << GPIO_SECR_SEC8_Pos) /*!< 0x00000100 */ -#define GPIO_SECR_SEC8 GPIO_SECR_SEC8_Msk -#define GPIO_SECR_SEC9_Pos (9U) -#define GPIO_SECR_SEC9_Msk (0x1U << GPIO_SECR_SEC9_Pos) /*!< 0x00000200 */ -#define GPIO_SECR_SEC9 GPIO_SECR_SEC9_Msk -#define GPIO_SECR_SEC10_Pos (10U) -#define GPIO_SECR_SEC10_Msk (0x1U << GPIO_SECR_SEC10_Pos) /*!< 0x00000400 */ -#define GPIO_SECR_SEC10 GPIO_SECR_SEC10_Msk -#define GPIO_SECR_SEC11_Pos (11U) -#define GPIO_SECR_SEC11_Msk (0x1U << GPIO_SECR_SEC11_Pos) /*!< 0x00000800 */ -#define GPIO_SECR_SEC11 GPIO_SECR_SEC11_Msk -#define GPIO_SECR_SEC12_Pos (12U) -#define GPIO_SECR_SEC12_Msk (0x1U << GPIO_SECR_SEC12_Pos) /*!< 0x00001000 */ -#define GPIO_SECR_SEC12 GPIO_SECR_SEC12_Msk -#define GPIO_SECR_SEC13_Pos (13U) -#define GPIO_SECR_SEC13_Msk (0x1U << GPIO_SECR_SEC13_Pos) /*!< 0x00002000 */ -#define GPIO_SECR_SEC13 GPIO_SECR_SEC13_Msk -#define GPIO_SECR_SEC14_Pos (14U) -#define GPIO_SECR_SEC14_Msk (0x1U << GPIO_SECR_SEC14_Pos) /*!< 0x00004000 */ -#define GPIO_SECR_SEC14 GPIO_SECR_SEC14_Msk -#define GPIO_SECR_SEC15_Pos (15U) -#define GPIO_SECR_SEC15_Msk (0x1U << GPIO_SECR_SEC15_Pos) /*!< 0x00008000 */ -#define GPIO_SECR_SEC15 GPIO_SECR_SEC15_Msk +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk + +/*************** Bit definition for GPIO_HWCFGR10 register ****************/ +#define GPIO_HWCFGR10_AHB_IOP_Pos (0U) +#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */ +#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR10_AF_SIZE_Pos (4U) +#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */ +#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U) +#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */ +#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U) +#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */ +#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR10_SEC_CFG_Pos (16U) +#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */ +#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR10_OR_CFG_Pos (20U) +#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */ +#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for GPIO_HWCFGR9 register ****************/ +#define GPIO_HWCFGR9_EN_IO_Pos (0U) +#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */ +#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for GPIO_HWCFGR8 register ****************/ +#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U) +#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U) +#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U) +#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U) +#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U) +#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U) +#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U) +#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U) +#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */ +#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR7 register ****************/ +#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U) +#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */ +#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U) +#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */ +#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U) +#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */ +#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U) +#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */ +#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U) +#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */ +#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U) +#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */ +#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U) +#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */ +#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U) +#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */ +#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */ +#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR6 register ****************/ +#define GPIO_HWCFGR6_MODER_RES_Pos (0U) +#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */ +#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR5 register ****************/ +#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U) +#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */ +#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR4 register ****************/ +#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U) +#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */ +#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR3 register ****************/ +#define GPIO_HWCFGR3_ODR_RES_Pos (0U) +#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */ +#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U) +#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */ +#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */ +#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR2 register ****************/ +#define GPIO_HWCFGR2_AFRL_RES_Pos (0U) +#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */ +#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR1 register ****************/ +#define GPIO_HWCFGR1_AFRH_RES_Pos (0U) +#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */ +#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */ +#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */ +#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */ +#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */ +#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */ +#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */ +#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */ +#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */ +#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */ +#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */ +#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */ +#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */ +#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */ +#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */ +#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */ +#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */ +#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for GPIO_HWCFGR0 register ****************/ +#define GPIO_HWCFGR0_OR_RES_Pos (0U) +#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */ +#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */ +#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */ +#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */ +#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */ +#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */ +#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */ +#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */ +#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */ +#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */ +#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */ +#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */ +#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */ +#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */ +#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */ +#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */ +#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */ +#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */ /********************** Bit definition for GPIO_VERR register *****************/ #define GPIO_VERR_MINREV_Pos (0U) @@ -23754,20 +24056,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* * @brief Specific device feature definitions */ -//#define RTC_TAMPER1_SUPPORT -//#define RTC_TAMPER2_SUPPORT -//#define RTC_TAMPER3_SUPPORT - -//#define RTC_BACKUP_SUPPORT -//#define RTC_BACKUP32_SUPPORT -//#define RTC_BACKUP128_SUPPORT - -#define RTC_CPU2_SUPPORT //not for G0, only first wb trials - -#define RTC_WAKEUP_SUPPORT -#define RTC_INTERNALTS_SUPPORT - -#define RTC_SECUREMODE_SUPPORT /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) @@ -23862,33 +24150,33 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SSR_SS RTC_SSR_SS_Msk /**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/ -#define RTC_ISR_RECALPF_Pos (16U) -#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ -#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk -#define RTC_ISR_INIT_Pos (7U) -#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ -#define RTC_ISR_INIT RTC_ISR_INIT_Msk -#define RTC_ISR_INITF_Pos (6U) -#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ -#define RTC_ISR_INITF RTC_ISR_INITF_Msk -#define RTC_ISR_RSF_Pos (5U) -#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ -#define RTC_ISR_RSF RTC_ISR_RSF_Msk -#define RTC_ISR_INITS_Pos (4U) -#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ -#define RTC_ISR_INITS RTC_ISR_INITS_Msk -#define RTC_ISR_SHPF_Pos (3U) -#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ -#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk -#define RTC_ISR_WUTWF_Pos (2U) -#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ -#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk -#define RTC_ISR_ALRBWF_Pos (1U) -#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ -#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk -#define RTC_ISR_ALRAWF_Pos (0U) -#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ -#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ @@ -23914,7 +24202,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_TAMPALRM_PU_Pos (29U) #define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk - #define RTC_CR_TAMPOE_Pos (26U) #define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk @@ -23938,9 +24225,9 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk -#define RTC_CR_BCK_Pos (18U) -#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ -#define RTC_CR_BCK RTC_CR_BCK_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk @@ -23991,12 +24278,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /******************** Bits definition for RTC_SMCR register *******************/ -#define RTC_SMCR_ERREN_Pos (31U) -#define RTC_SMCR_ERREN_Msk (0x1U << RTC_SMCR_ERREN_Pos) /*!< 0x80000000 */ -#define RTC_SMCR_ERREN RTC_SMCR_ERREN_Msk -#define RTC_SMCR_ERRMODE_Pos (30U) -#define RTC_SMCR_ERRMODE_Msk (0x1U << RTC_SMCR_ERRMODE_Pos) /*!< 0x40000000 */ -#define RTC_SMCR_ERRMODE RTC_SMCR_ERRMODE_Msk #define RTC_SMCR_DECPROT_Pos (15U) #define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */ #define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk @@ -24298,9 +24579,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_SR register *************/ -#define RTC_SR_SERRF_Pos (15U) -#define RTC_SR_SERRF_Msk (0x1U << RTC_SR_SERRF_Pos) /*!< 0x00008000 */ -#define RTC_SR_SERRF RTC_SR_SERRF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk @@ -24341,9 +24619,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk /******************** Bits definition for RTC_SMISR register *************/ -#define RTC_SMISR_SERRMF_Pos (15U) -#define RTC_SMISR_SERRMF_Msk (0x1U << RTC_SMISR_SERRMF_Pos) /*!< 0x00008000 */ -#define RTC_SMISR_SERRMF RTC_SMISR_SERRMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk @@ -24364,9 +24639,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk /******************** Bits definition for RTC_SCR register *************/ -#define RTC_SCR_CSERRF_Pos (15U) -#define RTC_SCR_CSERRF_Msk (0x1U << RTC_SCR_CSERRF_Pos) /*!< 0x00008000 */ -#define RTC_SCR_CSERRF RTC_SCR_CSERRF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk @@ -24387,9 +24659,14 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk /******************** Bits definition for RTC_OR register ****************/ -#define RTC_OR_OUT2_RMP_Pos (0U) -#define RTC_OR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ -#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk +#define RTC_CFGR_LSCOEN_Pos (1U) +#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */ +#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk +#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */ +#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */ +#define RTC_CFGR_OUT2_RMP_Pos (0U) +#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_HWCFGR register *************/ @@ -24477,22 +24754,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /* Tamper and Backup registers (TAMP) */ /* */ /******************************************************************************/ -#define TAMP_TAMPER1_SUPPORT -#define TAMP_TAMPER2_SUPPORT -#define TAMP_TAMPER3_SUPPORT - -#define TAMP_TAMPER8_SUPPORT -#define TAMP_INT_TAMPER16_SUPPORT - -#define TAMP_BACKUP_SUPPORT -#define TAMP_BACKUP32_SUPPORT -#define TAMP_BACKUP128_SUPPORT - -#define TAMP_CPU2_SUPPORT /******************** Bits definition for TAMP_CR1 register ***************/ #define TAMP_CR1_TAMPE_Pos (0U) -#define TAMP_CR1_TAMPE_Msk (0xFFU << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ +#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */ #define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ @@ -24503,23 +24768,8 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1U << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1U << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1U << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1U << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1U << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMPE_Pos (16U) -#define TAMP_CR1_ITAMPE_Msk (0xFFFFU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ +#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */ #define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ @@ -24536,124 +24786,48 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1U << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1U << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1U << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP10E_Pos (25U) -#define TAMP_CR1_ITAMP10E_Msk (0x1U << TAMP_CR1_ITAMP10E_Pos) /*!< 0x02000000 */ -#define TAMP_CR1_ITAMP10E TAMP_CR1_ITAMP10E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1U << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (23U) -#define TAMP_CR1_ITAMP12E_Msk (0x1U << TAMP_CR1_ITAMP12E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1U << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk -#define TAMP_CR1_ITAMP14E_Pos (29U) -#define TAMP_CR1_ITAMP14E_Msk (0x1U << TAMP_CR1_ITAMP14E_Pos) /*!< 0x20000000 */ -#define TAMP_CR1_ITAMP14E TAMP_CR1_ITAMP14E_Msk -#define TAMP_CR1_ITAMP15E_Pos (30U) -#define TAMP_CR1_ITAMP15E_Msk (0x1U << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ -#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk -#define TAMP_CR1_ITAMP16E_Pos (31U) -#define TAMP_CR1_ITAMP16E_Msk (0x1U << TAMP_CR1_ITAMP16E_Pos) /*!< 0x80000000 */ -#define TAMP_CR1_ITAMP16E TAMP_CR1_ITAMP16E_Msk - /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOER_Pos (0U) -#define TAMP_CR2_TAMPNOER_Msk (0xFFU << TAMP_CR2_TAMPNOER_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOER_Msk -#define TAMP_CR2_TAMP1NOER_Pos (0U) -#define TAMP_CR2_TAMP1NOER_Msk (0x1U << TAMP_CR2_TAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOER TAMP_CR2_TAMP1NOER_Msk -#define TAMP_CR2_TAMP2NOER_Pos (1U) -#define TAMP_CR2_TAMP2NOER_Msk (0x1U << TAMP_CR2_TAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOER TAMP_CR2_TAMP2NOER_Msk -#define TAMP_CR2_TAMP3NOER_Pos (2U) -#define TAMP_CR2_TAMP3NOER_Msk (0x1U << TAMP_CR2_TAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOER TAMP_CR2_TAMP3NOER_Msk -#define TAMP_CR2_TAMP4NOER_Pos (3U) -#define TAMP_CR2_TAMP4NOER_Msk (0x1U << TAMP_CR2_TAMP4NOER_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOER TAMP_CR2_TAMP4NOER_Msk -#define TAMP_CR2_TAMP5NOER_Pos (4U) -#define TAMP_CR2_TAMP5NOER_Msk (0x1U << TAMP_CR2_TAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOER TAMP_CR2_TAMP5NOER_Msk -#define TAMP_CR2_TAMP6NOER_Pos (5U) -#define TAMP_CR2_TAMP6NOER_Msk (0x1U << TAMP_CR2_TAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOER TAMP_CR2_TAMP6NOER_Msk -#define TAMP_CR2_TAMP7NOER_Pos (6U) -#define TAMP_CR2_TAMP7NOER_Msk (0x1U << TAMP_CR2_TAMP7NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOER TAMP_CR2_TAMP7NOER_Msk -#define TAMP_CR2_TAMP8NOER_Pos (7U) -#define TAMP_CR2_TAMP8NOER_Msk (0x1U << TAMP_CR2_TAMP8NOER_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOER TAMP_CR2_TAMP8NOER_Msk -#define TAMP_CR2_TAMPMF_Pos (16U) -#define TAMP_CR2_TAMPMF_Msk (0xFFU << TAMP_CR2_TAMPMF_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMF TAMP_CR2_TAMPMF_Msk -#define TAMP_CR2_TAMP1MF_Pos (16U) -#define TAMP_CR2_TAMP1MF_Msk (0x1U << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk -#define TAMP_CR2_TAMP2MF_Pos (17U) -#define TAMP_CR2_TAMP2MF_Msk (0x1U << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk -#define TAMP_CR2_TAMP3MF_Pos (18U) -#define TAMP_CR2_TAMP3MF_Msk (0x1U << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk -#define TAMP_CR2_TAMP4MF_Pos (19U) -#define TAMP_CR2_TAMP4MF_Msk (0x1U << TAMP_CR2_TAMP4MF_Pos) /*!< 0x00080000 */ -#define TAMP_CR2_TAMP4MF TAMP_CR2_TAMP4MF_Msk -#define TAMP_CR2_TAMP5MF_Pos (20U) -#define TAMP_CR2_TAMP5MF_Msk (0x1U << TAMP_CR2_TAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_CR2_TAMP5MF TAMP_CR2_TAMP5MF_Msk -#define TAMP_CR2_TAMP6MF_Pos (21U) -#define TAMP_CR2_TAMP6MF_Msk (0x1U << TAMP_CR2_TAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_CR2_TAMP6MF TAMP_CR2_TAMP6MF_Msk -#define TAMP_CR2_TAMP7MF_Pos (22U) -#define TAMP_CR2_TAMP7MF_Msk (0x1U << TAMP_CR2_TAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_CR2_TAMP7MF TAMP_CR2_TAMP7MF_Msk -#define TAMP_CR2_TAMP8MF_Pos (23U) -#define TAMP_CR2_TAMP8MF_Msk (0x1U << TAMP_CR2_TAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_TAMP8MF TAMP_CR2_TAMP8MF_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1U << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x08000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1U << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x10000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1U << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x20000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1U << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x40000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1U << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x80000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24677,72 +24851,72 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk -/******************** Bits definition for TAMP_ATCR register ***************/ -#define TAMP_ATCR_TAMPAE_Pos (0U) -#define TAMP_ATCR_TAMPAE_Msk (0xFFU << TAMP_ATCR_TAMPAE_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR_TAMPAE TAMP_ATCR_TAMPAE_Msk -#define TAMP_ATCR_TAMP1AE_Pos (0U) -#define TAMP_ATCR_TAMP1AE_Msk (0x1U << TAMP_ATCR_TAMP1AE_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR_TAMP1AE TAMP_ATCR_TAMP1AE_Msk -#define TAMP_ATCR_TAMP2AE_Pos (1U) -#define TAMP_ATCR_TAMP2AE_Msk (0x1U << TAMP_ATCR_TAMP2AE_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR_TAMP2AE TAMP_ATCR_TAMP2AE_Msk -#define TAMP_ATCR_TAMP3AE_Pos (2U) -#define TAMP_ATCR_TAMP3AE_Msk (0x1U << TAMP_ATCR_TAMP3AE_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR_TAMP3AE TAMP_ATCR_TAMP3AE_Msk -#define TAMP_ATCR_TAMP4AE_Pos (3U) -#define TAMP_ATCR_TAMP4AE_Msk (0x1U << TAMP_ATCR_TAMP4AE_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR_TAMP4AE TAMP_ATCR_TAMP4AE_Msk -#define TAMP_ATCR_TAMP5AE_Pos (4U) -#define TAMP_ATCR_TAMP5AE_Msk (0x1U << TAMP_ATCR_TAMP5AE_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR_TAMP5AE TAMP_ATCR_TAMP5AE_Msk -#define TAMP_ATCR_TAMP6AE_Pos (5U) -#define TAMP_ATCR_TAMP6AE_Msk (0x1U << TAMP_ATCR_TAMP6AE_Pos) /*!< 0x00000020 */ -#define TAMP_ATCR_TAMP6AE TAMP_ATCR_TAMP6AE_Msk -#define TAMP_ATCR_TAMP7AE_Pos (6U) -#define TAMP_ATCR_TAMP7AE_Msk (0x1U << TAMP_ATCR_TAMP7AE_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR_TAMP7AE TAMP_ATCR_TAMP7AE_Msk -#define TAMP_ATCR_TAMP8AE_Pos (7U) -#define TAMP_ATCR_TAMP8AE_Msk (0x1U << TAMP_ATCR_TAMP8AE_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR_TAMP8AE TAMP_ATCR_TAMP8AE_Msk -#define TAMP_ATCR_ATOSEL1_Pos (8U) -#define TAMP_ATCR_ATOSEL1_Msk (0x3U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR_ATOSEL1 TAMP_ATCR_ATOSEL1_Msk -#define TAMP_ATCR_ATOSEL1_0 (0x1U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR_ATOSEL1_1 (0x2U << TAMP_ATCR_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR_ATOSEL2_Pos (10U) -#define TAMP_ATCR_ATOSEL2_Msk (0x3U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR_ATOSEL2 TAMP_ATCR_ATOSEL2_Msk -#define TAMP_ATCR_ATOSEL2_0 (0x1U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR_ATOSEL2_1 (0x2U << TAMP_ATCR_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR_ATOSEL3_Pos (12U) -#define TAMP_ATCR_ATOSEL3_Msk (0x3U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR_ATOSEL3 TAMP_ATCR_ATOSEL3_Msk -#define TAMP_ATCR_ATOSEL3_0 (0x1U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR_ATOSEL3_1 (0x2U << TAMP_ATCR_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR_ATOSEL4_Pos (14U) -#define TAMP_ATCR_ATOSEL4_Msk (0x3U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR_ATOSEL4 TAMP_ATCR_ATOSEL4_Msk -#define TAMP_ATCR_ATOSEL4_0 (0x1U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR_ATOSEL4_1 (0x2U << TAMP_ATCR_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR_ATCKSEL_Pos (16U) -#define TAMP_ATCR_ATCKSEL_Msk (0x7U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00070000 */ -#define TAMP_ATCR_ATCKSEL TAMP_ATCR_ATCKSEL_Msk -#define TAMP_ATCR_ATCKSEL_0 (0x1U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR_ATCKSEL_1 (0x2U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR_ATCKSEL_2 (0x4U << TAMP_ATCR_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR_ATPER_Pos (24U) -#define TAMP_ATCR_ATPER_Msk (0x7U << TAMP_ATCR_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR_ATPER TAMP_ATCR_ATPER_Msk -#define TAMP_ATCR_ATPER_0 (0x1U << TAMP_ATCR_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR_ATPER_1 (0x2U << TAMP_ATCR_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR_ATPER_2 (0x4U << TAMP_ATCR_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR_ATOSHARE_Pos (30U) -#define TAMP_ATCR_ATOSHARE_Msk (0x1U << TAMP_ATCR_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR_ATOSHARE TAMP_ATCR_ATOSHARE_Msk -#define TAMP_ATCR_FLTEN_Pos (31U) -#define TAMP_ATCR_FLTEN_Msk (0x1U << TAMP_ATCR_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR_FLTEN TAMP_ATCR_FLTEN_Msk +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMPAM_Pos (0U) +#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ +#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp157dxx_ca7 + * @{ + */ + +#ifndef __STM32MP157Dxx_CA7_H +#define __STM32MP157Dxx_CA7_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-A Processor Specific Interrupt Numbers ***************************************************************/ + /* Software Generated Interrupts */ + SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ + SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ + SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ + SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ + SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ + SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ + SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ + SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ + SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ + SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ + SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ + SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ + SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ + SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ + SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ + SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ + /* Private Peripheral Interrupts */ + VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ + Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ + SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ + NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ + Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ + WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_36 = 36, /*!< RESERVED interrupt */ + RCC_IRQn = 37, /*!< RCC global Interrupt */ + EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 40, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 41, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 42, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 43, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 44, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 45, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 46, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 47, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 48, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 49, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 50, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 51, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 52, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 53, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 54, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 55, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 56, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 57, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 58, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 59, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 60, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 61, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 62, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 63, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 64, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 65, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 66, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 67, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 68, /*!< SPI2 global Interrupt */ + USART1_IRQn = 69, /*!< USART1 global Interrupt */ + USART2_IRQn = 70, /*!< USART2 global Interrupt */ + USART3_IRQn = 71, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 72, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 73, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 74, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 75, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 76, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 77, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 78, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 79, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 80, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 81, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 82, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 83, /*!< SPI3 global Interrupt */ + UART4_IRQn = 84, /*!< UART4 global Interrupt */ + UART5_IRQn = 85, /*!< UART5 global Interrupt */ + TIM6_IRQn = 86, /*!< TIM6 global */ + TIM7_IRQn = 87, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 88, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 89, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 90, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 91, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 92, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 93, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 94, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 95, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 96, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 97, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 98, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 99, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 100, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 101, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 102, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 103, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 106, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 107, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 108, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 109, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 110, /*!< DCMI global interrupt */ + RESERVED_111 = 111, /*!< reserved */ + HASH1_IRQn = 112, /*!< Hash global interrupt */ + RESERVED_113 = 113, /*!< reserved */ + UART7_IRQn = 114, /*!< UART7 global interrupt */ + UART8_IRQn = 115, /*!< UART8 global interrupt */ + SPI4_IRQn = 116, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 117, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 118, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 119, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 120, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 121, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 122, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 123, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 124, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 125, /*!< LP TIM1 interrupt */ + CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 127, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 128, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 130, /*!< USB On The Go global interrupt */ + RESERVED_131 = 131, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 132, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 133, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 134, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 135, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 136, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + RESERVED_137 = 137, /*!< reserved */ + HASH2_IRQn = 138, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 139, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 140, /*!< I2C5 Error Interrupt */ + GPU_IRQn = 141, /*!< GPU global Interrupt */ + DFSDM1_FLT0_IRQn = 142, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 143, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 144, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 145, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 146, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 147, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 148, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 149, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 150, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 151, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 152, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 153, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 154, /*!< MDMA global Interrupt */ + DSI_IRQn = 155, /*!< DSI global Interrupt */ + SDMMC2_IRQn = 156, /*!< SDMMC2 global Interrupt */ + HSEM_IT1_IRQn = 157, /*!< HSEM Semaphore Interrupt 1 */ + DFSDM1_FLT5_IRQn = 158, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 159, /*!< EXTI Line 15 Interrupts */ + MDMA_SEC_IT_IRQn = 160, /*!< MDMA global Secure interrupt */ + SYSRESETQ_IRQn = 161, /*!< MCU local Reset Request */ + TIM13_IRQn = 162, /*!< TIM13 global interrupt */ + TIM14_IRQn = 163, /*!< TIM14 global interrupt */ + DAC_IRQn = 164, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 165, /*!< RNG1 interrupt */ + RNG2_IRQn = 166, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 167, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 168, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 169, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 170, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 171, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 172, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 173, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 174, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + WWDG1_RST = 175, /*!< Window Watchdog 1 Reset through AIEC */ + MCU_SEV_IRQn = 176, /*!< MCU Send Event interrupt */ + RCC_WAKEUP_IRQn = 177, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 178, /*!< SAI4 global interrupt */ + DTS_IRQn = 179, /*!< Temperature sensor Global Interrupt */ + RESERVED_180 = 180, /*!< reserved */ + WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins */ + IWDG1_IRQn = 182, /*!< IWDG1 Early Interrupt */ + IWDG2_IRQn = 183, /*!< IWDG2 Early Interrupt */ + TAMP_SERR_S_IRQn = 229, /*!< TAMP Tamper and Security Error Secure interrupts */ + RTC_WKUP_ALARM_S_IRQn = 230, /*!< RTC Wakeup Timer and Alarms (A and B) Secure interrupt */ + RTC_TS_SERR_S_IRQn = 231, /*!< RTC TimeStamp and Security Error Secure interrupt */ + MAX_IRQ_n, + Force_IRQn_enum_size = 1048 /* Dummy entry to ensure IRQn_Type is more than 8 bits. Otherwise GIC init loop would fail */ + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals ============================ */ +#define __CORTEX_A 7U /*!< Cortex-A# Core */ +#define __CA_REV 0x0005U /*!< Core revision r0p0 */ +#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */ +#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */ +#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */ +#define __L2C_PRESENT 0U /*!< Set to 1 if L2C is present */ + +#define GIC_BASE 0xA0021000 +#define GIC_DISTRIBUTOR_BASE GIC_BASE +#define GIC_INTERFACE_BASE (GIC_BASE+0x1000) + +#include "core_ca.h" +#include "system_stm32mp1xx_A7.h" + + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DSI Controller + */ + +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED3[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED4[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED6; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED8[11]; /*!< Reserved, 0x164 - 0x18F */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + uint32_t RESERVED9[155]; /*!< Reserved, 0x194 - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED10; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[2]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-41C */ + uint32_t RESERVED11[4]; /*!< Reserved, 0x420 - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t RESERVED12[239]; /*!< Reserved, 0x434 - 0x7EC */ + __IO uint32_t HWCFGR; /*!< DSI Host hardware configuration register, Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DSI Host version register, Address offset: 0x7F4 */ + __IO uint32_t IPIDR; /*!< DSI Host Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DSI Host Size ID register, Address offset: 0x7FC */ +} DSI_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* DSI VERSION ********************************/ +#define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP157Dxx_CA7_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h new file mode 100644 index 0000000000..738f3c8712 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h @@ -0,0 +1,31839 @@ +/** + ****************************************************************************** + * @file stm32mp157dxx_cm4.h + * @author MCD Application Team + * @brief CMSIS stm32mp157dxx_cm4 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp157dxx_cm4 + * @{ + */ + +#ifndef __STM32MP157Dxx_CM4_H +#define __STM32MP157Dxx_CM4_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-M Processor Exceptions Numbers *******************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers ************************************************************************/ + WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_4 = 4, /*!< RESERVED interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + RESERVED_79 = 79, /*!< RESERVED interrupt */ + HASH1_IRQn = 80, /*!< Hash global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 90, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 98, /*!< USB On The Go global interrupt */ + RESERVED_99 = 99, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + RESERVED_105 = 105, /*!< RESERVED interrupt */ + HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */ + GPU_IRQn = 109, /*!< GPU global Interrupt */ + DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 114, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 119, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 122, /*!< MDMA global Interrupt */ + DSI_IRQn = 123, /*!< DSI global Interrupt */ + SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */ + HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */ + DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */ + nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */ + nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 133, /*!< RNG1 interrupt */ + RNG2_IRQn = 134, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + RESERVED_143 = 143, /*!< RESERVED interrupt */ + MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */ + RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 146, /*!< SAI4 global interrupt */ + DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */ + RESERVED_148 = 148, /*!< RESERVED interrupt */ + WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */ + MAX_IRQ_n + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_stm32mp1xx.h" + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DSI Controller + */ + +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED3[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED4[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED6; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED8[11]; /*!< Reserved, 0x164 - 0x18F */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + uint32_t RESERVED9[155]; /*!< Reserved, 0x194 - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED10; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[2]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-41C */ + uint32_t RESERVED11[4]; /*!< Reserved, 0x420 - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t RESERVED12[239]; /*!< Reserved, 0x434 - 0x7EC */ + __IO uint32_t HWCFGR; /*!< DSI Host hardware configuration register, Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DSI Host version register, Address offset: 0x7F4 */ + __IO uint32_t IPIDR; /*!< DSI Host Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DSI Host Size ID register, Address offset: 0x7FC */ +} DSI_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* DSI VERSION ********************************/ +#define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP157Dxx_CM4_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h new file mode 100644 index 0000000000..60ae69a3f1 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h @@ -0,0 +1,32084 @@ +/** + ****************************************************************************** + * @file stm32mp157fxx_ca7.h + * @author MCD Application Team + * @brief CMSIS stm32mp157fxx_ca7 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp157fxx_ca7 + * @{ + */ + +#ifndef __STM32MP157Fxx_CA7_H +#define __STM32MP157Fxx_CA7_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-A Processor Specific Interrupt Numbers ***************************************************************/ + /* Software Generated Interrupts */ + SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ + SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ + SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ + SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ + SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ + SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ + SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ + SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ + SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ + SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ + SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ + SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ + SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ + SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ + SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ + SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ + /* Private Peripheral Interrupts */ + VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ + Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ + SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ + NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ + Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ + WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_36 = 36, /*!< RESERVED interrupt */ + RCC_IRQn = 37, /*!< RCC global Interrupt */ + EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 40, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 41, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 42, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 43, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 44, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 45, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 46, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 47, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 48, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 49, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 50, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 51, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 52, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 53, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 54, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 55, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 56, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 57, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 58, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 59, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 60, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 61, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 62, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 63, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 64, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 65, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 66, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 67, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 68, /*!< SPI2 global Interrupt */ + USART1_IRQn = 69, /*!< USART1 global Interrupt */ + USART2_IRQn = 70, /*!< USART2 global Interrupt */ + USART3_IRQn = 71, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 72, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 73, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 74, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 75, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 76, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 77, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 78, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 79, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 80, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 81, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 82, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 83, /*!< SPI3 global Interrupt */ + UART4_IRQn = 84, /*!< UART4 global Interrupt */ + UART5_IRQn = 85, /*!< UART5 global Interrupt */ + TIM6_IRQn = 86, /*!< TIM6 global */ + TIM7_IRQn = 87, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 88, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 89, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 90, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 91, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 92, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 93, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 94, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 95, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 96, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 97, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 98, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 99, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 100, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 101, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 102, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 103, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 106, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 107, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 108, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 109, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 110, /*!< DCMI global interrupt */ + CRYP1_IRQn = 111, /*!< CRYP crypto global interrupt */ + HASH1_IRQn = 112, /*!< Hash global interrupt */ + RESERVED_113 = 113, /*!< reserved */ + UART7_IRQn = 114, /*!< UART7 global interrupt */ + UART8_IRQn = 115, /*!< UART8 global interrupt */ + SPI4_IRQn = 116, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 117, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 118, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 119, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 120, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 121, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 122, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 123, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 124, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 125, /*!< LP TIM1 interrupt */ + CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 127, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 128, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 130, /*!< USB On The Go global interrupt */ + RESERVED_131 = 131, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 132, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 133, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 134, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 135, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 136, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + CRYP2_IRQn = 137, /*!< CRYP2 crypto global interrupt */ + HASH2_IRQn = 138, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 139, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 140, /*!< I2C5 Error Interrupt */ + GPU_IRQn = 141, /*!< GPU global Interrupt */ + DFSDM1_FLT0_IRQn = 142, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 143, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 144, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 145, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 146, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 147, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 148, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 149, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 150, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 151, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 152, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 153, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 154, /*!< MDMA global Interrupt */ + DSI_IRQn = 155, /*!< DSI global Interrupt */ + SDMMC2_IRQn = 156, /*!< SDMMC2 global Interrupt */ + HSEM_IT1_IRQn = 157, /*!< HSEM Semaphore Interrupt 1 */ + DFSDM1_FLT5_IRQn = 158, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 159, /*!< EXTI Line 15 Interrupts */ + MDMA_SEC_IT_IRQn = 160, /*!< MDMA global Secure interrupt */ + SYSRESETQ_IRQn = 161, /*!< MCU local Reset Request */ + TIM13_IRQn = 162, /*!< TIM13 global interrupt */ + TIM14_IRQn = 163, /*!< TIM14 global interrupt */ + DAC_IRQn = 164, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 165, /*!< RNG1 interrupt */ + RNG2_IRQn = 166, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 167, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 168, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 169, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 170, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 171, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 172, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 173, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 174, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + WWDG1_RST = 175, /*!< Window Watchdog 1 Reset through AIEC */ + MCU_SEV_IRQn = 176, /*!< MCU Send Event interrupt */ + RCC_WAKEUP_IRQn = 177, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 178, /*!< SAI4 global interrupt */ + DTS_IRQn = 179, /*!< Temperature sensor Global Interrupt */ + RESERVED_180 = 180, /*!< reserved */ + WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins */ + IWDG1_IRQn = 182, /*!< IWDG1 Early Interrupt */ + IWDG2_IRQn = 183, /*!< IWDG2 Early Interrupt */ + TAMP_SERR_S_IRQn = 229, /*!< TAMP Tamper and Security Error Secure interrupts */ + RTC_WKUP_ALARM_S_IRQn = 230, /*!< RTC Wakeup Timer and Alarms (A and B) Secure interrupt */ + RTC_TS_SERR_S_IRQn = 231, /*!< RTC TimeStamp and Security Error Secure interrupt */ + MAX_IRQ_n, + Force_IRQn_enum_size = 1048 /* Dummy entry to ensure IRQn_Type is more than 8 bits. Otherwise GIC init loop would fail */ + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals ============================ */ +#define __CORTEX_A 7U /*!< Cortex-A# Core */ +#define __CA_REV 0x0005U /*!< Core revision r0p0 */ +#define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */ +#define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */ +#define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */ +#define __L2C_PRESENT 0U /*!< Set to 1 if L2C is present */ + +#define GIC_BASE 0xA0021000 +#define GIC_DISTRIBUTOR_BASE GIC_BASE +#define GIC_INTERFACE_BASE (GIC_BASE+0x1000) + +#include "core_ca.h" +#include "system_stm32mp1xx_A7.h" + + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DSI Controller + */ + +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED3[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED4[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED6; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED8[11]; /*!< Reserved, 0x164 - 0x18F */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + uint32_t RESERVED9[155]; /*!< Reserved, 0x194 - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED10; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[2]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-41C */ + uint32_t RESERVED11[4]; /*!< Reserved, 0x420 - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t RESERVED12[239]; /*!< Reserved, 0x434 - 0x7EC */ + __IO uint32_t HWCFGR; /*!< DSI Host hardware configuration register, Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DSI Host version register, Address offset: 0x7F4 */ + __IO uint32_t IPIDR; /*!< DSI Host Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DSI Host Size ID register, Address offset: 0x7FC */ +} DSI_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* CRYP VERSION ********************************/ +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* DSI VERSION ********************************/ +#define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP157Fxx_CA7_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h new file mode 100644 index 0000000000..7e58d59ec3 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h @@ -0,0 +1,32050 @@ +/** + ****************************************************************************** + * @file stm32mp157fxx_cm4.h + * @author MCD Application Team + * @brief CMSIS stm32mp157fxx_cm4 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp157fxx_cm4 + * @{ + */ + +#ifndef __STM32MP157Fxx_CM4_H +#define __STM32MP157Fxx_CM4_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-M Processor Exceptions Numbers *******************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers ************************************************************************/ + WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_4 = 4, /*!< RESERVED interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP1_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH1_IRQn = 80, /*!< Hash global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 90, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 98, /*!< USB On The Go global interrupt */ + RESERVED_99 = 99, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + CRYP2_IRQn = 105, /*!< CRYP2 crypto global interrupt */ + HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */ + GPU_IRQn = 109, /*!< GPU global Interrupt */ + DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 114, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 119, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 122, /*!< MDMA global Interrupt */ + DSI_IRQn = 123, /*!< DSI global Interrupt */ + SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */ + HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */ + DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */ + nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */ + nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 133, /*!< RNG1 interrupt */ + RNG2_IRQn = 134, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + RESERVED_143 = 143, /*!< RESERVED interrupt */ + MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */ + RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 146, /*!< SAI4 global interrupt */ + DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */ + RESERVED_148 = 148, /*!< RESERVED interrupt */ + WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */ + MAX_IRQ_n + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_stm32mp1xx.h" + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DSI Controller + */ + +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED3[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED4[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED6; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED8[11]; /*!< Reserved, 0x164 - 0x18F */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + uint32_t RESERVED9[155]; /*!< Reserved, 0x194 - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED10; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[2]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-41C */ + uint32_t RESERVED11[4]; /*!< Reserved, 0x420 - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t RESERVED12[239]; /*!< Reserved, 0x434 - 0x7EC */ + __IO uint32_t HWCFGR; /*!< DSI Host hardware configuration register, Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DSI Host version register, Address offset: 0x7F4 */ + __IO uint32_t IPIDR; /*!< DSI Host Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DSI Host Size ID register, Address offset: 0x7FC */ +} DSI_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* CRYP VERSION ********************************/ +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* DSI VERSION ********************************/ +#define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP157Fxx_CM4_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h index 528b9b91c3..e42480693f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h @@ -8,37 +8,21 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32MP1xx device used in the target application - * - To use or not the peripheral�s drivers in application code(i.e. - * code will be based on direct access to peripheral�s registers + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -86,7 +70,7 @@ * @brief CMSIS Device version number */ #define __STM32MP1xx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32MP1xx_CMSIS_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32MP1xx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ #define __STM32MP1xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32MP1xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32MP1xx_CMSIS_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ @@ -108,14 +92,26 @@ #include "stm32mp157axx_cm4.h" #elif defined(STM32MP157Cxx) #include "stm32mp157cxx_cm4.h" +#elif defined(STM32MP157Dxx) + #include "stm32mp157dxx_cm4.h" +#elif defined(STM32MP157Fxx) + #include "stm32mp157fxx_cm4.h" #elif defined(STM32MP153Axx) #include "stm32mp153axx_cm4.h" #elif defined(STM32MP153Cxx) #include "stm32mp153cxx_cm4.h" +#elif defined(STM32MP153Dxx) + #include "stm32mp153dxx_cm4.h" +#elif defined(STM32MP153Fxx) + #include "stm32mp153fxx_cm4.h" #elif defined(STM32MP151Axx) #include "stm32mp151axx_cm4.h" #elif defined(STM32MP151Cxx) #include "stm32mp151cxx_cm4.h" +#elif defined(STM32MP151Dxx) + #include "stm32mp151dxx_cm4.h" +#elif defined(STM32MP151Fxx) + #include "stm32mp151fxx_cm4.h" #else #error "Please select first the target STM32MP1xx device used in your application (in stm32mp1xx.h file)" #endif @@ -128,14 +124,26 @@ #include "stm32mp157axx_ca7.h" #elif defined(STM32MP157Cxx) #include "stm32mp157cxx_ca7.h" +#elif defined(STM32MP157Dxx) + #include "stm32mp157dxx_ca7.h" +#elif defined(STM32MP157Fxx) + #include "stm32mp157fxx_ca7.h" #elif defined(STM32MP153Axx) #include "stm32mp153axx_ca7.h" #elif defined(STM32MP153Cxx) #include "stm32mp153cxx_ca7.h" +#elif defined(STM32MP153Dxx) + #include "stm32mp153dxx_ca7.h" +#elif defined(STM32MP153Fxx) + #include "stm32mp153fxx_ca7.h" #elif defined(STM32MP151Axx) #include "stm32mp151axx_ca7.h" #elif defined(STM32MP151Cxx) #include "stm32mp151cxx_ca7.h" +#elif defined(STM32MP151Dxx) + #include "stm32mp151dxx_ca7.h" +#elif defined(STM32MP151Fxx) + #include "stm32mp151fxx_ca7.h" #else #error "Please select first the target STM32MP1xx device used in your application (in stm32mp1xx.h file)" #endif diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h index e9e849fc35..7d22efc319 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html index b848f38881..70a7bf7f9d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html @@ -163,15 +163,16 @@

License

-

V1.1.1 / 14-November-2019

+

V1.2.0 / 03-Feb-2020

-

Main changes

  • Patch release to fix known defects 
    • Align Header file with TIM driver ( Break Source definition)
    • Update Linker Template file to define OpenAMP region ( for EWARM and MDK_ARM)
+

Main changes

+
  • Header files: 
    • Add new Part Number for 800MHz
    • Update license with BSD 3-Clause template
    • Rework CMSIS for RTC/TAMP, GPIO and TIM
    • Rename TIM Break source bit definition
  • Update Linker Template file for KEIL and IAR:
    • Add OpenAMP region ( region present by default, to comment if needed )

Contents

    -
  • CMSIS devices files for STM32MP151Cxx ,STM32MP151Axx, STM32MP153Cxx, STM32MP153Axx, STM32MP157Cxx ,STM32MP157Axx
    +
  • CMSIS devices files for:
    • STM32MP151Cxx ,STM32MP151Axx, STM32MP151Dxx ,STM32MP151Fxx
    • STM32MP153Cxx ,STM32MP153Axx, STM32MP153Dxx ,STM32MP153Fxx
    • STM32MP157Cxx ,STM32MP157Axx, STM32MP157Dxx ,STM32MP157Fxx
@@ -180,7 +181,7 @@

Contents