From b32b9120cfb61ece3285603fc3afefa40a5fb811 Mon Sep 17 00:00:00 2001
From: microtronics <>
Date: Sun, 29 May 2022 09:41:12 +0200
Subject: [PATCH 1/6] Added the N-Versions of G0(7,8)1G(8,B)U generic Boards
---
README.md | 3 +
boards.txt | 24 +++
.../G071G(8-B)UxN_G081GBUxN/generic_clock.c | 40 +++-
.../G071G(8-B)UxN_G081GBUxN/ldscript.ld | 189 ++++++++++++++++++
4 files changed, 254 insertions(+), 2 deletions(-)
create mode 100644 variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/ldscript.ld
diff --git a/README.md b/README.md
index db8e764b7f..ed3bad8030 100644
--- a/README.md
+++ b/README.md
@@ -309,7 +309,10 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :yellow_heart: | STM32G070CB | Generic Board | **2.3.0** | |
| :yellow_heart: | STM32G070KB | Generic Board | **2.3.0** | |
| :yellow_heart: | STM32G070RB | Generic Board | **2.3.0** | |
+| :yellow_heart: | STM32G071G8UxN | Generic Board | **2.3.0** | |
+| :yellow_heart: | STM32G071GBUxN | Generic Board | **2.3.0** | |
| :green_heart: | STM32G071R6
STM32G071R8
STM32G071RB | Generic Board | *2.0.0* | |
+| :yellow_heart: | STM32G081GBUxN | Generic Board | **2.3.0** | |
| :green_heart: | STM32G081RB | Generic Board | *2.0.0* | |
| :green_heart: | STM32G0B1RB
STM32G0B1RC
STM32G0B1RE | Generic Board | *2.1.0* | |
| :green_heart: | STM32G0C1RB
STM32G0C1RE | Generic Board | *2.1.0* | |
diff --git a/boards.txt b/boards.txt
index f16a5bf613..11ee62a5ba 100644
--- a/boards.txt
+++ b/boards.txt
@@ -3423,6 +3423,22 @@ GenG0.menu.pnum.GENERIC_G070RBTX.build.board=GENERIC_G070RBTX
GenG0.menu.pnum.GENERIC_G070RBTX.build.product_line=STM32G070xx
GenG0.menu.pnum.GENERIC_G070RBTX.build.variant=STM32G0xx/G070RBT
+# Generic G071G8UxN
+GenG0.menu.pnum.GENERIC_G071G8UXN=Generic G071G8UxN
+GenG0.menu.pnum.GENERIC_G071G8UXN.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G071G8UXN.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G071G8UXN.build.board=GENERIC_G071G8UXN
+GenG0.menu.pnum.GENERIC_G071G8UXN.build.product_line=STM32G071xx
+GenG0.menu.pnum.GENERIC_G071G8UXN.build.variant=STM32G0xx/G071G(8-B)UxN_G081GBUxN
+
+# Generic G071GBUxN
+GenG0.menu.pnum.GENERIC_G071GBUXN=Generic G071GBUxN
+GenG0.menu.pnum.GENERIC_G071GBUXN.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G071GBUXN.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G071GBUXN.build.board=GENERIC_G071GBUXN
+GenG0.menu.pnum.GENERIC_G071GBUXN.build.product_line=STM32G071xx
+GenG0.menu.pnum.GENERIC_G071GBUXN.build.variant=STM32G0xx/G071G(8-B)UxN_G081GBUxN
+
# Generic G071R6Tx
GenG0.menu.pnum.GENERIC_G071R6TX=Generic G071R6Tx
GenG0.menu.pnum.GENERIC_G071R6TX.upload.maximum_size=32768
@@ -3455,6 +3471,14 @@ GenG0.menu.pnum.GENERIC_G071RBIX.build.board=GENERIC_G071RBIX
GenG0.menu.pnum.GENERIC_G071RBIX.build.product_line=STM32G071xx
GenG0.menu.pnum.GENERIC_G071RBIX.build.variant=STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)
+# Generic G081GBUxN
+GenG0.menu.pnum.GENERIC_G081GBUXN=Generic G081GBUxN
+GenG0.menu.pnum.GENERIC_G081GBUXN.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G081GBUXN.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G081GBUXN.build.board=GENERIC_G081GBUXN
+GenG0.menu.pnum.GENERIC_G081GBUXN.build.product_line=STM32G081xx
+GenG0.menu.pnum.GENERIC_G081GBUXN.build.variant=STM32G0xx/G071G(8-B)UxN_G081GBUxN
+
# Generic G081RBIx
GenG0.menu.pnum.GENERIC_G081RBIX=Generic G081RBIx
GenG0.menu.pnum.GENERIC_G081RBIX.upload.maximum_size=131072
diff --git a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
index 8aeb672143..1643db4788 100644
--- a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
+++ b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
@@ -21,8 +21,44 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+ RCC_OscInitStruct.PLL.PLLN = 8;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+ RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/ldscript.ld b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/ldscript.ld
new file mode 100644
index 0000000000..c2bcb5259d
--- /dev/null
+++ b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/ldscript.ld
@@ -0,0 +1,189 @@
+/*
+******************************************************************************
+**
+
+** File : LinkerScript.ld
+**
+** Author : STM32CubeMX
+**
+** Abstract : Linker script for STM32G071GBUxN series
+** 128Kbytes FLASH and 36Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed “as is,” without any warranty
+** of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** © COPYRIGHT(c) 2019 STMicroelectronics
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+** 1. Redistributions of source code must retain the above copyright notice,
+** this list of conditions and the following disclaimer.
+** 2. Redistributions in binary form must reproduce the above copyright notice,
+** this list of conditions and the following disclaimer in the documentation
+** and/or other materials provided with the distribution.
+** 3. Neither the name of STMicroelectronics nor the names of its contributors
+** may be used to endorse or promote products derived from this software
+** without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
From 9ec5a38577dbe2dff4cb883a4212d91504e5763d Mon Sep 17 00:00:00 2001
From: microtronics <>
Date: Sun, 29 May 2022 10:42:10 +0200
Subject: [PATCH 2/6] Fix typo generated by STM32CubeMX
---
variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/ldscript.ld | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/ldscript.ld b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/ldscript.ld
index c2bcb5259d..f32c2418eb 100644
--- a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/ldscript.ld
+++ b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/ldscript.ld
@@ -150,7 +150,7 @@ SECTIONS
. = ALIGN(4);
.bss :
{
- /* This is used by the startup in order to initialize the .bss secion */
+ /* This is used by the startup in order to initialize the .bss section */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
From 6595c75cf5f7c468fab092c55bafffcf2f18bf63 Mon Sep 17 00:00:00 2001
From: microtronics <>
Date: Sun, 29 May 2022 11:22:24 +0200
Subject: [PATCH 3/6] Fix AStyle errors
---
.../G071G(8-B)UxN_G081GBUxN/generic_clock.c | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
index 1643db4788..5ec974858e 100644
--- a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
+++ b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
@@ -19,8 +19,7 @@
* @param None
* @retval None
*/
-WEAK void SystemClock_Config(void)
-{
+WEAK void SystemClock_Config(void) {
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
@@ -42,21 +41,19 @@ WEAK void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- {
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- |RCC_CLOCKTYPE_PCLK1;
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
- {
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
Error_Handler();
}
}
From 124ff7bdd5825e963711c93c988511f5d7ec04e4 Mon Sep 17 00:00:00 2001
From: microtronics <>
Date: Sun, 29 May 2022 11:22:24 +0200
Subject: [PATCH 4/6] Fix AStyle errors
---
.../STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
index 1643db4788..3bf6f7367c 100644
--- a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
+++ b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
@@ -42,21 +42,19 @@ WEAK void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- {
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- |RCC_CLOCKTYPE_PCLK1;
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
- {
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
Error_Handler();
}
}
From f89183dd605c79c2f1f6a25cae5a7910a054cfdd Mon Sep 17 00:00:00 2001
From: microtronics <>
Date: Sun, 29 May 2022 11:26:12 +0200
Subject: [PATCH 5/6] Fix AStyle errors
---
variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
index 5ec974858e..3bf6f7367c 100644
--- a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
+++ b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
@@ -19,7 +19,8 @@
* @param None
* @retval None
*/
-WEAK void SystemClock_Config(void) {
+WEAK void SystemClock_Config(void)
+{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
From 812c4134412bc946a4187937156f272e9648e903 Mon Sep 17 00:00:00 2001
From: Frederic Pillon
Date: Mon, 30 May 2022 17:27:01 +0200
Subject: [PATCH 6/6] fix: compilation warnings
Co-authored-by: Alexandre Bourdiol <50730894+ABOSTM@users.noreply.github.com>
---
variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
index 3bf6f7367c..12f2a3d325 100644
--- a/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
+++ b/variants/STM32G0xx/G071G(8-B)UxN_G081GBUxN/generic_clock.c
@@ -21,8 +21,8 @@
*/
WEAK void SystemClock_Config(void)
{
- RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
/** Configure the main internal regulator output voltage
*/