diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h
index 39506778fe..01a6dae184 100644
--- a/cores/arduino/stm32/stm32_def_build.h
+++ b/cores/arduino/stm32/stm32_def_build.h
@@ -232,8 +232,12 @@
#define CMSIS_STARTUP_FILE "startup_stm32h742xx.s"
#elif defined(STM32H743xx)
#define CMSIS_STARTUP_FILE "startup_stm32h743xx.s"
+ #elif defined(STM32H745xG)
+ #define CMSIS_STARTUP_FILE "startup_stm32h745xg.s"
#elif defined(STM32H745xx)
#define CMSIS_STARTUP_FILE "startup_stm32h745xx.s"
+ #elif defined(STM32H747xG)
+ #define CMSIS_STARTUP_FILE "startup_stm32h747xg.s"
#elif defined(STM32H747xx)
#define CMSIS_STARTUP_FILE "startup_stm32h747xx.s"
#elif defined(STM32H750xx)
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h
index 610abfdc5e..12e10e68f6 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h
@@ -12,13 +12,12 @@
******************************************************************************
* @attention
*
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -50,7 +49,7 @@ typedef enum
{
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
@@ -213,12 +212,12 @@ typedef enum
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
-#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
-#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
-#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
+#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
+#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
/**
@@ -248,10 +247,10 @@ typedef struct
__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
- __IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
+ __IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
__IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
__IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
- __IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
+ __IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
uint32_t RESERVED2; /*!< Reserved, 0x02C */
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
@@ -928,8 +927,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
- * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
- * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
*/
@@ -2700,6 +2699,15 @@ typedef struct
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -10803,7 +10811,7 @@ typedef struct
/******************* Bits definition for FLASH_ACR register **********************/
#define FLASH_ACR_LATENCY_Pos (0U)
-#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
@@ -10813,6 +10821,14 @@ typedef struct
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
@@ -10821,12 +10837,6 @@ typedef struct
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
-
/******************* Bits definition for FLASH_CR register ***********************/
#define FLASH_CR_LOCK_Pos (0U)
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
@@ -19268,8 +19278,8 @@ typedef struct
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!