From df9c8e6f146eb712d98ace1576d2f486d85ad41b Mon Sep 17 00:00:00 2001 From: Alexandre Bourdiol Date: Wed, 15 Dec 2021 10:46:10 +0100 Subject: [PATCH 1/2] system(U5) update STM32U5xx HAL Drivers to v1.0.2 Included in STM32CubeU5 FW v1.0.2 Signed-off-by: Alexandre Bourdiol --- .../Inc/Legacy/stm32_hal_legacy.h | 7 ++ .../Inc/stm32u5xx_hal_dac.h | 4 +- .../Inc/stm32u5xx_hal_dac_ex.h | 12 +-- .../Inc/stm32u5xx_hal_dma.h | 10 +- .../Inc/stm32u5xx_hal_gpio_ex.h | 1 - .../Inc/stm32u5xx_ll_adc.h | 17 ++-- .../Inc/stm32u5xx_ll_dac.h | 15 +-- .../Inc/stm32u5xx_ll_i2c.h | 35 +++++++ system/Drivers/STM32U5xx_HAL_Driver/README.md | 24 ++--- .../STM32U5xx_HAL_Driver/Release_Notes.html | 95 +++++++++++++++++- .../STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c | 4 +- .../Src/stm32u5xx_hal_adc.c | 47 ++++++++- .../Src/stm32u5xx_hal_adc_ex.c | 63 +++++++++++- .../Src/stm32u5xx_hal_dac.c | 20 ++-- .../Src/stm32u5xx_hal_dac_ex.c | 20 ++-- .../Src/stm32u5xx_hal_dma.c | 4 +- .../Src/stm32u5xx_hal_dma_ex.c | 81 +++++----------- .../Src/stm32u5xx_hal_gtzc.c | 48 +++++----- .../Src/stm32u5xx_hal_i2c.c | 96 ++++++++++++++----- .../Src/stm32u5xx_hal_rcc.c | 18 ++-- .../Src/stm32u5xx_ll_dac.c | 4 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 22 files changed, 440 insertions(+), 187 deletions(-) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 5af2920753..04f59bdd80 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -259,6 +259,13 @@ extern "C" { #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h index 20eb3c35e8..a00bb9be76 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h @@ -218,8 +218,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); #define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 CH1 selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM3_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM3 CH1 selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac_ex.h index 0c978df06f..773529fe92 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac_ex.h @@ -105,8 +105,8 @@ typedef struct * @brief DAC Trigger stop mode * @{ */ -#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_LPTIM1_OUT /*!< LPTIM1 output selected as DAC trigger in stop mode */ -#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_LPTIM3_OUT /*!< LPTIM3 output selected as DAC trigger in stop mode */ +#define DAC_TRIGGER_STOP_LPTIM1_CH1 DAC_TRIGGER_LPTIM1_CH1 /*!< LPTIM1 output selected as DAC trigger in stop mode */ +#define DAC_TRIGGER_STOP_LPTIM3_CH1 DAC_TRIGGER_LPTIM3_CH1 /*!< LPTIM3 output selected as DAC trigger in stop mode */ #define DAC_TRIGGER_STOP_EXT_IT9 DAC_TRIGGER_EXT_IT9 /*!< EXTI line 9 selected as DAC trigger in stop mode */ /** * @} @@ -133,11 +133,11 @@ typedef struct ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \ - ((TRIGGER) == DAC_TRIGGER_LPTIM3_OUT) || \ + ((TRIGGER) == DAC_TRIGGER_LPTIM1_CH1) || \ + ((TRIGGER) == DAC_TRIGGER_LPTIM3_CH1) || \ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ - ((TRIGGER) == DAC_TRIGGER_STOP_LPTIM1_OUT) || \ - ((TRIGGER) == DAC_TRIGGER_STOP_LPTIM3_OUT) || \ + ((TRIGGER) == DAC_TRIGGER_STOP_LPTIM1_CH1) || \ + ((TRIGGER) == DAC_TRIGGER_STOP_LPTIM3_CH1) || \ ((TRIGGER) == DAC_TRIGGER_STOP_EXT_IT9) || \ ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h index 0e8d5f5cfb..0d910fe793 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h @@ -759,7 +759,8 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons #define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */ #define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */ #define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */ -#define DMA_CHANNEL_ATTR_MASK (0xFFFFFFF0U) /* DMA channel attributes mask */ +#define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */ +#define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */ #define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */ #define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */ /** @@ -839,9 +840,10 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT)) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ - (((((~((ATTRIBUTE) & DMA_CHANNEL_ATTR_MASK)) >> 4U) & ((ATTRIBUTE) & DMA_CHANNEL_ATTR_MASK)) == 0U) && \ - ((ATTRIBUTE) != 0U)) +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ + (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \ + (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \ + (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U))) #else #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h index 7b84dc0fb0..f6a02b2fac 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h @@ -105,7 +105,6 @@ typedef struct #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */ #define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */ #define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ #define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h index 0b94df71b6..2918a1d182 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h @@ -3227,14 +3227,12 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx * ADC state: * ADC must be enabled, without calibration on going, without conversion * on going on group regular. - * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationOffsetFactor - * CALFACT CALFACT_D LL_ADC_SetCalibrationOffsetFactor * @param ADCx ADC instance * @param SingleDiff This parameter can be one of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED - * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F + * @param CalibrationFactor Value between Min_Data=0x0000 and Max_Data=0xFFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, @@ -3243,7 +3241,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32 if (ADCx == ADC1) { CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF | ADC_CALFACT_CAPTURE_COEF); - MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, 0UL); /* CalibIndex == 0*/ + MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, (0UL << ADC_CR_CALINDEX0_Pos)); /* CalibIndex == 0*/ MODIFY_REG(ADCx->CALFACT2, SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) \ @@ -3268,13 +3266,11 @@ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32 * single-ended and differential modes * Calibration of linearity is common to both * single-ended and differential modes - * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationOffsetFactor - * CALFACT CALFACT_D LL_ADC_GetCalibrationOffsetFactor * @param ADCx ADC instance * @param SingleDiff This parameter can be one of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED - * @retval Value between Min_Data=0x00 and Max_Data=0x7F + * @retval Value between Min_Data=0x0000 and Max_Data=0xFFFF */ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff) { @@ -3285,9 +3281,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, ui if (ADCx == ADC1) { uint32_t temp_CalibOffset; - SET_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF); - CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF); - MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, 0UL); /* CalibIndex == 0*/ + MODIFY_REG(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF, ADC_CALFACT_CAPTURE_COEF); + MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, (0UL << ADC_CR_CALINDEX0_Pos)); /* CalibIndex == 0*/ temp_CalibOffset = (READ_BIT(ADCx->CALFACT2, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) \ >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF); @@ -4563,7 +4558,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) /* Parse register for end of sequence identifier */ /* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank (ADC_CHSELR_SQ2), value "4" to length of end of sequence - indentifier (0xF)*/ + identifier (0xF)*/ for (rank_index = 0UL; rank_index <= (28U - 4U); rank_index += 4U) { rank_shifted = (uint32_t)(0xF0UL << rank_index); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dac.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dac.h index 94d9c08653..7b0fee286d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dac.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dac.h @@ -295,9 +295,12 @@ typedef struct #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */ #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */ -#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */ -#define LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 TRGO. */ +#define LL_DAC_TRIG_EXT_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 CH1. */ +#define LL_DAC_TRIG_EXT_LPTIM3_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 CH1. */ #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */ + +#define LL_DAC_TRIG_EXT_LPTIM1_OUT LL_DAC_TRIG_EXT_LPTIM1_CH1 /*!< Keep old definition for compatibility */ +#define LL_DAC_TRIG_EXT_LPTIM3_OUT LL_DAC_TRIG_EXT_LPTIM3_CH1 /*!< Keep old definition for compatibility */ /** * @} */ @@ -712,8 +715,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO - * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT - * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT + * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1 + * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_CH1 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 * @retval None */ @@ -746,8 +749,8 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO - * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT - * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT + * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1 + * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_CH1 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 */ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h index c8c073a48d..d90701e88c 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h @@ -844,6 +844,41 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); } +/** + * @brief Enable I2C Fast Mode Plus (FMP = 1). + * @note 20mA I/O drive enable + * @rmtoll CR1 FMP LL_I2C_EnableFastModePlus + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_FMP); +} + +/** + * @brief Disable I2C Fast Mode Plus (FMP = 0). + * @note 20mA I/O drive disable + * @rmtoll CR1 FMP LL_I2C_DisableFastModePlus + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP); +} + +/** + * @brief Check if the I2C Fast Mode Plus is enabled or disabled. + * @rmtoll CR1 FMP LL_I2C_IsEnabledFastModePlus + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL); +} + /** * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. * @note Changing this bit is not allowed, when the START bit is set. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/README.md b/system/Drivers/STM32U5xx_HAL_Driver/README.md index c17c78999f..a01782acb2 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/README.md +++ b/system/Drivers/STM32U5xx_HAL_Driver/README.md @@ -1,21 +1,19 @@ # STM32CubeU5 HAL Driver MCU Component -![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32u5xx_hal_driver.svg?color=brightgreen) - ## Overview **STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. -**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. - * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. - * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. - * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series. - * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library... - * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series. +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series. + * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product + * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio + * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series + * A consistent set of middlewares components such as RTOS, FatFS, TCP-IP, Graphic ... + * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series Two models of publication are proposed for the STM32Cube embedded software: - * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). - * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. + * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series) + * The **MCU component** : progressively from June 2021, each STM32Cube software module being part of the STM32Cube MCU Package, are delivered as an individual repo, allowing the user to select and get only the required software functions. ## Description @@ -41,7 +39,9 @@ It is **crucial** that you use a consistent set of versions for the CMSIS Core - HAL Driver | CMSIS Device | CMSIS Core | Was delivered in the full MCU package ------------- | --------------- | ---------- | ------------------------------------- -Tag v1.0.0 | Tag v1.0.0 | Tag v5.6.0_cm33 | Tag v1.0.0 (and following, if any, till next tag) +Tag v1.0.0 | Tag v1.0.0 | Tag v560_cm33 | Tag v1.0.0 (and following, if any, till next tag) +Tag v1.0.1 | Tag v1.0.1 | Tag v560_cm33 | Tag v1.0.1 (and following, if any, till next tag) +Tag v1.0.2 | Tag v1.0.2 | Tag v560_cm33 | Tag v1.0.2 (and following, if any, till next tag) The full **STM32CubeU5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeU5). @@ -50,4 +50,4 @@ The full **STM32CubeU5** MCU package is available [here](https://github.com/STMi If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32u5xx_hal_driver/issues/new/choose). -For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/topic/0TO0X000000BSqSWAW/stm32-mcus). \ No newline at end of file +For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). \ No newline at end of file diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html index de8df577c8..c6849956a9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html @@ -40,16 +40,107 @@

Purpose

Update History

- +

Main Changes

    -
  • First official release of HAL and LL drivers for STM32U575xx / STM32U585xx devices
    • +
  • Patch release V1.0.2 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
    • +
+

LL Drivers updates

+
    +
  • LL DAC driver +
      +
    • Rename of the LPTIM1/3 trigger of the LL DAC to be in line with Reference Manual: +
        +
      • Rename LL_DAC_TRIG_EXT_LPTIM1_OUT to LL_DAC_TRIG_EXT_LPTIM1_CH1
        • +
      • Rename LL_DAC_TRIG_EXT_LPTIM3_OUT to LL_DAC_TRIG_EXT_LPTIM3_CH1
        • +
      • +
    • +
  • Backward compatibility ensured by legacy defines

Known Limitations

  • N/A
+

Backward compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Patch release V1.0.1 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
    • +
+

HAL Drivers updates

+
    +
  • HAL ADC driver +
      +
    • Update the DMA data length management implementation according source/destination width
      • +
    • Finetune HAL_ADCEx_Calibration_GetValue API to return correct calibration value for ADC4
      • +
    • +
  • HAL DAC driver +
      +
    • Rename of the LPTIM1/3 trigger of the DAC to be in line with Reference Manual: +
        +
      • Rename DAC_TRIGGER_STOP_LPTIM1_OUT to DAC_TRIGGER_STOP_LPTIM1_CH1
        • +
      • Rename DAC_TRIGGER_STOP_LPTIM3_OUT to DAC_TRIGGER_STOP_LPTIM3_CH1
        • +
      • Rename DAC_TRIGGER_LPTIM1_OUT to DAC_TRIGGER_LPTIM1_CH1
        • +
      • Rename DAC_TRIGGER_LPTIM3_OUT to DAC_TRIGGER_LPTIM3_CH1
        • +
      • +
    • +
  • HAL DMA driver +
      +
    • Fix DMA register callback error returning in case of invalid callback.
      • +
    • Enhance HAL_DMA_GetLockChannelAttributes API implementation to detect wrong parameters values
      • +
    • Enhance IS_DMA_ATTRIBUTES macro implementation to detect uncovered cases.
      • +
    • Optimize DMA_List_CheckNodesBaseAddresses API implementation by reducing parameters number
      • +
    • Optimize DMA_List_CheckNodesTypes API implementation by reducing parameters number
      • +
    • +
  • HAL GTZC driver +
      +
    • Fix issue with the APIs HAL_GTZC_MPCBB_ConfigMem : The CFGLOCK register should be updated after the update of SECCFGR and PRIVCFGR
      • +
    • +
  • HAL I2C driver +
      +
    • Add handle errors support in polling mode
      • +
    • +
  • HAL RCC driver +
      +
    • Fix setting Flash latency from MSIRange in Oscillator Configuration
      • +
    • +
+

LL Drivers updates

+
    +
  • LL I2C driver +
      +
    • Add LL_I2C_EnableFastModePlus, LL_I2C_DisableFastModePlus and LL_I2C_IsEnabledFastModePlus APIs
      • +
    • +
+

Known Limitations

+
    +
  • N/A
    • +
+

Backward compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • First official release of HAL and LL drivers for STM32U575xx / STM32U585xx devices
    • +
+

Known Limitations

+
    +
  • N/A
    • +
diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c index 45a84599c3..102c82bdc6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c @@ -52,11 +52,11 @@ * @{ */ /** - * @brief STM32U5xx HAL Driver version number 1.0.0 + * @brief STM32U5xx HAL Driver version number 1.0.2 */ #define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32U5xx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ -#define __STM32U5xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32U5xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ #define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\ |(__STM32U5xx_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c index 45c67fd196..9637903022 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c @@ -2170,6 +2170,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pDa { HAL_StatusTypeDef tmp_hal_status; uint32_t LengthInBytes; + DMA_NodeConfTypeDef node_conf; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -2244,14 +2245,35 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pDa hadc->Instance->CFGR1 |= ADC4_CFGR1_DMAEN; } - /* Length should be converted to number of bytes */ - LengthInBytes = Length * 4U; - /* Start the DMA channel */ + /* Check linkedlist mode */ if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) { if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL)) { + /* Length should be converted to number of bytes */ + if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK) + { + return HAL_ERROR; + } + + /* Length should be converted to number of bytes */ + if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + /* Word -> Bytes */ + LengthInBytes = Length * 4U; + } + else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + /* Halfword -> Bytes */ + LengthInBytes = Length * 2U; + } + else /* Bytes */ + { + /* Same size already expressed in Bytes */ + LengthInBytes = Length; + } + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes; hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \ (uint32_t)&hadc->Instance->DR; @@ -2265,6 +2287,23 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pDa } else { + /* Length should be converted to number of bytes */ + if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + /* Word -> Bytes */ + LengthInBytes = Length * 4U; + } + else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + /* Halfword -> Bytes */ + LengthInBytes = Length * 2U; + } + else /* Bytes */ + { + /* Same size already expressed in Bytes */ + LengthInBytes = Length; + } + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, \ LengthInBytes); } @@ -3840,7 +3879,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ /* performed automatically by hardware and flag ADC ready is not set. */ - if (hadc->Init.LowPowerAutoPowerOff == ADC_LOW_POWER_NONE) + if ((hadc->Init.LowPowerAutoPowerOff == ADC_LOW_POWER_NONE) || (hadc->Instance != ADC4)) { /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c index db2c63fc98..071dcd4b86 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c @@ -200,12 +200,30 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t */ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { + uint32_t Calib_Val = 0UL; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - /* Return the selected ADC calibration value */ - return LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff); + if (hadc->Instance != ADC4) + { + tmp_hal_status = ADC_Enable(hadc); /* ADC need to be enabled to performe calibration for ADC1/2 and not for ADC4 */ + } + + if (tmp_hal_status == HAL_OK) + { + /* Return the selected ADC calibration value */ + Calib_Val = LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff); + } + + if (hadc->Instance != ADC4) + { + tmp_hal_status = ADC_Disable(hadc); + UNUSED(tmp_hal_status); + } + return Calib_Val; } /** @@ -920,6 +938,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const ui ADC_HandleTypeDef tmp_hadc_slave; ADC_Common_TypeDef *tmp_adc_common; uint32_t LengthInBytes; + DMA_NodeConfTypeDef node_conf; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); @@ -1002,6 +1021,29 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const ui { if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL)) { + /* Length should be converted to number of bytes */ + if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK) + { + return HAL_ERROR; + } + + /* Length should be converted to number of bytes */ + if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + /* Word -> Bytes */ + LengthInBytes = Length * 4U; + } + else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + /* Halfword -> Bytes */ + LengthInBytes = Length * 2U; + } + else /* Bytes */ + { + /* Same size already expressed in Bytes */ + LengthInBytes = Length; + } + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes; hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \ (uint32_t)&tmp_adc_common->CDR; @@ -1016,6 +1058,23 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const ui } else { + /* Length should be converted to number of bytes */ + if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + /* Word -> Bytes */ + LengthInBytes = Length * 4U; + } + else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + /* Halfword -> Bytes */ + LengthInBytes = Length * 2U; + } + else /* Bytes */ + { + /* Same size already expressed in Bytes */ + LengthInBytes = Length; + } + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmp_adc_common->CDR, (uint32_t)pData, \ LengthInBytes); } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c index d603ab6e44..0cc58d4cd6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c @@ -10,7 +10,17 @@ * + Peripheral Control functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### DAC Peripheral features ##### @@ -293,16 +303,6 @@ (@) You can refer to the DAC HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * ****************************************************************************** */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac_ex.c index d027eb9dbd..16fdb1d5bc 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac_ex.c @@ -6,7 +6,17 @@ * This file provides firmware functions to manage the extended * functionalities of the DAC peripheral. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -55,16 +65,6 @@ (+) Use HAL_DACx_ClearConfigAutonomousMode() to clear the configuration of the autonomous mode @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * ****************************************************************************** */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c index 597058474b..9b5f5ed577 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c @@ -1177,6 +1177,8 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, default: { + /* Update error status */ + status = HAL_ERROR; break; } } @@ -1542,7 +1544,7 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons uint32_t channel_idx; /* Check the DMA peripheral handle and lock state parameters */ - if (hdma == NULL) + if ((hdma == NULL) || (pLockState == NULL)) { return HAL_ERROR; } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c index 6da399b33c..0b3c5c2ff6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c @@ -536,12 +536,10 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, DMA_NodeTypeDef const *const pNode); static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3, - DMA_NodeTypeDef const *const pNode4); + DMA_NodeTypeDef const *const pNode3); static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3, - DMA_NodeTypeDef const *const pNode4); + DMA_NodeTypeDef const *const pNode3); static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, uint32_t *const cllr_mask, uint32_t *const cllr_offset); @@ -743,9 +741,10 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) hdma->XferAbortCallback = NULL; hdma->XferSuspendCallback = NULL; - /* Update the queue state and error code */ + /* Check the linked-list queue */ if(hdma->LinkedListQueue != NULL) { + /* Update the queue state and error code */ hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; @@ -1155,7 +1154,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1164,7 +1163,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -1283,7 +1282,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1292,7 +1291,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -1363,7 +1362,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1372,7 +1371,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -1793,7 +1792,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1802,7 +1801,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -1955,7 +1954,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -1964,7 +1963,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) { /* Update the queue error code */ pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -2235,7 +2234,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -2247,7 +2246,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -2433,7 +2432,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -2445,7 +2444,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -2570,7 +2569,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, } /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U) + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; @@ -2582,7 +2581,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, } /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL, NULL) != 0U) + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) { /* Update the source queue error code */ pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; @@ -4070,15 +4069,13 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. - * @param pNode4 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 4 registers configurations. * @retval Return 0 when nodes addresses are compatible, 1 otherwise. */ static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3, - DMA_NodeTypeDef const *const pNode4) + DMA_NodeTypeDef const *const pNode3) { - uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3 | (uint32_t)pNode4) & DMA_CLBAR_LBA); + uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA); uint32_t ref = 0U; /* Check node 1 address */ @@ -4096,11 +4093,6 @@ static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pN { ref = (uint32_t)pNode3; } - /* Check node 4 address */ - else if ((uint32_t)pNode4 != 0U) - { - ref = (uint32_t)pNode4; - } else { /* Prevent MISRA-C2012-Rule-15.7 */ @@ -4120,13 +4112,11 @@ static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pN * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. - * @param pNode4 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 4 registers configurations. * @retval Return 0 when nodes types are compatible, otherwise nodes types are not compatible. */ static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3, - DMA_NodeTypeDef const *const pNode4) + DMA_NodeTypeDef const *const pNode3) { uint32_t ref = 0U; @@ -4145,26 +4135,11 @@ static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, { ref = pNode3->NodeInfo & NODE_TYPE_MASK; } - /* Check node 4 parameter */ - else if (pNode4 != NULL) - { - ref = pNode4->NodeInfo & NODE_TYPE_MASK; - } else { /* Prevent MISRA-C2012-Rule-15.7 */ } - /* Check node 1 parameter */ - if (pNode1 != NULL) - { - /* Check node type compatibility */ - if (ref != (pNode1->NodeInfo & NODE_TYPE_MASK)) - { - return 1U; - } - } - /* Check node 2 parameter */ if (pNode2 != NULL) { @@ -4185,16 +4160,6 @@ static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, } } - /* Check node 4 parameter */ - if (pNode4 != NULL) - { - /* Check node type compatibility */ - if (ref != (pNode4->NodeInfo & NODE_TYPE_MASK)) - { - return 4U; - } - } - return 0U; } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c index 3315c791fc..809a18b403 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c @@ -802,7 +802,6 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, MPCBB_ConfigTypeDef *pMPCBB_desc) { GTZC_MPCBB_TypeDef *mpcbb_ptr; - uint32_t reg_value; uint32_t mem_size; uint32_t size_in_superblocks; uint32_t i; @@ -824,10 +823,6 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, return HAL_ERROR; } - /* write InvertSecureState and SecureRWIllegalMode properties */ - /* assume their Position/Mask is identical for all sub-blocks */ - reg_value = pMPCBB_desc->InvertSecureState; - reg_value |= pMPCBB_desc->SecureRWIllegalMode; if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) { mpcbb_ptr = GTZC_MPCBB1; @@ -853,37 +848,46 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, /* translate mem_size in number of super-blocks */ size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); + /* write PRIVCFGR register information */ + for (i = 0U; i < size_in_superblocks; i++) + { + WRITE_REG(mpcbb_ptr->PRIVCFGR[i], + pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]); + } + #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) uint32_t size_mask; + uint32_t reg_value; - /* write configuration and lock register information */ - MODIFY_REG(mpcbb_ptr->CR, - GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value); - if (size_in_superblocks == 32U) + /* write SECCFGR register information */ + for (i = 0U; i < size_in_superblocks; i++) + { + WRITE_REG(mpcbb_ptr->SECCFGR[i], + pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]); + } + +#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) + if (size_in_superblocks >= 32U) { size_mask = 0xFFFFFFFFU; + MODIFY_REG(mpcbb_ptr->CFGLOCKR2, 0x000FFFFFUL, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1]); } else +#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ { size_mask = (1UL << size_in_superblocks) - 1U; } /* limitation: code not portable with memory > 512K */ MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]); - /* write SECCFGR register information */ - for (i = 0U; i < size_in_superblocks; i++) - { - WRITE_REG(mpcbb_ptr->SECCFGR[i], - pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]); - } -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + /* write InvertSecureState and SecureRWIllegalMode properties */ + reg_value = pMPCBB_desc->InvertSecureState; + reg_value |= pMPCBB_desc->SecureRWIllegalMode; - /* write PRIVCFGR register information */ - for (i = 0U; i < size_in_superblocks; i++) - { - WRITE_REG(mpcbb_ptr->PRIVCFGR[i], - pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]); - } + /* write configuration and lock register information */ + MODIFY_REG(mpcbb_ptr->CR, + GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value); +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ return HAL_OK; } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c index a7c35ed569..cba20e3531 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c @@ -438,7 +438,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); @@ -6740,8 +6740,8 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6777,8 +6777,8 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6811,8 +6811,8 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6863,16 +6863,20 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } /** - * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @brief This function handles errors detection during an I2C Communication. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hi2c->Instance->ISR; + uint32_t error_code = 0; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) { /* In case of Soft End condition, generate the STOP condition */ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) @@ -6881,49 +6885,91 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 hi2c->Instance->CR2 |= I2C_CR2_STOP; } - /* Wait until STOP Flag is reset */ + /* Wait until STOP Flag is set or timeout occurred */ /* AutoEnd should be initiate after AF */ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + error_code |= HAL_I2C_ERROR_TIMEOUT; - return HAL_ERROR; + status = HAL_ERROR; } } } + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + /* Clear NACKF Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + error_code |= HAL_I2C_ERROR_AF; + + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + + /* Then verify if an additionnal errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + { + error_code |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + + status = HAL_ERROR; + } + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + { + error_code |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + + status = HAL_ERROR; + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + { + error_code |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { /* Flush TX register */ I2C_Flush_TXDR(hi2c); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + hi2c->ErrorCode |= error_code; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - - return HAL_ERROR; } - return HAL_OK; + + return status; } /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c index d6775b260f..60c1e06ec7 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c @@ -580,10 +580,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) (HCLK) and the supply voltage of the device */ if (pRCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) { - /* First increase number of wait states update if necessary */ - if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) + /* Decrease number of wait states update if necessary */ + /* Only possible when MSI is the System clock source */ + if(sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) { - return HAL_ERROR; + if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) + { + return HAL_ERROR; + } } /* Selects the Multiple Speed oscillator (MSI) clock range */ @@ -601,10 +605,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \ (pRCC_OscInitStruct->MSIClockRange)); - /* Decrease number of wait states update if necessary */ - if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) + if(sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) { - return HAL_ERROR; + if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) + { + return HAL_ERROR; + } } } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dac.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dac.c index 98833f9b73..45737c60e1 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dac.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dac.c @@ -59,8 +59,8 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM3_OUT) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_CH1) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM3_CH1) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ ) diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index dc96e04c71..fdd62b863c 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -14,7 +14,7 @@ * STM32L4: 1.13.0 * STM32L5: 1.0.4 * STM32MP1: 1.5.0 - * STM32U5: 1.0.0 + * STM32U5: 1.0.2 * STM32WB: 1.10.0 * STM32WL: 1.1.0 From f5bea415e725a829c58b01afed115a2b07937758 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 12 Jul 2021 15:13:35 +0200 Subject: [PATCH 2/2] fix: U5: HAL: add missing GPIO_AF3_TIM1 Signed-off-by: Frederic Pillon --- system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h | 1 + 1 file changed, 1 insertion(+) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h index f6a02b2fac..7b84dc0fb0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h @@ -105,6 +105,7 @@ typedef struct #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */ #define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */ #define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ #define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */