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system(H5): update STM32H5xx CMSIS Drivers to v1.1.0
Included in STM32CubeH5 FW v1.1.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 5029ebb commit e742a5b

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-35
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7 files changed

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-35
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‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1356,6 +1356,7 @@ typedef struct
13561356
__IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3;
13571357
} NSSLIB_pFunc_TypeDef;
13581358

1359+
13591360
/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */
13601361

13611362

@@ -10575,11 +10576,12 @@ typedef struct
1057510576
#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */
1057610577
#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */
1057710578
#define TAMP_ATCR1_ATCKSEL_Pos (16U)
10578-
#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */
10579+
#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */
1057910580
#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk
1058010581
#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */
1058110582
#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */
1058210583
#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */
10584+
#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */
1058310585
#define TAMP_ATCR1_ATPER_Pos (24U)
1058410586
#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */
1058510587
#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk

‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2111,6 +2111,7 @@ typedef struct
21112111
__IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3;
21122112
} NSSLIB_pFunc_TypeDef;
21132113

2114+
21142115
/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */
21152116

21162117

@@ -15786,11 +15787,12 @@ typedef struct
1578615787
#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */
1578715788
#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */
1578815789
#define TAMP_ATCR1_ATCKSEL_Pos (16U)
15789-
#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */
15790+
#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */
1579015791
#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk
1579115792
#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */
1579215793
#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */
1579315794
#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */
15795+
#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */
1579415796
#define TAMP_ATCR1_ATPER_Pos (24U)
1579515797
#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */
1579615798
#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk
@@ -21125,8 +21127,6 @@ typedef struct
2112521127
((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
2112621128
((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
2112721129
((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \
21128-
((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \
21129-
((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \
2113021130
((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
2113121131

2113221132
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -21254,15 +21254,9 @@ typedef struct
2125421254
((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
2125521255

2125621256
/******************* TIM Instances : Timer input selection ********************/
21257-
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
21258-
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
21257+
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
2125921258
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
21260-
((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
21261-
((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
21262-
((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
2126321259
((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \
21264-
((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S)|| \
21265-
((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S)|| \
2126621260
((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)|| \
2126721261
((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \
2126821262
((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2299,6 +2299,7 @@ typedef struct
22992299
__IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3;
23002300
} NSSLIB_pFunc_TypeDef;
23012301

2302+
23022303
/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */
23032304

23042305

@@ -17882,11 +17883,12 @@ typedef struct
1788217883
#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */
1788317884
#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */
1788417885
#define TAMP_ATCR1_ATCKSEL_Pos (16U)
17885-
#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */
17886+
#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */
1788617887
#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk
1788717888
#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */
1788817889
#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */
1788917890
#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */
17891+
#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */
1789017892
#define TAMP_ATCR1_ATPER_Pos (24U)
1789117893
#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */
1789217894
#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk
@@ -23261,8 +23263,6 @@ typedef struct
2326123263
((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
2326223264
((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
2326323265
((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \
23264-
((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \
23265-
((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \
2326623266
((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
2326723267

2326823268
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -23390,15 +23390,9 @@ typedef struct
2339023390
((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
2339123391

2339223392
/******************* TIM Instances : Timer input selection ********************/
23393-
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
23394-
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
23393+
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
2339523394
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
23396-
((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
23397-
((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
23398-
((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
2339923395
((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \
23400-
((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S)|| \
23401-
((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S)|| \
2340223396
((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)|| \
2340323397
((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \
2340423398
((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h

Lines changed: 28 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2394,6 +2394,31 @@ typedef struct
23942394
__IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3;
23952395
} NSSLIB_pFunc_TypeDef;
23962396

2397+
/*
2398+
* Certificate address description
2399+
*/
2400+
#define CERT_CHIP_PACK1_ADDR (0x0BF9FE00U)
2401+
#define CERT_CHIP_PACK1_SIZE (0x200U)
2402+
#define CERT_CHIP_PACK2_ADDR (0x0BF9FC00U)
2403+
#define CERT_CHIP_PACK2_SIZE (0x200U)
2404+
2405+
#define CERT_CHIP_PACK_ADDR (CERT_CHIP_PACK2_ADDR)
2406+
#define CERT_CHIP_PACK_SIZE (CERT_CHIP_PACK1_SIZE + CERT_CHIP_PACK2_SIZE)
2407+
2408+
#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET (152U)
2409+
#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET)
2410+
#define CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET (216U)
2411+
#define CERT_ST_DUA_INIT_ATTEST_SIGN_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET)
2412+
#define CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET (484U)
2413+
#define CERT_ST_DUA_INIT_ATTEST_SERIAL_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET)
2414+
2415+
#define CERT_ST_DUA_USER_PUB_KEY_OFFSET (12U)
2416+
#define CERT_ST_DUA_USER_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_PUB_KEY_OFFSET)
2417+
#define CERT_ST_DUA_USER_SIGN_OFFSET (76U)
2418+
#define CERT_ST_DUA_USER_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SIGN_OFFSET)
2419+
#define CERT_ST_DUA_USER_SERIAL_OFFSET (140U)
2420+
#define CERT_ST_DUA_USER_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SERIAL_OFFSET)
2421+
23972422
/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */
23982423

23992424

@@ -18439,11 +18464,12 @@ typedef struct
1843918464
#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */
1844018465
#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */
1844118466
#define TAMP_ATCR1_ATCKSEL_Pos (16U)
18442-
#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */
18467+
#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */
1844318468
#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk
1844418469
#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */
1844518470
#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */
1844618471
#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */
18472+
#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */
1844718473
#define TAMP_ATCR1_ATPER_Pos (24U)
1844818474
#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */
1844918475
#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk
@@ -24186,8 +24212,6 @@ typedef struct
2418624212
((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
2418724213
((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
2418824214
((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \
24189-
((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \
24190-
((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \
2419124215
((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
2419224216

2419324217
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -24315,15 +24339,9 @@ typedef struct
2431524339
((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
2431624340

2431724341
/******************* TIM Instances : Timer input selection ********************/
24318-
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
24319-
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
24342+
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
2432024343
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
24321-
((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \
24322-
((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \
24323-
((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \
2432424344
((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \
24325-
((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S)|| \
24326-
((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S)|| \
2432724345
((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)|| \
2432824346
((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \
2432924347
((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))

‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -78,10 +78,10 @@
7878
#endif /* USE_HAL_DRIVER */
7979

8080
/**
81-
* @brief CMSIS Device version number 1.0.0
81+
* @brief CMSIS Device version number 1.1.0
8282
*/
8383
#define __STM32H5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
84-
#define __STM32H5_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
84+
#define __STM32H5_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
8585
#define __STM32H5_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
8686
#define __STM32H5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
8787
#define __STM32H5_CMSIS_VERSION ((__STM32H5_CMSIS_VERSION_MAIN << 24U)\

‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,10 +30,21 @@ <h1 id="release-notes-for-stm32h5xx-cmsis">Release Notes for <mark> STM32H5xx C
3030
<div class="col-sm-12 col-lg-8">
3131
<h1 id="update-history"><strong>Update History</strong></h1>
3232
<div class="collapse">
33-
<input type="checkbox" id="collapse-section1" Checked aria-hidden="true"> <label for="collapse-section1" checked aria-hidden="true"><strong>V1.0.0 / 10-February-2023</strong></label>
33+
<input type="checkbox" id="collapse-section2" Checked aria-hidden="true"> <label for="collapse-section2" checked aria-hidden="true"><strong>V1.1.0 / 07-June-2023</strong></label>
3434
<div>
3535
<h2 id="main-changes">Main Changes</h2>
3636
<ul>
37+
<li>Add DUA addresses constants definitions for STM32H573xx devices only</li>
38+
<li>Fix wrong definition of IS_TIM_CLOCKSOURCE_TIX_INSTANCE &amp; IS_TIM_TISEL_INSTANCE macros</li>
39+
<li>Update possible values of the ATCKSEL field of TAMP active tamper control register and update the mask accordingly.</li>
40+
</ul>
41+
</div>
42+
</div>
43+
<div class="collapse">
44+
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" checked aria-hidden="true"><strong>V1.0.0 / 10-February-2023</strong></label>
45+
<div>
46+
<h2 id="main-changes-1">Main Changes</h2>
47+
<ul>
3748
<li>First official release version of bits and registers definition aligned with RM0481 and RM0492 (STM32H5 reference manuals)</li>
3849
</ul>
3950
</div>

‎system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
* STM32F7: 1.2.8
1010
* STM32G0: 1.4.3
1111
* STM32G4: 1.2.2
12-
* STM32H5: 1.0.0
12+
* STM32H5: 1.1.0
1313
* STM32H7: 1.10.3
1414
* STM32L0: 1.9.3
1515
* STM32L1: 2.3.3

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