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Change the SystemClock_Config for BLE on this nucleo_wb55rg
enabling IPCC module of the stm32WB55 to support with the correct Peripheral CLK Config and otp which contains the device bd address Signed-off-by: Francois Ramu <francois.ramu@st.com>
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-58
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3 files changed

+143
-58
lines changed

‎variants/PNUCLEO_WB55RG/otp.h

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/**
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******************************************************************************
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* @file otp.h
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* @author MCD Application Team
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* @brief OTP manager interface
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******************************************************************************
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* @attention
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*
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* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __OTP_H
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#define __OTP_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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/* ----------------------------------- *
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* Packed usage (compiler dependent) *
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* ----------------------------------- */
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#undef PACKED__
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#undef PACKED_STRUCT
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typedef struct __packed {
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uint8_t bd_address[6];
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uint8_t hse_tuning;
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uint8_t id;
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} OTP_ID0_t;
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/* Exported constants --------------------------------------------------------*/
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#define CFG_OTP_BASE_ADDRESS OTP_AREA_BASE
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#define CFG_OTP_END_ADDRESS OTP_AREA_END_ADDR
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#ifdef __cplusplus
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}
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#endif
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#endif /*__OTP_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎variants/PNUCLEO_WB55RG/variant.cpp

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*/
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#include "pins_arduino.h"
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#include "otp.h"
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#ifdef __cplusplus
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extern "C" {
@@ -88,71 +89,100 @@ const PinName digitalPin[] = {
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extern "C" {
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#endif
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static uint8_t * OTP_Read( uint8_t id )
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{
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uint8_t *p_id;
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p_id = (uint8_t*)(CFG_OTP_END_ADDRESS - 7) ;
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while( ((*( p_id + 7 )) != id) && ( p_id != (uint8_t*)CFG_OTP_BASE_ADDRESS) )
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{
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p_id -= 8 ;
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}
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if((*( p_id + 7 )) != id)
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{
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p_id = 0 ;
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}
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return p_id ;
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}
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static void Config_HSE(void)
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{
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OTP_ID0_t *p_otp;
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/**
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* Read HSE_Tuning from OTP
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*/
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p_otp = (OTP_ID0_t *) OTP_Read(0);
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if (p_otp) {
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LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
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}
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}
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/**
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* @brief System Clock Configuration
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* @param None
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* @retval None
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*/
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WEAK void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
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/* Configure LSE Drive Capability */
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__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
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/* Configure the main internal regulator output voltage */
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/* Initializes the CPU, AHB and APB busses clocks */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
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| RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.MSIState = RCC_MSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
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RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
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RCC_OscInitStruct.PLL.PLLN = 32;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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Error_Handler();
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}
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/* Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2
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| RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
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RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
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Error_Handler();
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}
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/* Initializes the peripherals clocks */
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_USB;
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PeriphClkInitStruct.PLLSAI1.PLLN = 24;
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PeriphClkInitStruct.PLLSAI1.PLLP = RCC_PLLP_DIV2;
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PeriphClkInitStruct.PLLSAI1.PLLQ = RCC_PLLQ_DIV2;
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PeriphClkInitStruct.PLLSAI1.PLLR = RCC_PLLR_DIV2;
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PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_USBCLK;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
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PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
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PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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Error_Handler();
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}
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/* Enable MSI Auto calibration */
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HAL_RCCEx_EnableMSIPLLMode();
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RCC_OscInitTypeDef RCC_OscInitStruct = {};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
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Config_HSE();
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__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/* Initializes the CPU, AHB and APB busses clocks */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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Error_Handler();
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}
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/* Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2
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| RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
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Error_Handler();
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}
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/* Initializes the peripherals clocks */
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/* RNG needs to be configured like in M0 core, i.e. with HSI48 */
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP |
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RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
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PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
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PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
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PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
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PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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Error_Handler();
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}
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LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
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LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
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LL_PWR_SMPS_Enable();
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/* Select HSI as system clock source after Wake Up from Stop mode */
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LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
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}
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#ifdef __cplusplus

‎variants/PNUCLEO_WB55RG/variant.h

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// for EEPROM emulation to the last 512k pages.
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#define FLASH_PAGE_NUMBER 127
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#define HAL_IPCC_MODULE_ENABLED
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#ifdef __cplusplus
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} // extern "C"
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#endif

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