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Updated STM32L1xx HAL Drivers to v1.3.1
Included in STM32CubeL1 FW V1.8.0 Signed-off-by: Frederic.Pillon <frederic.pillon@st.com>
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‎system/Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

Lines changed: 89 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32_hal_legacy.h
44
* @author MCD Application Team
5-
* @version 21-April-2017
6-
* @date V1.3.0
75
* @brief This file contains aliases definition for the STM32Cube HAL constants
86
* macros and functions maintained for legacy purpose.
97
******************************************************************************
@@ -138,7 +136,9 @@
138136
#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
139137
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
140138
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
141-
#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
139+
#if defined(STM32L0)
140+
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
141+
#endif
142142
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
143143
#if defined(STM32F373xC) || defined(STM32F378xx)
144144
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
@@ -265,7 +265,6 @@
265265
#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
266266
#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
267267
#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
268-
#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
269268
#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
270269
#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
271270
#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
@@ -467,7 +466,60 @@
467466
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
468467
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
469468
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
470-
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
469+
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
470+
471+
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
472+
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
473+
474+
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
475+
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
476+
477+
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
478+
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
479+
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
480+
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
481+
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
482+
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
483+
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
484+
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
485+
486+
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
487+
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
488+
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
489+
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
490+
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
491+
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
492+
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
493+
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
494+
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
495+
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
496+
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
497+
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
498+
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
499+
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
500+
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
501+
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
502+
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
503+
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
504+
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
505+
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
506+
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
507+
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
508+
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
509+
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
510+
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
511+
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
512+
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
513+
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
514+
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
515+
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
516+
517+
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
518+
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
519+
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
520+
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
521+
522+
471523
#endif /* STM32H7 */
472524

473525

@@ -689,17 +741,13 @@
689741
#define FORMAT_BCD RTC_FORMAT_BCD
690742

691743
#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
692-
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
693744
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
694745
#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
695746
#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
696747

697748
#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
698749
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
699750
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
700-
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
701-
#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
702-
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
703751
#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
704752
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
705753

@@ -915,9 +963,9 @@
915963
#define CAN_IT_RQCP2 CAN_IT_TME
916964
#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
917965
#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
918-
#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
919-
#define CAN_TXSTATUS_OK ((uint8_t)0x01)
920-
#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
966+
#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
967+
#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
968+
#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
921969

922970
/**
923971
* @}
@@ -965,9 +1013,12 @@
9651013
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
9661014
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
9671015
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
1016+
#if defined(STM32F1)
1017+
#else
9681018
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
9691019
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
9701020
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
1021+
#endif
9711022
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
9721023
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
9731024
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
@@ -1332,7 +1383,6 @@
13321383
#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
13331384
#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
13341385
#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
1335-
#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
13361386
#define __HAL_ADC_JSQR ADC_JSQR
13371387

13381388
#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
@@ -1809,20 +1859,20 @@
18091859
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
18101860
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
18111861

1812-
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
1813-
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
1814-
#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
1815-
#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
1816-
#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
1817-
#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
1818-
#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
1819-
#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
1820-
#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
1821-
#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
1822-
#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
1823-
#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
1824-
#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
1825-
#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
1862+
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
1863+
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
1864+
#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
1865+
#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
1866+
#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
1867+
#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
1868+
#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
1869+
#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
1870+
#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
1871+
#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
1872+
#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
1873+
#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
1874+
#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
1875+
#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
18261876
#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
18271877
#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
18281878
#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
@@ -1839,7 +1889,7 @@
18391889
#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
18401890
#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
18411891
#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
1842-
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
1892+
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
18431893
#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
18441894
#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
18451895
#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
@@ -2434,7 +2484,6 @@
24342484
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
24352485
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
24362486
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
2437-
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
24382487
#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
24392488
#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
24402489
#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
@@ -2467,8 +2516,6 @@
24672516
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
24682517
#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
24692518
#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
2470-
#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
2471-
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
24722519
#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
24732520
#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
24742521
#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
@@ -2490,8 +2537,6 @@
24902537
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
24912538
#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
24922539
#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
2493-
#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
2494-
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
24952540
#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
24962541
#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
24972542
#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
@@ -2658,6 +2703,11 @@
26582703
#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
26592704
#endif
26602705

2706+
#if defined(STM32F7)
2707+
#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
2708+
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
2709+
#endif
2710+
26612711
#if defined(STM32H7)
26622712
#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
26632713
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
@@ -2682,11 +2732,6 @@
26822732
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
26832733
#endif
26842734

2685-
#if defined(STM32F7)
2686-
#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
2687-
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
2688-
#endif
2689-
26902735
#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
26912736
#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
26922737

@@ -2740,7 +2785,10 @@
27402785
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
27412786
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
27422787

2788+
#if defined(STM32WB) || defined(STM32G0)
2789+
#else
27432790
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
2791+
#endif
27442792

27452793
#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
27462794
#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
@@ -2865,8 +2913,10 @@
28652913
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
28662914
* @{
28672915
*/
2868-
2916+
#if defined (STM32G0)
2917+
#else
28692918
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
2919+
#endif
28702920
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
28712921
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
28722922

‎system/Drivers/STM32L1xx_HAL_Driver/Inc/stm32_assert_template.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32_assert.h
44
* @author MCD Application Team
5-
* @version 21-April-2017
6-
* @date V1.3.0
75
* @brief STM32 assert template file.
86
* This file should be copied to the application folder and renamed
97
* to stm32_assert.h.

‎system/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32l1xx_hal.h
44
* @author MCD Application Team
5-
* @version 21-April-2017
6-
* @date V1.3.0
75
* @brief This file contains all the functions prototypes for the HAL
86
* module driver.
97
******************************************************************************

‎system/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32l1xx_hal_adc.h
44
* @author MCD Application Team
5-
* @version 21-April-2017
6-
* @date V1.3.0
75
* @brief Header file containing functions prototypes of ADC HAL library.
86
******************************************************************************
97
* @attention

‎system/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32l1xx_hal_adc_ex.h
44
* @author MCD Application Team
5-
* @version 21-April-2017
6-
* @date V1.3.0
75
* @brief Header file of ADC HAL Extension module.
86
******************************************************************************
97
* @attention

‎system/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32l1xx_hal_comp.h
44
* @author MCD Application Team
5-
* @version 21-April-2017
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* @date V1.3.0
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* @brief Header file of COMP HAL module.
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******************************************************************************
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* @attention

‎system/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_comp_ex.h

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******************************************************************************
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* @file stm32l1xx_hal_comp_ex.h
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* @author MCD Application Team
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* @version 21-April-2017
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* @date V1.3.0
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* @brief Header file of COMP HAL Extension module.
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******************************************************************************
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* @attention

‎system/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_conf_template.h

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* @file stm32l1xx_hal_conf.h
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* @author MCD Application Team
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* @version 21-April-2017
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* @date V1.3.0
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* @brief HAL configuration template file.
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* This file should be copied to the application folder and renamed
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* to stm32l1xx_hal_conf.h.

‎system/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h

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* @file stm32l1xx_hal_cortex.h
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* @author MCD Application Team
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* @version 21-April-2017
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* @date V1.3.0
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* @brief Header file of CORTEX HAL module.
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******************************************************************************
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* @attention

‎system/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_crc.h

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* @file stm32l1xx_hal_crc.h
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* @author MCD Application Team
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* @version 21-April-2017
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* @date V1.3.0
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* @brief Header file of CRC HAL module.
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******************************************************************************
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* @attention

‎system/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp.h

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* @file stm32l1xx_hal_cryp.h
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* @author MCD Application Team
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* @version 21-April-2017
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* @date V1.3.0
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* @brief Header file of CRYP HAL module.
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******************************************************************************
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* @attention

‎system/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cryp_ex.h

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* @file stm32l1xx_hal_cryp_ex.h
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* @author MCD Application Team
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* @version 21-April-2017
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* @date V1.3.0
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* @brief Header file of CRYPEx HAL module.
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******************************************************************************
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* @attention

‎system/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac.h

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* @file stm32l1xx_hal_dac.h
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* @author MCD Application Team
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* @version 21-April-2017
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* @date V1.3.0
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* @brief Header file of DAC HAL module.
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******************************************************************************
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* @attention

‎system/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dac_ex.h

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* @file stm32l1xx_hal_dac_ex.h
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* @author MCD Application Team
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* @version 21-April-2017
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* @date V1.3.0
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* @brief Header file of DAC HAL Extension module.
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******************************************************************************
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* @attention

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