|
460 | 460 | #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
|
461 | 461 | #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
|
462 | 462 | #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
|
463 |
| -#endif |
| 463 | +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE |
| 464 | +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL |
| 465 | +#endif /* STM32H7 */ |
464 | 466 |
|
465 | 467 | /**
|
466 | 468 | * @}
|
|
735 | 737 | #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
|
736 | 738 | #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
|
737 | 739 | #endif /* STM32H7 */
|
| 740 | + |
| 741 | +#if defined(STM32F3) |
| 742 | +#define HRTIM_OUTPUTSET_TIMEV_1 HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 |
| 743 | +#define HRTIM_OUTPUTSET_TIMEV_2 HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 |
| 744 | +#define HRTIM_OUTPUTSET_TIMEV_3 HRTIM_OUTPUTSET_TIMAEV3_TIMBCMP4 |
| 745 | +#define HRTIM_OUTPUTSET_TIMEV_4 HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2 |
| 746 | +#define HRTIM_OUTPUTSET_TIMEV_5 HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3 |
| 747 | +#define HRTIM_OUTPUTSET_TIMEV_6 HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1 |
| 748 | +#define HRTIM_OUTPUTSET_TIMEV_7 HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2 |
| 749 | +#define HRTIM_OUTPUTSET_TIMEV_8 HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3 |
| 750 | +#define HRTIM_OUTPUTSET_TIMEV_9 HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4 |
| 751 | + |
| 752 | +#define HRTIM_OUTPUTRESET_TIMEV_1 HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 |
| 753 | +#define HRTIM_OUTPUTRESET_TIMEV_2 HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 |
| 754 | +#define HRTIM_OUTPUTRESET_TIMEV_3 HRTIM_OUTPUTRESET_TIMAEV3_TIMBCMP4 |
| 755 | +#define HRTIM_OUTPUTRESET_TIMEV_4 HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2 |
| 756 | +#define HRTIM_OUTPUTRESET_TIMEV_5 HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3 |
| 757 | +#define HRTIM_OUTPUTRESET_TIMEV_6 HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1 |
| 758 | +#define HRTIM_OUTPUTRESET_TIMEV_7 HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2 |
| 759 | +#define HRTIM_OUTPUTRESET_TIMEV_8 HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3 |
| 760 | +#define HRTIM_OUTPUTRESET_TIMEV_9 HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4 |
| 761 | + |
| 762 | +#define HRTIM_EVENTSRC_1 HRTIM_EEV1SRC_GPIO |
| 763 | +#define HRTIM_EVENTSRC_2 HRTIM_EEV2SRC_GPIO |
| 764 | +#define HRTIM_EVENTSRC_3 HRTIM_EEV3SRC_GPIO |
| 765 | +#define HRTIM_EVENTSRC_4 HRTIM_EEV4SRC_GPIO |
| 766 | +#endif /* STM32F3 */ |
738 | 767 | /**
|
739 | 768 | * @}
|
740 | 769 | */
|
|
1380 | 1409 | #endif
|
1381 | 1410 | #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
|
1382 | 1411 | #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
|
| 1412 | +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) |
| 1413 | +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode |
| 1414 | +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode |
| 1415 | +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode |
| 1416 | +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode |
| 1417 | +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7A3xxQ || STM32H7B3xxQ */ |
| 1418 | + |
1383 | 1419 | /**
|
1384 | 1420 | * @}
|
1385 | 1421 | */
|
|
3242 | 3278 | /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
3243 | 3279 | * @{
|
3244 | 3280 | */
|
3245 |
| -#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined STM32G4 |
| 3281 | +#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) |
3246 | 3282 | #else
|
3247 | 3283 | #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
3248 | 3284 | #endif
|
|
3606 | 3642 | * @{
|
3607 | 3643 | */
|
3608 | 3644 | #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
|
3609 |
| -#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT |
3610 |
| -#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA |
3611 |
| -#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart |
3612 |
| -#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT |
3613 |
| -#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA |
3614 |
| -#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop |
| 3645 | +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT |
| 3646 | +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA |
| 3647 | +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart |
| 3648 | +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT |
| 3649 | +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA |
| 3650 | +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop |
3615 | 3651 | #endif
|
3616 | 3652 | /**
|
3617 | 3653 | * @}
|
|
0 commit comments