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Merge pull request #1595 from ABOSTM/STM32U5_UPDATE_V1.0.2
Stm32 u5 update v1.0.2
2 parents 165435b + f5bea41 commit c010008

21 files changed

+440
-186
lines changed

‎system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -259,6 +259,13 @@ extern "C" {
259259
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
260260
#endif
261261

262+
#if defined(STM32U5)
263+
#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
264+
#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
265+
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
266+
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
267+
#endif
268+
262269
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
263270
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
264271
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID

‎system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -218,8 +218,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
218218
#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
219219
#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
220220
#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
221-
#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */
222-
#define DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel */
221+
#define DAC_TRIGGER_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 CH1 selected as external conversion trigger for DAC channel */
222+
#define DAC_TRIGGER_LPTIM3_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM3 CH1 selected as external conversion trigger for DAC channel */
223223
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
224224

225225
/**

‎system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac_ex.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -105,8 +105,8 @@ typedef struct
105105
* @brief DAC Trigger stop mode
106106
* @{
107107
*/
108-
#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_LPTIM1_OUT /*!< LPTIM1 output selected as DAC trigger in stop mode */
109-
#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_LPTIM3_OUT /*!< LPTIM3 output selected as DAC trigger in stop mode */
108+
#define DAC_TRIGGER_STOP_LPTIM1_CH1 DAC_TRIGGER_LPTIM1_CH1 /*!< LPTIM1 output selected as DAC trigger in stop mode */
109+
#define DAC_TRIGGER_STOP_LPTIM3_CH1 DAC_TRIGGER_LPTIM3_CH1 /*!< LPTIM3 output selected as DAC trigger in stop mode */
110110
#define DAC_TRIGGER_STOP_EXT_IT9 DAC_TRIGGER_EXT_IT9 /*!< EXTI line 9 selected as DAC trigger in stop mode */
111111
/**
112112
* @}
@@ -133,11 +133,11 @@ typedef struct
133133
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
134134
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
135135
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
136-
((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
137-
((TRIGGER) == DAC_TRIGGER_LPTIM3_OUT) || \
136+
((TRIGGER) == DAC_TRIGGER_LPTIM1_CH1) || \
137+
((TRIGGER) == DAC_TRIGGER_LPTIM3_CH1) || \
138138
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
139-
((TRIGGER) == DAC_TRIGGER_STOP_LPTIM1_OUT) || \
140-
((TRIGGER) == DAC_TRIGGER_STOP_LPTIM3_OUT) || \
139+
((TRIGGER) == DAC_TRIGGER_STOP_LPTIM1_CH1) || \
140+
((TRIGGER) == DAC_TRIGGER_STOP_LPTIM3_CH1) || \
141141
((TRIGGER) == DAC_TRIGGER_STOP_EXT_IT9) || \
142142
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
143143

‎system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -759,7 +759,8 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
759759
#define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */
760760
#define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */
761761
#define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */
762-
#define DMA_CHANNEL_ATTR_MASK (0xFFFFFFF0U) /* DMA channel attributes mask */
762+
#define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */
763+
#define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */
763764
#define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */
764765
#define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */
765766
/**
@@ -839,9 +840,10 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
839840
(((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT))
840841

841842
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
842-
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
843-
(((((~((ATTRIBUTE) & DMA_CHANNEL_ATTR_MASK)) >> 4U) & ((ATTRIBUTE) & DMA_CHANNEL_ATTR_MASK)) == 0U) && \
844-
((ATTRIBUTE) != 0U))
843+
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
844+
(((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \
845+
(((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \
846+
(((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U)))
845847
#else
846848
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
847849
(((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \

‎system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h

Lines changed: 6 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -3227,14 +3227,12 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx
32273227
* ADC state:
32283228
* ADC must be enabled, without calibration on going, without conversion
32293229
* on going on group regular.
3230-
* @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationOffsetFactor
3231-
* CALFACT CALFACT_D LL_ADC_SetCalibrationOffsetFactor
32323230
* @param ADCx ADC instance
32333231
* @param SingleDiff This parameter can be one of the following values:
32343232
* @arg @ref LL_ADC_SINGLE_ENDED
32353233
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
32363234
* @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
3237-
* @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
3235+
* @param CalibrationFactor Value between Min_Data=0x0000 and Max_Data=0xFFFF
32383236
* @retval None
32393237
*/
32403238
__STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff,
@@ -3243,7 +3241,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32
32433241
if (ADCx == ADC1)
32443242
{
32453243
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF | ADC_CALFACT_CAPTURE_COEF);
3246-
MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, 0UL); /* CalibIndex == 0*/
3244+
MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, (0UL << ADC_CR_CALINDEX0_Pos)); /* CalibIndex == 0*/
32473245
MODIFY_REG(ADCx->CALFACT2,
32483246
SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
32493247
CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) \
@@ -3268,13 +3266,11 @@ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32
32683266
* single-ended and differential modes
32693267
* Calibration of linearity is common to both
32703268
* single-ended and differential modes
3271-
* @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationOffsetFactor
3272-
* CALFACT CALFACT_D LL_ADC_GetCalibrationOffsetFactor
32733269
* @param ADCx ADC instance
32743270
* @param SingleDiff This parameter can be one of the following values:
32753271
* @arg @ref LL_ADC_SINGLE_ENDED
32763272
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3277-
* @retval Value between Min_Data=0x00 and Max_Data=0x7F
3273+
* @retval Value between Min_Data=0x0000 and Max_Data=0xFFFF
32783274
*/
32793275
__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
32803276
{
@@ -3285,9 +3281,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, ui
32853281
if (ADCx == ADC1)
32863282
{
32873283
uint32_t temp_CalibOffset;
3288-
SET_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
3289-
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF);
3290-
MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, 0UL); /* CalibIndex == 0*/
3284+
MODIFY_REG(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF, ADC_CALFACT_CAPTURE_COEF);
3285+
MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, (0UL << ADC_CR_CALINDEX0_Pos)); /* CalibIndex == 0*/
32913286
temp_CalibOffset = (READ_BIT(ADCx->CALFACT2, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) \
32923287
>> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
32933288
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
@@ -4563,7 +4558,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
45634558
/* Parse register for end of sequence identifier */
45644559
/* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank
45654560
(ADC_CHSELR_SQ2), value "4" to length of end of sequence
4566-
indentifier (0xF)*/
4561+
identifier (0xF)*/
45674562
for (rank_index = 0UL; rank_index <= (28U - 4U); rank_index += 4U)
45684563
{
45694564
rank_shifted = (uint32_t)(0xF0UL << rank_index);

‎system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dac.h

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -295,9 +295,12 @@ typedef struct
295295
#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
296296
#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
297297
#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
298-
#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */
299-
#define LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 TRGO. */
298+
#define LL_DAC_TRIG_EXT_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 CH1. */
299+
#define LL_DAC_TRIG_EXT_LPTIM3_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 CH1. */
300300
#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
301+
302+
#define LL_DAC_TRIG_EXT_LPTIM1_OUT LL_DAC_TRIG_EXT_LPTIM1_CH1 /*!< Keep old definition for compatibility */
303+
#define LL_DAC_TRIG_EXT_LPTIM3_OUT LL_DAC_TRIG_EXT_LPTIM3_CH1 /*!< Keep old definition for compatibility */
301304
/**
302305
* @}
303306
*/
@@ -712,8 +715,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC
712715
* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
713716
* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
714717
* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
715-
* @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
716-
* @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT
718+
* @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1
719+
* @arg @ref LL_DAC_TRIG_EXT_LPTIM3_CH1
717720
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
718721
* @retval None
719722
*/
@@ -746,8 +749,8 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha
746749
* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
747750
* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
748751
* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
749-
* @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
750-
* @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT
752+
* @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1
753+
* @arg @ref LL_DAC_TRIG_EXT_LPTIM3_CH1
751754
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
752755
*/
753756
__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)

‎system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -844,6 +844,41 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
844844
return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
845845
}
846846

847+
/**
848+
* @brief Enable I2C Fast Mode Plus (FMP = 1).
849+
* @note 20mA I/O drive enable
850+
* @rmtoll CR1 FMP LL_I2C_EnableFastModePlus
851+
* @param I2Cx I2C Instance.
852+
* @retval None
853+
*/
854+
__STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx)
855+
{
856+
SET_BIT(I2Cx->CR1, I2C_CR1_FMP);
857+
}
858+
859+
/**
860+
* @brief Disable I2C Fast Mode Plus (FMP = 0).
861+
* @note 20mA I/O drive disable
862+
* @rmtoll CR1 FMP LL_I2C_DisableFastModePlus
863+
* @param I2Cx I2C Instance.
864+
* @retval None
865+
*/
866+
__STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx)
867+
{
868+
CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP);
869+
}
870+
871+
/**
872+
* @brief Check if the I2C Fast Mode Plus is enabled or disabled.
873+
* @rmtoll CR1 FMP LL_I2C_IsEnabledFastModePlus
874+
* @param I2Cx I2C Instance.
875+
* @retval State of bit (1 or 0).
876+
*/
877+
__STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(I2C_TypeDef *I2Cx)
878+
{
879+
return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL);
880+
}
881+
847882
/**
848883
* @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
849884
* @note Changing this bit is not allowed, when the START bit is set.

‎system/Drivers/STM32U5xx_HAL_Driver/README.md

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,21 +1,19 @@
11
# STM32CubeU5 HAL Driver MCU Component
22

3-
![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32u5xx_hal_driver.svg?color=brightgreen)
4-
53
## Overview
64

75
**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
86

9-
**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
10-
* The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
11-
* The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
12-
* The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
13-
* A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library...
14-
* A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
7+
**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series.
8+
* The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product
9+
* The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio
10+
* The BSP Drivers of each evaluation or demonstration board provided by this STM32 series
11+
* A consistent set of middlewares components such as RTOS, FatFS, TCP-IP, Graphic ...
12+
* A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series
1513

1614
Two models of publication are proposed for the STM32Cube embedded software:
17-
* The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
18-
* The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions.
15+
* The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series)
16+
* The **MCU component** : progressively from June 2021, each STM32Cube software module being part of the STM32Cube MCU Package, are delivered as an individual repo, allowing the user to select and get only the required software functions.
1917

2018
## Description
2119

@@ -41,7 +39,9 @@ It is **crucial** that you use a consistent set of versions for the CMSIS Core -
4139

4240
HAL Driver | CMSIS Device | CMSIS Core | Was delivered in the full MCU package
4341
------------- | --------------- | ---------- | -------------------------------------
44-
Tag v1.0.0 | Tag v1.0.0 | Tag v5.6.0_cm33 | Tag v1.0.0 (and following, if any, till next tag)
42+
Tag v1.0.0 | Tag v1.0.0 | Tag v560_cm33 | Tag v1.0.0 (and following, if any, till next tag)
43+
Tag v1.0.1 | Tag v1.0.1 | Tag v560_cm33 | Tag v1.0.1 (and following, if any, till next tag)
44+
Tag v1.0.2 | Tag v1.0.2 | Tag v560_cm33 | Tag v1.0.2 (and following, if any, till next tag)
4545

4646

4747
The full **STM32CubeU5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeU5).
@@ -50,4 +50,4 @@ The full **STM32CubeU5** MCU package is available [here](https://github.com/STMi
5050

5151
If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32u5xx_hal_driver/issues/new/choose).
5252

53-
For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/topic/0TO0X000000BSqSWAW/stm32-mcus).
53+
For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).

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