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adjusted formatting
1 parent cd8c68a commit b5a5d30

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-8
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+5
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variants/STM32L4xx/L431C(B-C)(T-U)/generic_clock.c

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -26,8 +26,7 @@ WEAK void SystemClock_Config(void)
2626

2727
/** Configure the main internal regulator output voltage
2828
*/
29-
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
30-
{
29+
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
3130
Error_Handler();
3231
}
3332

@@ -44,22 +43,20 @@ WEAK void SystemClock_Config(void)
4443
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
4544
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
4645
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
47-
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
48-
{
46+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
4947
Error_Handler();
5048
}
5149

5250
/** Initializes the CPU, AHB and APB buses clocks
5351
*/
54-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
55-
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
52+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
53+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
5654
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
5755
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
5856
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
5957
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
6058

61-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
62-
{
59+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
6360
Error_Handler();
6461
}
6562
}

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