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Merge branch 'main' into variant/RAK3172-Module
2 parents 2948e50 + 97030d8 commit 9d8f71e

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+1575
-1507
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12 files changed

+1575
-1507
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boards.txt

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -9772,15 +9772,6 @@ GenWL.build.flash_offset=0x0
97729772
GenWL.upload.maximum_size=0
97739773
GenWL.upload.maximum_data_size=0
97749774

9775-
# Generic node SE by The Things Industries
9776-
GenWL.menu.pnum.GENERIC_NODE_SE_TTI=Generic Node SE (TTI)
9777-
GenWL.menu.pnum.GENERIC_NODE_SE_TTI.upload.maximum_size=262144
9778-
GenWL.menu.pnum.GENERIC_NODE_SE_TTI.upload.maximum_data_size=65536
9779-
GenWL.menu.pnum.GENERIC_NODE_SE_TTI.build.board=GENERIC_NODE_SE_TTI
9780-
GenWL.menu.pnum.GENERIC_NODE_SE_TTI.build.product_line=STM32WL55xx
9781-
GenWL.menu.pnum.GENERIC_NODE_SE_TTI.build.variant_h=variant_GENERIC_NODE_SE_TTI.h
9782-
GenWL.menu.pnum.GENERIC_NODE_SE_TTI.build.variant=STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U
9783-
97849775
# Generic WL54CCUx
97859776
GenWL.menu.pnum.GENERIC_WL54CCUX=Generic WL54CCUx
97869777
GenWL.menu.pnum.GENERIC_WL54CCUX.upload.maximum_size=262144
@@ -10465,6 +10456,19 @@ LoRa.menu.pnum.ACSIP_S76S.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
1046510456
LoRa.menu.pnum.ACSIP_S76S.build.cmsis_lib_gcc=arm_cortexM0l_math
1046610457
LoRa.menu.pnum.ACSIP_S76S.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0
1046710458

10459+
# Generic node SE by The Things Industries
10460+
LoRa.menu.pnum.GENERIC_NODE_SE_TTI=Generic Node SE (TTI)
10461+
LoRa.menu.pnum.GENERIC_NODE_SE_TTI.upload.maximum_size=262144
10462+
LoRa.menu.pnum.GENERIC_NODE_SE_TTI.upload.maximum_data_size=65536
10463+
LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.mcu=cortex-m4
10464+
LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.board=GENERIC_NODE_SE_TTI
10465+
LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.series=STM32WLxx
10466+
LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.product_line=STM32WL55xx
10467+
LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.variant=STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U
10468+
LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.variant_h=variant_GENERIC_NODE_SE_TTI.h
10469+
LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.cmsis_lib_gcc=arm_cortexM4l_math
10470+
LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.st_extra_flags=-D{build.product_line} -DUSE_CM4_STARTUP_FILE {build.xSerial}
10471+
1046810472
# LORA_E5_MINI board
1046910473
LoRa.menu.pnum.LORA_E5_MINI=LoRa-E5 mini
1047010474
LoRa.menu.pnum.LORA_E5_MINI.upload.maximum_size=262144

cmake/boards_db.cmake

Lines changed: 1542 additions & 1485 deletions
Large diffs are not rendered by default.

variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins_ARMED_V1.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -319,7 +319,7 @@ WEAK const PinMap PinMap_CAN_TD[] = {
319319

320320
//*** ETHERNET ***
321321

322-
#ifdef HAL_ETH_MODULE_ENABLED
322+
#if defined(HAL_ETH_MODULE_ENABLED) || defined(HAL_ETH_LEGACY_MODULE_ENABLED)
323323
WEAK const PinMap PinMap_Ethernet[] = {
324324
{PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
325325
{PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK

variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins_BLACK_F407VX.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -319,7 +319,7 @@ WEAK const PinMap PinMap_CAN_TD[] = {
319319

320320
//*** ETHERNET ***
321321

322-
#ifdef HAL_ETH_MODULE_ENABLED
322+
#if defined(HAL_ETH_MODULE_ENABLED) || defined(HAL_ETH_LEGACY_MODULE_ENABLED)
323323
WEAK const PinMap PinMap_Ethernet[] = {
324324
{PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
325325
{PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK

variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins_BLUE_F407VE_MINI.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -319,7 +319,7 @@ WEAK const PinMap PinMap_CAN_TD[] = {
319319

320320
//*** ETHERNET ***
321321

322-
#ifdef HAL_ETH_MODULE_ENABLED
322+
#if defined(HAL_ETH_MODULE_ENABLED) || defined(HAL_ETH_LEGACY_MODULE_ENABLED)
323323
WEAK const PinMap PinMap_Ethernet[] = {
324324
{PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
325325
{PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK

variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins_FK407M1.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -319,7 +319,7 @@ WEAK const PinMap PinMap_CAN_TD[] = {
319319

320320
//*** ETHERNET ***
321321

322-
#ifdef HAL_ETH_MODULE_ENABLED
322+
#if defined(HAL_ETH_MODULE_ENABLED) || defined(HAL_ETH_LEGACY_MODULE_ENABLED)
323323
WEAK const PinMap PinMap_Ethernet[] = {
324324
{PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
325325
{PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK

variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins_PRNTR_V1.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -319,7 +319,7 @@ WEAK const PinMap PinMap_CAN_TD[] = {
319319

320320
//*** ETHERNET ***
321321

322-
#ifdef HAL_ETH_MODULE_ENABLED
322+
#if defined(HAL_ETH_MODULE_ENABLED) || defined(HAL_ETH_LEGACY_MODULE_ENABLED)
323323
WEAK const PinMap PinMap_Ethernet[] = {
324324
// {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
325325
// {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK

variants/STM32F4xx/F407V(E-G)T_F417V(E-G)T/PeripheralPins_PRNTR_V2.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -319,7 +319,7 @@ WEAK const PinMap PinMap_CAN_TD[] = {
319319

320320
//*** ETHERNET ***
321321

322-
#ifdef HAL_ETH_MODULE_ENABLED
322+
#if defined(HAL_ETH_MODULE_ENABLED) || defined(HAL_ETH_LEGACY_MODULE_ENABLED)
323323
WEAK const PinMap PinMap_Ethernet[] = {
324324
// {PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
325325
// {PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK

variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins_BLACK_F407ZX.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -339,7 +339,7 @@ WEAK const PinMap PinMap_CAN_TD[] = {
339339

340340
//*** ETHERNET ***
341341

342-
#ifdef HAL_ETH_MODULE_ENABLED
342+
#if defined(HAL_ETH_MODULE_ENABLED) || defined(HAL_ETH_LEGACY_MODULE_ENABLED)
343343
WEAK const PinMap PinMap_Ethernet[] = {
344344
{PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
345345
{PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK

variants/STM32F4xx/F407Z(E-G)T_F417Z(E-G)T/PeripheralPins_VCCGND_F407ZG_MINI.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -339,7 +339,7 @@ WEAK const PinMap PinMap_CAN_TD[] = {
339339

340340
//*** ETHERNET ***
341341

342-
#ifdef HAL_ETH_MODULE_ENABLED
342+
#if defined(HAL_ETH_MODULE_ENABLED) || defined(HAL_ETH_LEGACY_MODULE_ENABLED)
343343
WEAK const PinMap PinMap_Ethernet[] = {
344344
{PA_0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
345345
{PA_1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK

variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_GENERIC_NODE_SE_TTI.cpp

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -70,15 +70,20 @@ WEAK void SystemClock_Config(void)
7070
RCC_OscInitTypeDef RCC_OscInitStruct = {};
7171
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
7272

73+
/** Configure LSE Drive Capability
74+
*/
75+
HAL_PWR_EnableBkUpAccess();
76+
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
7377
/** Configure the main internal regulator output voltage
7478
*/
75-
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
79+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
7680
/** Initializes the CPU, AHB and APB busses clocks
7781
*/
78-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
82+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
83+
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
7984
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
8085
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
81-
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
86+
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
8287
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
8388
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
8489
Error_Handler();
@@ -94,12 +99,12 @@ WEAK void SystemClock_Config(void)
9499
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
95100
RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1;
96101

97-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) {
102+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
98103
Error_Handler();
99104
}
100105
}
101106

102107
#ifdef __cplusplus
103108
}
104109
#endif
105-
#endif /* ARDUINO_GENERIC_* */
110+
#endif /* ARDUINO_GENERIC_NODE_SE_TTI */

variants/STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I/CMakeLists.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,9 @@ target_link_libraries(variant INTERFACE variant_usage)
2121
add_library(variant_bin STATIC EXCLUDE_FROM_ALL
2222
generic_clock.c
2323
PeripheralPins.c
24+
PeripheralPins_LORA_E5_MINI.c
2425
variant_generic.cpp
26+
variant_LORA_E5_MINI.cpp
2527
variant_NUCLEO_WL55JC1.cpp
2628
)
2729
target_link_libraries(variant_bin PUBLIC variant_usage)

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