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431 | 431 | #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
|
432 | 432 | #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
|
433 | 433 |
|
434 |
| -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) |
| 434 | +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) |
435 | 435 | #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
436 | 436 | #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
437 | 437 | #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
|
438 | 438 | #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
|
439 |
| -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ |
| 439 | +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ |
440 | 440 |
|
441 | 441 | #if defined(STM32L1)
|
442 | 442 | #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
|
|
2119 | 2119 | #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
|
2120 | 2120 | #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
|
2121 | 2121 | #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
|
| 2122 | + |
| 2123 | +#if defined(STM32WB) |
| 2124 | +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE |
| 2125 | +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE |
| 2126 | +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE |
| 2127 | +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE |
| 2128 | +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET |
| 2129 | +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET |
| 2130 | +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED |
| 2131 | +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED |
| 2132 | +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED |
| 2133 | +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED |
| 2134 | +#define QSPI_IRQHandler QUADSPI_IRQHandler |
| 2135 | +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ |
| 2136 | + |
2122 | 2137 | #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
|
2123 | 2138 | #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
|
2124 | 2139 | #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
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|
2787 | 2802 | #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
2788 | 2803 | #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
2789 | 2804 |
|
2790 |
| -#if defined(STM32WB) || defined(STM32G0) |
| 2805 | +#if defined(STM32L4) |
| 2806 | +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE |
| 2807 | +#elif defined(STM32WB) || defined(STM32G0) |
2791 | 2808 | #else
|
2792 | 2809 | #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
2793 | 2810 | #endif
|
|
3038 | 3055 | #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
|
3039 | 3056 | #endif
|
3040 | 3057 |
|
| 3058 | +#if defined(STM32H7) |
| 3059 | +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback |
| 3060 | +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback |
| 3061 | +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback |
| 3062 | +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback |
| 3063 | +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback |
| 3064 | +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback |
| 3065 | +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback |
| 3066 | +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback |
| 3067 | +#endif |
3041 | 3068 | /**
|
3042 | 3069 | * @}
|
3043 | 3070 | */
|
|
3252 | 3279 | * @}
|
3253 | 3280 | */
|
3254 | 3281 |
|
| 3282 | +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose |
| 3283 | + * @{ |
| 3284 | + */ |
| 3285 | +#if defined(STM32H7) |
| 3286 | +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow |
| 3287 | +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT |
| 3288 | +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA |
| 3289 | +#endif |
| 3290 | +/** |
| 3291 | + * @} |
| 3292 | + */ |
3255 | 3293 |
|
3256 | 3294 | /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
|
3257 | 3295 | * @{
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