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[WB] Update STM32WBxx HAL Drivers to v1.4.0
Included in STM32CubeWB FW V1.4.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 29d083b commit 7ecc1f8

25 files changed

+509
-164
lines changed

‎system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

Lines changed: 109 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -236,12 +236,12 @@
236236
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
237237
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
238238

239-
#if defined(STM32G4)
240-
#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)
241-
#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)
239+
#if defined(STM32G4) || defined(STM32H7)
240+
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
241+
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
242242
#endif
243243

244-
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)
244+
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32H7) || defined(STM32F4)
245245
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
246246
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
247247
#endif
@@ -306,8 +306,17 @@
306306
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
307307
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
308308

309+
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
310+
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
311+
#endif
312+
309313
#endif /* STM32L4 */
310314

315+
#if defined(STM32G0)
316+
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
317+
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
318+
#endif
319+
311320
#if defined(STM32H7)
312321

313322
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@@ -365,6 +374,9 @@
365374
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
366375
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
367376

377+
#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
378+
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
379+
368380
#endif /* STM32H7 */
369381

370382
/**
@@ -566,7 +578,14 @@
566578
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
567579
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
568580
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
569-
#endif
581+
582+
#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) \
583+
|| defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
584+
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
585+
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
586+
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
587+
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
588+
#endif /* STM32H7 */
570589

571590
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
572591
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
@@ -737,32 +756,65 @@
737756
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
738757
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
739758
#endif /* STM32H7 */
740-
759+
741760
#if defined(STM32F3)
742-
#define HRTIM_OUTPUTSET_TIMEV_1 HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
743-
#define HRTIM_OUTPUTSET_TIMEV_2 HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
744-
#define HRTIM_OUTPUTSET_TIMEV_3 HRTIM_OUTPUTSET_TIMAEV3_TIMBCMP4
745-
#define HRTIM_OUTPUTSET_TIMEV_4 HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2
746-
#define HRTIM_OUTPUTSET_TIMEV_5 HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3
747-
#define HRTIM_OUTPUTSET_TIMEV_6 HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1
748-
#define HRTIM_OUTPUTSET_TIMEV_7 HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2
749-
#define HRTIM_OUTPUTSET_TIMEV_8 HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3
750-
#define HRTIM_OUTPUTSET_TIMEV_9 HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4
751-
752-
#define HRTIM_OUTPUTRESET_TIMEV_1 HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
753-
#define HRTIM_OUTPUTRESET_TIMEV_2 HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
754-
#define HRTIM_OUTPUTRESET_TIMEV_3 HRTIM_OUTPUTRESET_TIMAEV3_TIMBCMP4
755-
#define HRTIM_OUTPUTRESET_TIMEV_4 HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2
756-
#define HRTIM_OUTPUTRESET_TIMEV_5 HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3
757-
#define HRTIM_OUTPUTRESET_TIMEV_6 HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1
758-
#define HRTIM_OUTPUTRESET_TIMEV_7 HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2
759-
#define HRTIM_OUTPUTRESET_TIMEV_8 HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3
760-
#define HRTIM_OUTPUTRESET_TIMEV_9 HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4
761-
762-
#define HRTIM_EVENTSRC_1 HRTIM_EEV1SRC_GPIO
763-
#define HRTIM_EVENTSRC_2 HRTIM_EEV2SRC_GPIO
764-
#define HRTIM_EVENTSRC_3 HRTIM_EEV3SRC_GPIO
765-
#define HRTIM_EVENTSRC_4 HRTIM_EEV4SRC_GPIO
761+
/** @brief Constants defining available sources associated to external events.
762+
*/
763+
#define HRTIM_EVENTSRC_1 (0x00000000U)
764+
#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
765+
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
766+
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
767+
768+
/** @brief Constants defining the events that can be selected to configure the
769+
* set/reset crossbar of a timer output
770+
*/
771+
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
772+
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
773+
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
774+
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
775+
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
776+
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
777+
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
778+
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
779+
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
780+
781+
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
782+
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
783+
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
784+
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
785+
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
786+
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
787+
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
788+
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
789+
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
790+
791+
/** @brief Constants defining the event filtering applied to external events
792+
* by a timer
793+
*/
794+
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
795+
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
796+
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
797+
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
798+
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
799+
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
800+
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
801+
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
802+
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
803+
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
804+
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
805+
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
806+
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
807+
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
808+
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
809+
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
810+
811+
/** @brief Constants defining the DLL calibration periods (in micro seconds)
812+
*/
813+
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
814+
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
815+
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
816+
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
817+
766818
#endif /* STM32F3 */
767819
/**
768820
* @}
@@ -903,7 +955,7 @@
903955
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
904956
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
905957

906-
#if defined(STM32L1) || defined(STM32L4)
958+
#if defined(STM32L1) || defined(STM32L4) || defined(STM32H7)
907959
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
908960
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
909961
#endif
@@ -994,6 +1046,16 @@
9941046
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
9951047
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
9961048

1049+
#if defined(STM32H7)
1050+
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
1051+
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
1052+
1053+
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
1054+
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
1055+
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
1056+
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
1057+
#endif /* STM32H7 */
1058+
9971059
/**
9981060
* @}
9991061
*/
@@ -1409,12 +1471,12 @@
14091471
#endif
14101472
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
14111473
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
1412-
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ)
1474+
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
14131475
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
14141476
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
14151477
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
14161478
#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
1417-
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7A3xxQ || STM32H7B3xxQ */
1479+
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
14181480

14191481
/**
14201482
* @}
@@ -1445,16 +1507,18 @@
14451507

14461508
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
14471509

1448-
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
1510+
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
14491511
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
14501512
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
14511513
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
14521514
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
1515+
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
1516+
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
14531517
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
14541518
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
14551519
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
14561520
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
1457-
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
1521+
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
14581522

14591523
#if defined(STM32F4)
14601524
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@@ -1473,6 +1537,13 @@
14731537
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
14741538
* @{
14751539
*/
1540+
1541+
#if defined(STM32G0)
1542+
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
1543+
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
1544+
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
1545+
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
1546+
#endif
14761547
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
14771548
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
14781549
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
@@ -1545,14 +1616,14 @@
15451616
#define HAL_TIM_DMAError TIM_DMAError
15461617
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
15471618
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
1548-
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)
1619+
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
15491620
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
15501621
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
15511622
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
15521623
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
15531624
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
15541625
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
1555-
#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
1626+
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
15561627
/**
15571628
* @}
15581629
*/
@@ -3278,7 +3349,7 @@
32783349
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
32793350
* @{
32803351
*/
3281-
#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
3352+
#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined STM32G4
32823353
#else
32833354
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
32843355
#endif

‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_conf_template.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -174,17 +174,17 @@
174174
*/
175175
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
176176
#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */
177-
#define USE_RTOS 0
178-
#define PREFETCH_ENABLE 0
179-
#define INSTRUCTION_CACHE_ENABLE 1
180-
#define DATA_CACHE_ENABLE 1
177+
#define USE_RTOS 0U
178+
#define PREFETCH_ENABLE 0U
179+
#define INSTRUCTION_CACHE_ENABLE 1U
180+
#define DATA_CACHE_ENABLE 1U
181181

182182
/* ########################## Assert Selection ############################## */
183183
/**
184184
* @brief Uncomment the line below to expanse the "assert_param" macro in the
185185
* HAL drivers code
186186
*/
187-
/* #define USE_FULL_ASSERT 1 */
187+
/* #define USE_FULL_ASSERT 1U */
188188

189189
/* ################## SPI peripheral configuration ########################## */
190190

‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cryp.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -186,6 +186,8 @@ typedef struct
186186

187187
uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */
188188

189+
uint32_t SizesSum_saved; /*!< copy of SizesSum when processing is suspended */
190+
189191
uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */
190192

191193
FunctionalState AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */

‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c_ex.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,9 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
118118
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
119119
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
120120
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
121+
122+
123+
121124
/**
122125
* @}
123126
*/

‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_ipcc.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,11 @@
66
******************************************************************************
77
* @attention
88
*
9-
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
9+
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
1010
* All rights reserved.</center></h2>
1111
*
1212
* This software component is licensed by ST under BSD 3-Clause license,
13-
* the "License"; You may not use this file except in compliance with the
13+
* the "License"; You may not use this file except in compliance with the
1414
* License. You may obtain a copy of the License at:
1515
* opensource.org/licenses/BSD-3-Clause
1616
*
@@ -28,6 +28,7 @@ extern "C" {
2828
/* Includes ------------------------------------------------------------------*/
2929
#include "stm32wbxx_hal_def.h"
3030

31+
#if defined(IPCC)
3132

3233
/** @addtogroup STM32WBxx_HAL_Driver
3334
* @{
@@ -253,6 +254,7 @@ void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_
253254
/**
254255
* @}
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*/
257+
#endif /* IPCC */
256258

257259
#ifdef __cplusplus
258260
}

‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_lptim.h

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -592,14 +592,25 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
592592
* @{
593593
*/
594594

595+
/** @addtogroup LPTIM_Exported_Functions_Group1
596+
* @brief Initialization and Configuration functions.
597+
* @{
598+
*/
595599
/* Initialization/de-initialization functions ********************************/
596600
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
597601
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
598602

599603
/* MSP functions *************************************************************/
600604
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
601605
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
606+
/**
607+
* @}
608+
*/
602609

610+
/** @addtogroup LPTIM_Exported_Functions_Group2
611+
* @brief Start-Stop operation functions.
612+
* @{
613+
*/
603614
/* Start/Stop operation functions *********************************************/
604615
/* ################################# PWM Mode ################################*/
605616
/* Blocking mode: Polling */
@@ -648,12 +659,26 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
648659
/* Non-Blocking mode: Interrupt */
649660
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
650661
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
662+
/**
663+
* @}
664+
*/
651665

666+
/** @addtogroup LPTIM_Exported_Functions_Group3
667+
* @brief Read operation functions.
668+
* @{
669+
*/
652670
/* Reading operation functions ************************************************/
653671
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
654672
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
655673
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
674+
/**
675+
* @}
676+
*/
656677

678+
/** @addtogroup LPTIM_Exported_Functions_Group4
679+
* @brief LPTIM IRQ handler and callback functions.
680+
* @{
681+
*/
657682
/* LPTIM IRQ functions *******************************************************/
658683
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
659684

@@ -671,9 +696,19 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
671696
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
672697
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
673698
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
699+
/**
700+
* @}
701+
*/
674702

703+
/** @addtogroup LPTIM_Group5
704+
* @brief Peripheral State functions.
705+
* @{
706+
*/
675707
/* Peripheral State functions ************************************************/
676708
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
709+
/**
710+
* @}
711+
*/
677712

678713
/**
679714
* @}

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