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Merge pull request #1398 from fpistm/G0B1RE
Add generic G0B1R(B-C-E)T, G0C1R(C-E)T and Nucleo-G0B1RE
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‎README.md

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@@ -105,6 +105,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :green_heart: | STM32F411RE | [Nucleo F411RE](http://www.st.com/en/evaluation-tools/nucleo-f411re.html) | *0.2.1* | |
106106
| :green_heart: | STM32F446RE | [Nucleo F446RE](http://www.st.com/en/evaluation-tools/nucleo-f446re.html) | *1.1.1* | |
107107
| :green_heart: | STM32G071RB | [Nucleo G071RB](https://www.st.com/en/evaluation-tools/nucleo-g071rb.html) | *1.6.0* | |
108+
| :yellow_heart: | STM32G0B1RE | [Nucleo G0B1RE](https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html) | **2.1.0** | |
108109
| :green_heart: | STM32G431RB | [Nucleo G431RB](https://www.st.com/en/evaluation-tools/nucleo-g431rb.html) | *1.7.0* | |
109110
| :green_heart: | STM32G474RE | [Nucleo G474RE](https://www.st.com/en/evaluation-tools/nucleo-g474re.html) | *1.7.0* | |
110111
| :yellow_heart: | STM32L010RB | [Nucleo L010RB](https://www.st.com/en/evaluation-tools/nucleo-l010rb.html) | **2.1.0** | |
@@ -289,6 +290,8 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :green_heart: | STM32G041K6<br>STM32G041K8 | Generic Board | *2.0.0* | |
290291
| :green_heart: | STM32G071R6<br>STM32G071R8<br>STM32G071RB | Generic Board | *2.0.0* | |
291292
| :green_heart: | STM32G081RB | Generic Board | *2.0.0* | |
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| :yellow_heart: | STM32G0B1RB<br>STM32G0B1RC<br>STM32G0B1RE | Generic Board | **2.1.0** | |
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| :yellow_heart: | STM32G0C1RB<br>STM32G0C1RE | Generic Board | **2.1.0** | |
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293296
### Generic STM32G4 boards
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‎boards.txt

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@@ -347,6 +347,19 @@ Nucleo_64.menu.pnum.NUCLEO_G071RB.build.variant=STM32G0xx/G071R(6-8)T_G071RB(I-T
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Nucleo_64.menu.pnum.NUCLEO_G071RB.build.cmsis_lib_gcc=arm_cortexM0l_math
348348
Nucleo_64.menu.pnum.NUCLEO_G071RB.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0
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# NUCLEO_G0B1RE board
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Nucleo_64.menu.pnum.NUCLEO_G0B1RE=Nucleo G0B1RE
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Nucleo_64.menu.pnum.NUCLEO_G0B1RE.node=NOD_G0B1RE
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Nucleo_64.menu.pnum.NUCLEO_G0B1RE.upload.maximum_size=262144
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Nucleo_64.menu.pnum.NUCLEO_G0B1RE.upload.maximum_data_size=147456
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Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.mcu=cortex-m0plus
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Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.board=NUCLEO_G0B1RE
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Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.series=STM32G0xx
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Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.product_line=STM32G0B1xx
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Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.variant=STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T
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Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.cmsis_lib_gcc=arm_cortexM0l_math
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Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0
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# NUCLEO_G431RB board
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Nucleo_64.menu.pnum.NUCLEO_G431RB=Nucleo G431RB
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Nucleo_64.menu.pnum.NUCLEO_G431RB.node="NODE_G431RB,NOD_G431RB"
@@ -3261,6 +3274,46 @@ GenG0.menu.pnum.GENERIC_G081RBTX.build.board=GENERIC_G081RBTX
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GenG0.menu.pnum.GENERIC_G081RBTX.build.product_line=STM32G081xx
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GenG0.menu.pnum.GENERIC_G081RBTX.build.variant=STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)
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# Generic G0B1RBTx
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GenG0.menu.pnum.GENERIC_G0B1RBTX=Generic G0B1RBTx
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GenG0.menu.pnum.GENERIC_G0B1RBTX.upload.maximum_size=131072
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GenG0.menu.pnum.GENERIC_G0B1RBTX.upload.maximum_data_size=147456
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GenG0.menu.pnum.GENERIC_G0B1RBTX.build.board=GENERIC_G0B1RBTX
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GenG0.menu.pnum.GENERIC_G0B1RBTX.build.product_line=STM32G0B1xx
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GenG0.menu.pnum.GENERIC_G0B1RBTX.build.variant=STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T
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# Generic G0B1RCTx
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GenG0.menu.pnum.GENERIC_G0B1RCTX=Generic G0B1RCTx
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GenG0.menu.pnum.GENERIC_G0B1RCTX.upload.maximum_size=262144
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GenG0.menu.pnum.GENERIC_G0B1RCTX.upload.maximum_data_size=147456
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GenG0.menu.pnum.GENERIC_G0B1RCTX.build.board=GENERIC_G0B1RCTX
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GenG0.menu.pnum.GENERIC_G0B1RCTX.build.product_line=STM32G0B1xx
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GenG0.menu.pnum.GENERIC_G0B1RCTX.build.variant=STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T
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# Generic G0B1RETx
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GenG0.menu.pnum.GENERIC_G0B1RETX=Generic G0B1RETx
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GenG0.menu.pnum.GENERIC_G0B1RETX.upload.maximum_size=524288
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GenG0.menu.pnum.GENERIC_G0B1RETX.upload.maximum_data_size=147456
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GenG0.menu.pnum.GENERIC_G0B1RETX.build.board=GENERIC_G0B1RETX
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GenG0.menu.pnum.GENERIC_G0B1RETX.build.product_line=STM32G0B1xx
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GenG0.menu.pnum.GENERIC_G0B1RETX.build.variant=STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T
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# Generic G0C1RCTx
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GenG0.menu.pnum.GENERIC_G0C1RCTX=Generic G0C1RCTx
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GenG0.menu.pnum.GENERIC_G0C1RCTX.upload.maximum_size=262144
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GenG0.menu.pnum.GENERIC_G0C1RCTX.upload.maximum_data_size=147456
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GenG0.menu.pnum.GENERIC_G0C1RCTX.build.board=GENERIC_G0C1RCTX
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GenG0.menu.pnum.GENERIC_G0C1RCTX.build.product_line=STM32G0C1xx
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GenG0.menu.pnum.GENERIC_G0C1RCTX.build.variant=STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T
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# Generic G0C1RETx
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GenG0.menu.pnum.GENERIC_G0C1RETX=Generic G0C1RETx
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GenG0.menu.pnum.GENERIC_G0C1RETX.upload.maximum_size=524288
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GenG0.menu.pnum.GENERIC_G0C1RETX.upload.maximum_data_size=147456
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GenG0.menu.pnum.GENERIC_G0C1RETX.build.board=GENERIC_G0C1RETX
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GenG0.menu.pnum.GENERIC_G0C1RETX.build.product_line=STM32G0C1xx
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GenG0.menu.pnum.GENERIC_G0C1RETX.build.variant=STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T
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# Upload menu
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GenG0.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD)
32663319
GenG0.menu.upload_method.swdMethod.upload.protocol=0

‎variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/generic_clock.c

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@@ -22,8 +22,49 @@
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*/
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WEAK void SystemClock_Config(void)
2424
{
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/* SystemClock_Config can be generated by STM32CubeMX */
26-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
25+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
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/** Configure the main internal regulator output voltage
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*/
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HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
34+
*/
35+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
36+
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
42+
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
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RCC_OscInitStruct.PLL.PLLN = 8;
44+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
48+
Error_Handler();
49+
}
50+
/** Initializes the CPU, AHB and APB buses clocks
51+
*/
52+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
53+
| RCC_CLOCKTYPE_PCLK1;
54+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
57+
58+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
59+
Error_Handler();
60+
}
61+
/** Initializes the peripherals clocks
62+
*/
63+
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
64+
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
65+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
66+
Error_Handler();
67+
}
2768
}
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#endif /* ARDUINO_GENERIC_* */

‎variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/ldscript.ld

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/**
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******************************************************************************
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* @file LinkerScript.ld
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* @author Auto-generated by STM32CubeIDE
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* @brief Linker script for STM32G0B1RETx Device from STM32G0 series
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* 512Kbytes FLASH
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* 144Kbytes RAM
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*
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* Set heap size, stack size and stack location according
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* to application requirements.
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*
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* Set memory bank area and size if external memory is used
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******************************************************************************
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* @attention
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*
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* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
29+
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/* Highest address of the user mode stack */
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_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
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_Min_Heap_Size = 0x200; /* required amount of heap */
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_Min_Stack_Size = 0x400; /* required amount of stack */
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/* Memories definition */
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MEMORY
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{
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
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FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
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}
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/* Sections */
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SECTIONS
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{
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/* The startup code into "FLASH" Rom type memory */
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.isr_vector :
48+
{
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. = ALIGN(4);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
52+
} >FLASH
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/* The program code and other data into "FLASH" Rom type memory */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(4);
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_etext = .; /* define a global symbols at end of code */
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} >FLASH
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/* Constant data into "FLASH" Rom type memory */
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.rodata :
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{
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. = ALIGN(4);
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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. = ALIGN(4);
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} >FLASH
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.ARM.extab : {
81+
. = ALIGN(4);
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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. = ALIGN(4);
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} >FLASH
85+
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.ARM : {
87+
. = ALIGN(4);
88+
__exidx_start = .;
89+
*(.ARM.exidx*)
90+
__exidx_end = .;
91+
. = ALIGN(4);
92+
} >FLASH
93+
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.preinit_array :
95+
{
96+
. = ALIGN(4);
97+
PROVIDE_HIDDEN (__preinit_array_start = .);
98+
KEEP (*(.preinit_array*))
99+
PROVIDE_HIDDEN (__preinit_array_end = .);
100+
. = ALIGN(4);
101+
} >FLASH
102+
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.init_array :
104+
{
105+
. = ALIGN(4);
106+
PROVIDE_HIDDEN (__init_array_start = .);
107+
KEEP (*(SORT(.init_array.*)))
108+
KEEP (*(.init_array*))
109+
PROVIDE_HIDDEN (__init_array_end = .);
110+
. = ALIGN(4);
111+
} >FLASH
112+
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.fini_array :
114+
{
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. = ALIGN(4);
116+
PROVIDE_HIDDEN (__fini_array_start = .);
117+
KEEP (*(SORT(.fini_array.*)))
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KEEP (*(.fini_array*))
119+
PROVIDE_HIDDEN (__fini_array_end = .);
120+
. = ALIGN(4);
121+
} >FLASH
122+
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/* Used by the startup to initialize data */
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_sidata = LOADADDR(.data);
125+
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/* Initialized data sections into "RAM" Ram type memory */
127+
.data :
128+
{
129+
. = ALIGN(4);
130+
_sdata = .; /* create a global symbol at data start */
131+
*(.data) /* .data sections */
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*(.data*) /* .data* sections */
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*(.RamFunc) /* .RamFunc sections */
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*(.RamFunc*) /* .RamFunc* sections */
135+
136+
. = ALIGN(4);
137+
_edata = .; /* define a global symbol at data end */
138+
139+
} >RAM AT> FLASH
140+
141+
/* Uninitialized data section into "RAM" Ram type memory */
142+
. = ALIGN(4);
143+
.bss :
144+
{
145+
/* This is used by the startup in order to initialize the .bss section */
146+
_sbss = .; /* define a global symbol at bss start */
147+
__bss_start__ = _sbss;
148+
*(.bss)
149+
*(.bss*)
150+
*(COMMON)
151+
152+
. = ALIGN(4);
153+
_ebss = .; /* define a global symbol at bss end */
154+
__bss_end__ = _ebss;
155+
} >RAM
156+
157+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
158+
._user_heap_stack :
159+
{
160+
. = ALIGN(8);
161+
PROVIDE ( end = . );
162+
PROVIDE ( _end = . );
163+
. = . + _Min_Heap_Size;
164+
. = . + _Min_Stack_Size;
165+
. = ALIGN(8);
166+
} >RAM
167+
168+
/* Remove information from the compiler libraries */
169+
/DISCARD/ :
170+
{
171+
libc.a ( * )
172+
libm.a ( * )
173+
libgcc.a ( * )
174+
}
175+
176+
.ARM.attributes 0 : { *(.ARM.attributes) }
177+
}

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