Skip to content

Commit 675149e

Browse files
fpistmfpistm
committed
system(WL) update STM32WLxx HAL Drivers to v1.3.0
Included in STM32CubeWL FW 1.3.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 3ca6815 commit 675149e

File tree

72 files changed

+3449
-2140
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

72 files changed

+3449
-2140
lines changed

‎system/Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

Lines changed: 68 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -37,14 +37,16 @@ extern "C" {
3737
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
3838
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
3939
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
40-
#if defined(STM32U5)
40+
#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
4141
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
4242
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
4343
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
4444
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
45+
#if defined(STM32U5)
4546
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
4647
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
4748
#endif /* STM32U5 */
49+
#endif /* STM32U5 || STM32H7 || STM32MP1 */
4850
/**
4951
* @}
5052
*/
@@ -110,6 +112,7 @@ extern "C" {
110112
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
111113
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
112114
#endif /* STM32U5 */
115+
113116
/**
114117
* @}
115118
*/
@@ -211,6 +214,11 @@ extern "C" {
211214
#endif
212215

213216
#endif
217+
218+
#if defined(STM32U5)
219+
#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
220+
#endif
221+
214222
/**
215223
* @}
216224
*/
@@ -231,9 +239,11 @@ extern "C" {
231239
/** @defgroup CRC_Aliases CRC API aliases
232240
* @{
233241
*/
242+
#if defined(STM32C0)
243+
#else
234244
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
235245
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
236-
246+
#endif
237247
/**
238248
* @}
239249
*/
@@ -263,7 +273,7 @@ extern "C" {
263273
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
264274
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
265275

266-
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
276+
#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
267277
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
268278
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
269279
#endif
@@ -500,7 +510,7 @@ extern "C" {
500510
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
501511
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
502512
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
503-
#if defined(STM32G0)
513+
#if defined(STM32G0) || defined(STM32C0)
504514
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
505515
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
506516
#else
@@ -525,6 +535,9 @@ extern "C" {
525535
#define OB_USER_nBOOT0 OB_USER_NBOOT0
526536
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
527537
#define OB_nBOOT0_SET OB_NBOOT0_SET
538+
#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
539+
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
540+
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
528541
#endif /* STM32U5 */
529542

530543
/**
@@ -667,6 +680,8 @@ extern "C" {
667680

668681
#if defined(STM32U5)
669682
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
683+
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
684+
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
670685
#endif /* STM32U5 */
671686
/**
672687
* @}
@@ -677,7 +692,9 @@ extern "C" {
677692
*/
678693
#if defined(STM32U5)
679694
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
695+
#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
680696
#endif /* STM32U5 */
697+
681698
/**
682699
* @}
683700
*/
@@ -996,7 +1013,7 @@ extern "C" {
9961013
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
9971014
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
9981015

999-
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
1016+
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
10001017
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
10011018
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
10021019
#endif
@@ -1080,8 +1097,8 @@ extern "C" {
10801097
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
10811098

10821099
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
1083-
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
1084-
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
1100+
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
1101+
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
10851102
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
10861103

10871104
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
@@ -1092,15 +1109,22 @@ extern "C" {
10921109
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
10931110
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
10941111

1112+
#if defined(STM32F7)
1113+
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
1114+
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
1115+
#endif /* STM32F7 */
1116+
10951117
#if defined(STM32H7)
10961118
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
10971119
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
1120+
#endif /* STM32H7 */
10981121

1122+
#if defined(STM32F7) || defined(STM32H7)
10991123
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
11001124
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
11011125
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
1102-
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
1103-
#endif /* STM32H7 */
1126+
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
1127+
#endif /* STM32F7 || STM32H7 */
11041128

11051129
/**
11061130
* @}
@@ -1705,7 +1729,6 @@ extern "C" {
17051729
#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
17061730
#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
17071731
#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
1708-
#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
17091732
#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
17101733
#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
17111734
#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
@@ -2944,6 +2967,11 @@ extern "C" {
29442967

29452968
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
29462969
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
2970+
#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
2971+
#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
2972+
#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
2973+
#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
2974+
#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
29472975
#endif
29482976

29492977
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
@@ -3408,7 +3436,7 @@ extern "C" {
34083436
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
34093437
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
34103438

3411-
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
3439+
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
34123440
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
34133441
#else
34143442
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3521,8 +3549,8 @@ extern "C" {
35213549
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
35223550
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
35233551
#if defined(STM32U5)
3524-
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
3525-
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
3552+
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
3553+
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
35263554
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
35273555
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
35283556
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
@@ -3538,15 +3566,20 @@ extern "C" {
35383566
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
35393567
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
35403568
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
3541-
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
3542-
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
3543-
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
3544-
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
3545-
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3546-
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3547-
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
3548-
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
3549-
#endif
3569+
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
3570+
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
3571+
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
3572+
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
3573+
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3574+
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3575+
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
3576+
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
3577+
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
3578+
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
3579+
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
3580+
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
3581+
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
3582+
#endif /* STM32U5 */
35503583

35513584
/**
35523585
* @}
@@ -3564,7 +3597,8 @@ extern "C" {
35643597
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
35653598
* @{
35663599
*/
3567-
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
3600+
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || \
3601+
defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32C0)
35683602
#else
35693603
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
35703604
#endif
@@ -3628,7 +3662,7 @@ extern "C" {
36283662
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
36293663
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
36303664

3631-
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
3665+
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
36323666
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
36333667
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
36343668
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
@@ -3965,6 +3999,16 @@ extern "C" {
39653999
* @}
39664000
*/
39674001

4002+
/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
4003+
* @{
4004+
*/
4005+
#if defined (STM32F7)
4006+
#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
4007+
#endif /* STM32F7 */
4008+
/**
4009+
* @}
4010+
*/
4011+
39684012
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
39694013
* @{
39704014
*/

0 commit comments

Comments
 (0)