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variant: U5: add NUCLEO-U575ZI-Q
Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
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‎README.md

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@@ -92,6 +92,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :green_heart: | STM32L4R5ZI-P | [Nucleo L4R5ZI-P](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi-p.html) | *1.4.0* | |
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| :green_heart: | STM32L552ZE-Q | [Nucleo L552ZE-Q](https://www.st.com/en/evaluation-tools/nucleo-l552ze-q.html) | *2.0.0* | |
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| :green_heart: | STM32H743ZI | [Nucleo H743ZI(2)](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html) | *1.5.0* | Nucleo H743ZI2 since 1.6.0 |
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| :yellow_heart: | STM32U575ZI-Q | [NUCLEO-U575ZI-Q](https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html) | **2.1.0** | |
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### [Nucleo 64](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-nucleo-boards.html) boards
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‎boards.txt

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@@ -180,6 +180,19 @@ Nucleo_144.menu.pnum.NUCLEO_L552ZE_Q.build.product_line=STM32L552xx
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Nucleo_144.menu.pnum.NUCLEO_L552ZE_Q.build.variant=STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ
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Nucleo_144.menu.pnum.NUCLEO_L552ZE_Q.build.cmsis_lib_gcc=arm_ARMv8MMLlfsp_math
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# NUCLEO_U575ZI_Q board
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Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q=Nucleo U575ZI-Q
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Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.node=NOD_U575ZI
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Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.upload.maximum_size=2097152
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Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.upload.maximum_data_size=262144
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Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.build.mcu=cortex-m33
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Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
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Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.build.board=NUCLEO_U575ZI_Q
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Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.build.series=STM32U5xx
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Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.build.product_line=STM32U575xx
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Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.build.variant=STM32U5xx/U575Z(G-I)TxQ_U585ZETxQ
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Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.build.cmsis_lib_gcc=arm_ARMv8MMLlfsp_math
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# Upload menu
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Nucleo_144.menu.upload_method.MassStorage=Mass Storage
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Nucleo_144.menu.upload_method.MassStorage.upload.protocol=

‎variants/STM32U5xx/U575Z(G-I)TxQ_U585ZETxQ/variant_NUCLEO_U575ZI_Q.cpp

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/*
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*******************************************************************************
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* Copyright (c) 2021, STMicroelectronics
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#if defined(ARDUINO_NUCLEO_U575ZI_Q)
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#include "pins_arduino.h"
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// Digital PinName array
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const PinName digitalPin[] = {
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PG_8, // D0
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PG_7, // D1
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PF_15, // D2/A9
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PE_13, // D3
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PF_14, // D4/A10
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PE_11, // D5
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PE_9, // D6
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PF_13, // D7
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PF_12, // D8
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PD_15, // D9
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PD_14, // D10
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PA_7, // D11/A11
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PA_6, // D12/A12
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PA_5, // D13/A13
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PB_9, // D14
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PB_8, // D15
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PC_6, // D16
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PD_11, // D17/A14
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PB_13, // D18
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PD_12, // D19/A15
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PA_4, // D20/A16
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PB_4, // D21
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PB_5, // D22
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PB_3, // D23
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PA_4, // D24
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PB_4, // D25
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PA_2, // D26
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PB_10, // D27
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PE_15, // D28
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PB_0, // D29
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PE_12, // D30
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PE_14, // D31
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PA_0, // D32/A17
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PA_8, // D33
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PE_0, // D34
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PB_11, // D35
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PB_10, // D36
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PE_15, // D37
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PE_14, // D38
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PE_12, // D39
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PE_10, // D40
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PE_7, // D41
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PE_8, // D42
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PC_8, // D43
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PC_9, // D44
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PC_10, // D45
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PC_11, // D46
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PC_12, // D47
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PD_2, // D48
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PF_3, // D49
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PF_5, // D50
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PD_7, // D51
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PD_6, // D52
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PD_5, // D53
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PD_4, // D54
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PD_3, // D55
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PE_2, // D56
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PE_4, // D57
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PE_5, // D58
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PE_6, // D59
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PE_3, // D60
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PF_8, // D61
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PF_7, // D62
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PF_9, // D63
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PG_1, // D64/A18
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PG_0, // D65/A19
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PD_1, // D66
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PD_0, // D67
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PF_0, // D68
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PF_1, // D69
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PF_2, // D70
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PB_6, // D71
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PB_2, // D72/A20
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PA_3, // D73/A0
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PA_2, // D74/A1
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PC_3, // D75/A2
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PB_0, // D76/A3
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PC_1, // D77/A4
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PC_0, // D78/A5
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PB_1, // D79/A6
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PC_2, // D80/A7
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PA_1, // D81/A8
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PA_9, // D82
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PA_10, // D83
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PA_11, // D84
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PA_12, // D85
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PA_13, // D86
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PA_14, // D87
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PA_15, // D88
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PB_7, // D89
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PB_14, // D90
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PB_15, // D91
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PC_7, // D92
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PC_13, // D93
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PC_14, // D94
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PC_15, // D95
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PD_8, // D96
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PD_9, // D97
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PD_10, // D98
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PD_13, // D99/A21
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PE_1, // D100
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PF_4, // D101
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PF_6, // D102
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PF_10, // D103
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PF_11, // D104
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PG_2, // D105
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PG_3, // D106
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PG_4, // D107
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PG_5, // D108
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PG_6, // D109
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PG_9, // D110
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PG_10, // D111
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PG_12, // D112
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PG_13, // D113
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PG_14, // D114
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PG_15, // D115
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PH_0, // D116
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PH_1, // D117
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PH_3 // D118
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};
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// Analog (Ax) pin number array
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const uint32_t analogInputPin[] = {
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73, // A0, PA3
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74, // A1, PA2
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75, // A2, PC3
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76, // A3, PB0
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77, // A4, PC1
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78, // A5, PC0
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79, // A6, PB1
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80, // A7, PC2
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81, // A8, PA1
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2, // A9, PF15
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4, // A10, PF14
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11, // A11, PA7
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12, // A12, PA6
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13, // A13, PA5
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17, // A14, PD11
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19, // A15, PD12
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20, // A16, PA4
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32, // A17, PA0
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64, // A18, PG1
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65, // A19, PG0
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72, // A20, PB2
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99 // A21, PD13
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};
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// ----------------------------------------------------------------------------
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** System Clock Configuration
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*/
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WEAK void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
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/** Configure the main internal regulator output voltage
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*/
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if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
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Error_Handler();
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}
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/** Configure LSE Drive Capability
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*/
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HAL_PWR_EnableBkUpAccess();
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__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
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/** Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI
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| RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.MSIState = RCC_MSI_ON;
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RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_0;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
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RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV4;
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RCC_OscInitStruct.PLL.PLLM = 3;
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RCC_OscInitStruct.PLL.PLLN = 10;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLR = 1;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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Error_Handler();
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}
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/** Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
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| RCC_CLOCKTYPE_PCLK3;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
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Error_Handler();
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}
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC1
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| RCC_PERIPHCLK_CLK48;
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PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HSI;
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PeriphClkInit.Dac1ClockSelection = RCC_DAC1CLKSOURCE_LSE;
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PeriphClkInit.Clk48ClockSelection = RCC_CLK48CLKSOURCE_HSI48;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
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Error_Handler();
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}
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* ARDUINO_NUCLEO_U575ZI_Q */

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