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2 | 2 | ******************************************************************************
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3 | 3 | * @file stm32_hal_legacy.h
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4 | 4 | * @author MCD Application Team
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5 |
| - * @version V1.8.1 |
6 |
| - * @date 14-April-2017 |
7 | 5 | * @brief This file contains aliases definition for the STM32Cube HAL constants
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8 | 6 | * macros and functions maintained for legacy purpose.
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9 | 7 | ******************************************************************************
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138 | 136 | #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
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139 | 137 | #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
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140 | 138 | #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
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141 |
| -#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ |
| 139 | +#if defined(STM32L0) |
| 140 | +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ |
| 141 | +#endif |
142 | 142 | #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
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143 | 143 | #if defined(STM32F373xC) || defined(STM32F378xx)
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144 | 144 | #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
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265 | 265 | #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
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266 | 266 | #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
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267 | 267 | #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
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268 |
| -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 |
269 | 268 | #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
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270 | 269 | #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
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271 | 270 | #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
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457 | 456 | * @}
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458 | 457 | */
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459 | 458 |
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| 459 | +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose |
| 460 | + * @{ |
| 461 | + */ |
| 462 | + |
| 463 | +#if defined(STM32H7) |
| 464 | + #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE |
| 465 | + #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE |
| 466 | + #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET |
| 467 | + #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET |
| 468 | + #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE |
| 469 | + #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE |
| 470 | + |
| 471 | + #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 |
| 472 | + #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 |
| 473 | + |
| 474 | + #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX |
| 475 | + #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX |
| 476 | + |
| 477 | + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT |
| 478 | + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT |
| 479 | + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT |
| 480 | + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT |
| 481 | + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT |
| 482 | + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT |
| 483 | + #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 |
| 484 | + #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO |
| 485 | + |
| 486 | + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT |
| 487 | + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT |
| 488 | + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT |
| 489 | + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT |
| 490 | + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT |
| 491 | + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT |
| 492 | + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT |
| 493 | + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP |
| 494 | + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP |
| 495 | + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP |
| 496 | + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT |
| 497 | + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP |
| 498 | + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT |
| 499 | + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP |
| 500 | + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP |
| 501 | + #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP |
| 502 | + #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP |
| 503 | + #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT |
| 504 | + #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT |
| 505 | + #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP |
| 506 | + #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 |
| 507 | + #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 |
| 508 | + #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT |
| 509 | + #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT |
| 510 | + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT |
| 511 | + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT |
| 512 | + #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT |
| 513 | + #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT |
| 514 | + #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT |
| 515 | + #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT |
| 516 | + |
| 517 | + #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT |
| 518 | + #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING |
| 519 | + #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING |
| 520 | + #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING |
| 521 | + |
| 522 | + |
| 523 | +#endif /* STM32H7 */ |
| 524 | + |
| 525 | + |
| 526 | +/** |
| 527 | + * @} |
| 528 | + */ |
| 529 | + |
| 530 | + |
460 | 531 | /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
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461 | 532 | * @{
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462 | 533 | */
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670 | 741 | #define FORMAT_BCD RTC_FORMAT_BCD
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671 | 742 |
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672 | 743 | #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
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673 |
| -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE |
674 | 744 | #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
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675 | 745 | #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
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676 | 746 | #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
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677 | 747 |
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678 | 748 | #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
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679 | 749 | #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
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680 | 750 | #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
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681 |
| -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE |
682 |
| -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE |
683 |
| -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE |
684 | 751 | #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
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685 | 752 | #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
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686 | 753 |
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1312 | 1379 | #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
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1313 | 1380 | #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
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1314 | 1381 | #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
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1315 |
| -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION |
1316 | 1382 | #define __HAL_ADC_JSQR ADC_JSQR
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1317 | 1383 |
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1318 | 1384 | #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
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1785 | 1851 | #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
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1786 | 1852 | #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
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1787 | 1853 |
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1788 |
| -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE |
1789 |
| -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE |
1790 |
| -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE |
1791 |
| -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE |
1792 |
| -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET |
1793 |
| -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET |
1794 |
| -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE |
1795 |
| -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE |
1796 |
| -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET |
1797 |
| -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET |
1798 |
| -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE |
1799 |
| -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE |
1800 |
| -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE |
1801 |
| -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE |
| 1854 | +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE |
| 1855 | +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE |
| 1856 | +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE |
| 1857 | +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE |
| 1858 | +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET |
| 1859 | +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET |
| 1860 | +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE |
| 1861 | +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE |
| 1862 | +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET |
| 1863 | +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET |
| 1864 | +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE |
| 1865 | +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE |
| 1866 | +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE |
| 1867 | +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE |
1802 | 1868 | #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
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1803 | 1869 | #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
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1804 | 1870 | #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
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1815 | 1881 | #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
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1816 | 1882 | #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
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1817 | 1883 | #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
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1818 |
| -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET |
| 1884 | +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET |
1819 | 1885 | #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
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1820 | 1886 | #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
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1821 | 1887 | #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
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2410 | 2476 | #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
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2411 | 2477 | #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
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2412 | 2478 | #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
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2413 |
| -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET |
2414 | 2479 | #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
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2415 | 2480 | #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
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2416 | 2481 | #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
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2443 | 2508 | #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
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2444 | 2509 | #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
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2445 | 2510 | #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
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2446 |
| -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE |
2447 |
| -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE |
2448 | 2511 | #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
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2449 | 2512 | #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
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2450 | 2513 | #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
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|
2466 | 2529 | #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
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2467 | 2530 | #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
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2468 | 2531 | #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
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2469 |
| -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET |
2470 |
| -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET |
2471 | 2532 | #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
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2472 | 2533 | #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
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2473 | 2534 | #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
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2692 | 2753 | #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
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2693 | 2754 | #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
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2694 | 2755 |
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| 2756 | +#if defined(STM32WB) || defined(STM32G0) |
| 2757 | +#else |
2695 | 2758 | #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
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| 2759 | +#endif |
2696 | 2760 |
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2697 | 2761 | #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
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2698 | 2762 | #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
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2804 | 2868 | /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
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2805 | 2869 | * @{
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2806 | 2870 | */
|
2807 |
| - |
| 2871 | +#if defined (STM32G0) |
| 2872 | +#else |
2808 | 2873 | #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
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| 2874 | +#endif |
2809 | 2875 | #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
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2810 | 2876 | #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
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2811 | 2877 |
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