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Merge pull request #2014 from fpistm/CubeL1_v1.10.4
Update to latest STM32CubeL1 v1.10.4
2 parents bd6048b + 9ae0f65 commit 2b4d8ef

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‎libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c

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Original file line numberDiff line numberDiff line change
@@ -22,6 +22,8 @@
2222
#include "stm32h7xx_hal_smbus.c"
2323
#elif STM32L0xx
2424
#include "stm32l0xx_hal_smbus.c"
25+
#elif STM32L1xx
26+
#include "stm32l1xx_hal_smbus.c"
2527
#elif STM32L4xx
2628
#include "stm32l4xx_hal_smbus.c"
2729
#elif STM32L5xx

‎system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h

Lines changed: 27 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -9,18 +9,17 @@
99
* This file contains:
1010
* - Data structures and the address mapping for all peripherals
1111
* - Peripheral's registers declarations and bits definition
12-
* - Macros to access peripheral�s registers hardware
12+
* - Macros to access peripheral's registers hardware
1313
*
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2017-2021 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
@@ -863,7 +862,7 @@ typedef struct
863862
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
864863
#define ADC_CR2_ALIGN_Pos (11U)
865864
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
866-
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
865+
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
867866

868867
#define ADC_CR2_JEXTSEL_Pos (16U)
869868
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -2751,7 +2750,7 @@ typedef struct
27512750
/* */
27522751
/******************************************************************************/
27532752
/*
2754-
* @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
2753+
* @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
27552754
*/
27562755
#define FLASH_CUT1
27572756

@@ -3658,7 +3657,7 @@ typedef struct
36583657

36593658
#define LCD_FCR_PON_Pos (4U)
36603659
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
3661-
#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
3660+
#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
36623661
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
36633662
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
36643663
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -4465,7 +4464,7 @@ typedef struct
44654464
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
44664465
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
44674466

4468-
/*!< RTC congiguration */
4467+
/*!< RTC configuration */
44694468
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
44704469
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
44714470
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4515,7 +4514,7 @@ typedef struct
45154514
/* */
45164515
/******************************************************************************/
45174516
/*
4518-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
4517+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
45194518
*/
45204519
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
45214520
#define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
@@ -5006,7 +5005,7 @@ typedef struct
50065005
/******************************************************************************/
50075006

50085007
/*
5009-
* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
5008+
* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
50105009
*/
50115010

50125011
/******************* Bit definition for SPI_CR1 register ********************/
@@ -6078,12 +6077,21 @@ typedef struct
60786077
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
60796078

60806079
/****************** Bit definition for USART_BRR register *******************/
6081-
#define USART_BRR_DIV_FRACTION_Pos (0U)
6082-
#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
6083-
#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
6084-
#define USART_BRR_DIV_MANTISSA_Pos (4U)
6085-
#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
6086-
#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
6080+
#define USART_BRR_DIV_Fraction_Pos (0U)
6081+
#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
6082+
#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
6083+
#define USART_BRR_DIV_Mantissa_Pos (4U)
6084+
#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
6085+
#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
6086+
6087+
/* Legacy aliases */
6088+
#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
6089+
#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
6090+
#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
6091+
6092+
#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
6093+
#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
6094+
#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
60876095

60886096
/****************** Bit definition for USART_CR1 register *******************/
60896097
#define USART_CR1_SBK_Pos (0U)
@@ -7666,4 +7674,3 @@ typedef struct
76667674

76677675

76687676

7669-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h

Lines changed: 28 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -9,18 +9,17 @@
99
* This file contains:
1010
* - Data structures and the address mapping for all peripherals
1111
* - Peripheral's registers declarations and bits definition
12-
* - Macros to access peripheral�s registers hardware
12+
* - Macros to access peripheral's registers hardware
1313
*
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2017-2021 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
@@ -863,7 +862,7 @@ typedef struct
863862
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
864863
#define ADC_CR2_ALIGN_Pos (11U)
865864
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
866-
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
865+
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
867866

868867
#define ADC_CR2_JEXTSEL_Pos (16U)
869868
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
@@ -2754,7 +2753,7 @@ typedef struct
27542753
/* */
27552754
/******************************************************************************/
27562755
/*
2757-
* @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
2756+
* @brief Specific device feature definitions (not present on all devices in the STM32L1 series)
27582757
*/
27592758
#define FLASH_CUT2
27602759

@@ -3664,7 +3663,7 @@ typedef struct
36643663

36653664
#define LCD_FCR_PON_Pos (4U)
36663665
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
3667-
#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
3666+
#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
36683667
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
36693668
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
36703669
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
@@ -3833,7 +3832,7 @@ typedef struct
38333832
/* */
38343833
/******************************************************************************/
38353834
/*
3836-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
3835+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
38373836
*/
38383837
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
38393838

@@ -4492,7 +4491,7 @@ typedef struct
44924491
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
44934492
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
44944493

4495-
/*!< RTC congiguration */
4494+
/*!< RTC configuration */
44964495
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
44974496
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
44984497
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
@@ -4542,7 +4541,7 @@ typedef struct
45424541
/* */
45434542
/******************************************************************************/
45444543
/*
4545-
* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
4544+
* @brief Specific device feature definitions (not present on all devices in the STM32F0 series)
45464545
*/
45474546
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
45484547
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -5154,7 +5153,7 @@ typedef struct
51545153
/******************************************************************************/
51555154

51565155
/*
5157-
* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
5156+
* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
51585157
*/
51595158

51605159
/******************* Bit definition for SPI_CR1 register ********************/
@@ -6226,12 +6225,21 @@ typedef struct
62266225
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
62276226

62286227
/****************** Bit definition for USART_BRR register *******************/
6229-
#define USART_BRR_DIV_FRACTION_Pos (0U)
6230-
#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
6231-
#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
6232-
#define USART_BRR_DIV_MANTISSA_Pos (4U)
6233-
#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
6234-
#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
6228+
#define USART_BRR_DIV_Fraction_Pos (0U)
6229+
#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
6230+
#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
6231+
#define USART_BRR_DIV_Mantissa_Pos (4U)
6232+
#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
6233+
#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
6234+
6235+
/* Legacy aliases */
6236+
#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
6237+
#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
6238+
#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction
6239+
6240+
#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
6241+
#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
6242+
#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa
62356243

62366244
/****************** Bit definition for USART_CR1 register *******************/
62376245
#define USART_CR1_SBK_Pos (0U)
@@ -7814,4 +7822,3 @@ typedef struct
78147822

78157823

78167824

7817-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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