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[STM32MP157_DK] System clock and HAL configuration
1 parent 63fc867 commit 203bdc7

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3 files changed

+142
-8
lines changed

3 files changed

+142
-8
lines changed

‎system/STM32MP1xx/stm32mp1xx_hal_conf_default.h

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
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*
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*
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******************************************************************************
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*/
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32MP1xx_HAL_CONF_DEFAULT_H
@@ -37,6 +37,18 @@
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* @brief Include the default list of modules to be used in the HAL driver
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* and manage module deactivation
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*/
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#define HAL_RTC_MODULE_DISABLED /* RTC MODULE on Cortex-M side is not supported.
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Linux on Cortex-A will handle this. */
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#define HAL_ETH_MODULE_DISABLED /* ETH module is also not intended to be used */
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#define HAL_MDMA_MODULE_ENABLED /* Some other modules (e.g. USART) require this */
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#if defined(ARDUINO_STM32MP157A_DK1) || defined(ARDUINO_STM32MP157A_DK2)
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// Cannot use them in this board, or define them in the kernel device tree.
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#define HAL_QSPI_MODULE_DISABLED
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#define HAL_FDCAN_MODULE_DISABLED
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#endif // defined(ARDUINO_STM32MP157A_DK1) && defined(ARDUINO_STM32MP157A_DK2)
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#include "stm32yyxx_hal_conf.h"
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#if 0
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/**

‎system/STM32MP1xx/system_stm32mp1xx.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,10 @@
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#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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#if !defined (CSI_VALUE)
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#define CSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
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#endif /* CSI_VALUE */
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/**
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* @}
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*/

‎variants/STM32MP157_DK/variant.cpp

Lines changed: 125 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -128,14 +128,132 @@ extern "C" {
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* @param None
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* @retval None
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*/
131-
WEAK void SystemClock_Config(void)
131+
void SystemClock_Config(void)
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{
133-
// Here copy the desired System Clock Configuration
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// It could be generated thanks STM32CubeMX after code generation for Toolchain/IDE: 'SW4STM32',
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// available in src/main.c
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// or
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// copied from a STM32CubeYY project examples
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// where 'YY' could be F0, F1, F2, F3, F4, F7, G0, H7, L0, L1, L4, WB
133+
/**
134+
* NOTE: Because of the limitation of STM32MP1xx, unlike other MCUs this is
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* NOT a WEAK function, preventing being overriden.
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* In STM32MP1 series, SystemClock_Config()) is "done" by running the FSBL
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* (First Stage Boot Loader) on Cortex-A. This function call shall NOT be
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* executed in production mode. SystemClock_Config() shall be under
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* if(IS_ENGINEERING_BOOT_MODE()).
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*
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* NOTE:
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* * Production mode: Both CA7 and CM4 core running, BOOT0 and BOOT2 are ON.
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* * Engineering mode: Only CM4 running, BOOT0 = OFF, BOOT2 = ON.
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* See:
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* https://wiki.st.com/stm32mpu/wiki/STM32CubeMP1_development_guidelines
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*/
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if(!IS_ENGINEERING_BOOT_MODE()) {
148+
return;
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}
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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/**Configure LSE Drive Capability
155+
*/
156+
HAL_PWR_EnableBkUpAccess();
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__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
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/**Initializes the CPU, AHB and APB busses clocks
160+
*/
161+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
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| RCC_OSCILLATORTYPE_LSE;
163+
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = 16;
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RCC_OscInitStruct.HSIDivValue = RCC_HSI_DIV1;
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/**PLL1 Config
170+
*/
171+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLL12SOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 3;
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RCC_OscInitStruct.PLL.PLLN = 81;
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RCC_OscInitStruct.PLL.PLLP = 1;
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RCC_OscInitStruct.PLL.PLLQ = 1;
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RCC_OscInitStruct.PLL.PLLR = 1;
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RCC_OscInitStruct.PLL.PLLFRACV = 0x800;
179+
RCC_OscInitStruct.PLL.PLLMODE = RCC_PLL_FRACTIONAL;
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RCC_OscInitStruct.PLL.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
181+
RCC_OscInitStruct.PLL.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
182+
183+
/**PLL2 Config
184+
*/
185+
RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON;
186+
RCC_OscInitStruct.PLL2.PLLSource = RCC_PLL12SOURCE_HSE;
187+
RCC_OscInitStruct.PLL2.PLLM = 3;
188+
RCC_OscInitStruct.PLL2.PLLN = 66;
189+
RCC_OscInitStruct.PLL2.PLLP = 2;
190+
RCC_OscInitStruct.PLL2.PLLQ = 1;
191+
RCC_OscInitStruct.PLL2.PLLR = 1;
192+
RCC_OscInitStruct.PLL2.PLLFRACV = 0x1400;
193+
RCC_OscInitStruct.PLL2.PLLMODE = RCC_PLL_FRACTIONAL;
194+
RCC_OscInitStruct.PLL2.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
195+
RCC_OscInitStruct.PLL2.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
196+
197+
/**PLL3 Config
198+
*/
199+
RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON;
200+
RCC_OscInitStruct.PLL3.PLLSource = RCC_PLL3SOURCE_HSE;
201+
RCC_OscInitStruct.PLL3.PLLM = 2;
202+
RCC_OscInitStruct.PLL3.PLLN = 34;
203+
RCC_OscInitStruct.PLL3.PLLP = 2;
204+
RCC_OscInitStruct.PLL3.PLLQ = 17;
205+
RCC_OscInitStruct.PLL3.PLLR = 37;
206+
RCC_OscInitStruct.PLL3.PLLRGE = RCC_PLL3IFRANGE_1;
207+
RCC_OscInitStruct.PLL3.PLLFRACV = 0x1A04;
208+
RCC_OscInitStruct.PLL3.PLLMODE = RCC_PLL_FRACTIONAL;
209+
RCC_OscInitStruct.PLL3.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
210+
RCC_OscInitStruct.PLL3.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
211+
212+
/**PLL4 Config
213+
*/
214+
RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_ON;
215+
RCC_OscInitStruct.PLL4.PLLSource = RCC_PLL4SOURCE_HSE;
216+
RCC_OscInitStruct.PLL4.PLLM = 4;
217+
RCC_OscInitStruct.PLL4.PLLN = 99;
218+
RCC_OscInitStruct.PLL4.PLLP = 6;
219+
RCC_OscInitStruct.PLL4.PLLQ = 8;
220+
RCC_OscInitStruct.PLL4.PLLR = 8;
221+
RCC_OscInitStruct.PLL4.PLLRGE = RCC_PLL4IFRANGE_0;
222+
RCC_OscInitStruct.PLL4.PLLFRACV = 0;
223+
RCC_OscInitStruct.PLL4.PLLMODE = RCC_PLL_INTEGER;
224+
RCC_OscInitStruct.PLL4.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
225+
RCC_OscInitStruct.PLL4.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
226+
227+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
228+
/* Initialization Error */
229+
while (1);
230+
}
231+
/**RCC Clock Config
232+
*/
233+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_ACLK
234+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
235+
| RCC_CLOCKTYPE_PCLK3 | RCC_CLOCKTYPE_PCLK4
236+
| RCC_CLOCKTYPE_PCLK5 | RCC_CLOCKTYPE_MPU;
237+
RCC_ClkInitStruct.MPUInit.MPU_Clock = RCC_MPUSOURCE_PLL1;
238+
RCC_ClkInitStruct.MPUInit.MPU_Div = RCC_MPU_DIV2;
239+
RCC_ClkInitStruct.AXISSInit.AXI_Clock = RCC_AXISSOURCE_PLL2;
240+
RCC_ClkInitStruct.AXISSInit.AXI_Div = RCC_AXI_DIV1;
241+
RCC_ClkInitStruct.MCUInit.MCU_Clock = RCC_MCUSSOURCE_PLL3;
242+
RCC_ClkInitStruct.MCUInit.MCU_Div = RCC_MCU_DIV1;
243+
RCC_ClkInitStruct.APB4_Div = RCC_APB4_DIV2;
244+
RCC_ClkInitStruct.APB5_Div = RCC_APB5_DIV4;
245+
RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV2;
246+
RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV2;
247+
RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV2;
248+
249+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) {
250+
/* Initialization Error */
251+
while (1);
252+
}
253+
254+
/**Set the HSE division factor for RTC clock
255+
*/
256+
__HAL_RCC_RTC_HSEDIV(24);
139257
}
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#ifdef __cplusplus

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