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system(H5) update STM32H5xx HAL Drivers to v1.5.0
Included in STM32CubeH5 FW v1.5.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 2801e70 commit 17f3be3

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55 files changed

+6697
-455
lines changed

‎system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -538,6 +538,10 @@ extern "C" {
538538
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
539539
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
540540
#endif /* STM32H7 */
541+
#if defined(STM32H7RS)
542+
#define FLASH_OPTKEY1 FLASH_OPT_KEY1
543+
#define FLASH_OPTKEY2 FLASH_OPT_KEY2
544+
#endif /* STM32H7RS */
541545
#if defined(STM32U5)
542546
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
543547
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
@@ -1299,22 +1303,22 @@ extern "C" {
12991303
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
13001304
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
13011305

1302-
#if defined(STM32F7)
1306+
#if defined(STM32F7) || defined(STM32WB)
13031307
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
13041308
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
1305-
#endif /* STM32F7 */
1309+
#endif /* STM32F7 || STM32WB */
13061310

13071311
#if defined(STM32H7)
13081312
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
13091313
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
13101314
#endif /* STM32H7 */
13111315

1312-
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
1316+
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
13131317
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
13141318
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
13151319
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
13161320
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
1317-
#endif /* STM32F7 || STM32H7 || STM32L0 */
1321+
#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
13181322

13191323
/**
13201324
* @}
@@ -1481,7 +1485,7 @@ extern "C" {
14811485
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
14821486
#endif
14831487

1484-
#if defined(STM32U5)
1488+
#if defined(STM32U5) || defined(STM32MP2)
14851489
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
14861490
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
14871491
#endif
@@ -3695,7 +3699,8 @@ extern "C" {
36953699
#endif
36963700

36973701
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
3698-
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0)
3702+
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
3703+
defined(STM32U0)
36993704
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
37003705
#else
37013706
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3946,8 +3951,8 @@ extern "C" {
39463951
*/
39473952
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
39483953
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
3949-
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \
3950-
defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
3954+
defined (STM32WBA) || defined (STM32H5) || \
3955+
defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
39513956
#else
39523957
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
39533958
#endif

‎system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -490,6 +490,26 @@ extern HAL_TickFreqTypeDef uwTickFreq;
490490
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP)
491491
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP */
492492

493+
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP)
494+
#define __HAL_DBGMCU_FREEZE_GPDMA1_8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP)
495+
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP)
496+
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP */
497+
498+
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP)
499+
#define __HAL_DBGMCU_FREEZE_GPDMA1_9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP)
500+
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP)
501+
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP */
502+
503+
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP)
504+
#define __HAL_DBGMCU_FREEZE_GPDMA1_10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP)
505+
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP)
506+
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP */
507+
508+
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP)
509+
#define __HAL_DBGMCU_FREEZE_GPDMA1_11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP)
510+
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP)
511+
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP */
512+
493513
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP)
494514
#define __HAL_DBGMCU_FREEZE_GPDMA2_0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP)
495515
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP)
@@ -530,6 +550,25 @@ extern HAL_TickFreqTypeDef uwTickFreq;
530550
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP)
531551
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP */
532552

553+
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP)
554+
#define __HAL_DBGMCU_FREEZE_GPDMA2_8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP)
555+
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP)
556+
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP */
557+
558+
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP)
559+
#define __HAL_DBGMCU_FREEZE_GPDMA2_9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP)
560+
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP)
561+
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP */
562+
563+
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP)
564+
#define __HAL_DBGMCU_FREEZE_GPDMA2_10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP)
565+
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP)
566+
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP */
567+
568+
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP)
569+
#define __HAL_DBGMCU_FREEZE_GPDMA2_11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP)
570+
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP)
571+
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP */
533572
/**
534573
* @}
535574
*/

‎system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_conf_template.h

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
**********************************************************************************************************************
99
* @attention
1010
*
11-
* Copyright (c) 2023 STMicroelectronics.
11+
* Copyright (c) 2023-2025 STMicroelectronics.
1212
* All rights reserved.
1313
*
1414
* This software is licensed under terms that can be found in the LICENSE file
@@ -77,6 +77,7 @@ extern "C" {
7777
#define HAL_RTC_MODULE_ENABLED
7878
#define HAL_SAI_MODULE_ENABLED
7979
#define HAL_SD_MODULE_ENABLED
80+
#define HAL_SDIO_MODULE_ENABLED
8081
#define HAL_SDRAM_MODULE_ENABLED
8182
#define HAL_SMARTCARD_MODULE_ENABLED
8283
#define HAL_SMBUS_MODULE_ENABLED
@@ -186,6 +187,10 @@ in voltage and temperature.*/
186187
*/
187188
/* #define USE_FULL_ASSERT 1U */
188189

190+
/* ############################################ Max IO function number for SDIO device ############################## */
191+
#define SDIO_MAX_IO_NUMBER 7U /*!< SDIO device support maximum IO number */
192+
#define USE_SDIO_TRANSCEIVER 1U /*!< SDIO Transceiver */
193+
189194
/* ############################################ Register callback feature configuration ############################# */
190195
/**
191196
* @brief Set below the peripheral configuration to "1U" to add the support
@@ -227,6 +232,7 @@ in voltage and temperature.*/
227232
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
228233
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
229234
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
235+
#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */
230236
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
231237
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
232238
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
@@ -376,6 +382,10 @@ in voltage and temperature.*/
376382
#include "stm32h5xx_hal_sd.h"
377383
#endif /* HAL_SD_MODULE_ENABLED */
378384

385+
#ifdef HAL_SDIO_MODULE_ENABLED
386+
#include "stm32h5xx_hal_sdio.h"
387+
#endif /* HAL_SDIO_MODULE_ENABLED */
388+
379389
#ifdef HAL_SMBUS_MODULE_ENABLED
380390
#include "stm32h5xx_hal_smbus.h"
381391
#endif /* HAL_SMBUS_MODULE_ENABLED */

‎system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cryp.h

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -484,25 +484,25 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
484484
* @arg @ref CRYP_FLAG_KEIF Key error flag
485485
* @arg @ref CRYP_FLAG_RWEIF Read/write Error flag
486486
487-
* @retval The state of __FLAG__ (TRUE or FALSE).
487+
* @retval The state of __FLAG__ (FlagStatus).
488488
*/
489489

490490
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (\
491-
((__FLAG__) == CRYP_FLAG_KEYVALID )?(((__HANDLE__)->Instance->SR \
492-
& (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \
493-
((__FLAG__) == CRYP_FLAG_BUSY )?(((__HANDLE__)->Instance->SR \
494-
& (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \
495-
((__FLAG__) == CRYP_FLAG_WRERR )?(((__HANDLE__)->Instance->SR \
491+
((__FLAG__) == CRYP_FLAG_KEYVALID )?((((__HANDLE__)->Instance->SR \
492+
& (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID))?SET:RESET) : \
493+
((__FLAG__) == CRYP_FLAG_BUSY )?((((__HANDLE__)->Instance->SR \
494+
& (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY))?SET:RESET) : \
495+
((__FLAG__) == CRYP_FLAG_WRERR )?((((__HANDLE__)->Instance->SR \
496496
& (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) == \
497-
(CRYP_FLAG_WRERR & 0x7FFFFFFFU)) : \
498-
((__FLAG__) == CRYP_FLAG_RDERR )?(((__HANDLE__)->Instance->SR \
497+
(CRYP_FLAG_WRERR & 0x7FFFFFFFU))?SET:RESET) : \
498+
((__FLAG__) == CRYP_FLAG_RDERR )?((((__HANDLE__)->Instance->SR \
499499
& (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) == \
500-
(CRYP_FLAG_RDERR & 0x7FFFFFFFU)) : \
501-
((__FLAG__) == CRYP_FLAG_KEIF )?(((__HANDLE__)->Instance->ISR \
502-
& (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF)) : \
503-
((__FLAG__) == CRYP_FLAG_RWEIF )?(((__HANDLE__)->Instance->ISR \
504-
& (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF)) : \
505-
(((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF)))
500+
(CRYP_FLAG_RDERR & 0x7FFFFFFFU))?SET:RESET) : \
501+
((__FLAG__) == CRYP_FLAG_KEIF )?((((__HANDLE__)->Instance->ISR \
502+
& (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF))?SET:RESET) : \
503+
((__FLAG__) == CRYP_FLAG_RWEIF )?((((__HANDLE__)->Instance->ISR \
504+
& (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF))?SET:RESET) : \
505+
((((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF)))?SET:RESET)
506506

507507
/** @brief Clear the CRYP pending status flag.
508508
* @param __HANDLE__ specifies the CRYP handle.

‎system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_eth.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1798,6 +1798,7 @@ uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth);
17981798
uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth);
17991799
uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth);
18001800
uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth);
1801+
uint32_t HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth);
18011802
/**
18021803
* @}
18031804
*/

‎system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -198,7 +198,7 @@ typedef struct
198198
#if defined (FLASH_EDATAR_EDATA_EN)
199199
#define FLASH_TYPEPROGRAM_HALFWORD_EDATA (FLASH_CR_PG | FLASH_EDATA_HALFWORD) /*!< Program a flash
200200
high-cycle data half-word (16-bit)at a specified address */
201-
#define FLASH_TYPEPROGRAM_WORD_EDATA (FLASH_CR_PG | FLASH_EDATA_WORD) /*!< Program a flash
201+
#define FLASH_TYPEPROGRAM_WORD_EDATA (FLASH_CR_PG | FLASH_EDATA_WORD) /*!< Program a flash
202202
high-cycle data half-word (32-bit)at a specified address */
203203
#endif /* FLASH_EDATAR_EDATA_EN */
204204
#endif /* __ARM_FEATURE_CMSE */
@@ -650,6 +650,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
650650
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
651651
/* Option bytes control */
652652
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
653+
653654
/**
654655
* @}
655656
*/

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