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[F7] Update STM32F7xx CMSIS Drivers to v1.2.6
Included in STM32CubeF7 FW v1.16.1 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 50f1663 commit 0fc1f07

29 files changed

+679
-360
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f745xx.h

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -475,7 +475,8 @@ typedef struct
475475
__IO uint32_t PTPTTLR;
476476
__IO uint32_t RESERVED8;
477477
__IO uint32_t PTPTSSR;
478-
uint32_t RESERVED9[565];
478+
__IO uint32_t PTPPPSCR;
479+
uint32_t RESERVED9[564];
479480
__IO uint32_t DMABMR;
480481
__IO uint32_t DMATPDR;
481482
__IO uint32_t DMARPDR;
@@ -12899,6 +12900,30 @@ typedef struct
1289912900
#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */
1290012901

1290112902
/****************** Bit definition for SYSCFG_PMC register ******************/
12903+
#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
12904+
#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
12905+
#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
12906+
#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
12907+
#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
12908+
#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
12909+
#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
12910+
#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
12911+
#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
12912+
#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
12913+
#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
12914+
#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
12915+
#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
12916+
#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
12917+
#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
12918+
#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
12919+
#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
12920+
#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
12921+
#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
12922+
#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
12923+
#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
12924+
#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
12925+
#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
12926+
#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */
1290212927

1290312928
#define SYSCFG_PMC_ADCxDC2_Pos (16U)
1290412929
#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
@@ -15221,6 +15246,11 @@ typedef struct
1522115246
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
1522215247
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
1522315248

15249+
/* Bit definition for Ethernet PTP PPS Control Register */
15250+
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
15251+
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
15252+
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
15253+
1522415254
/******************************************************************************/
1522515255
/* Ethernet DMA Registers bits definition */
1522615256
/******************************************************************************/

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -477,7 +477,8 @@ typedef struct
477477
__IO uint32_t PTPTTLR;
478478
__IO uint32_t RESERVED8;
479479
__IO uint32_t PTPTSSR;
480-
uint32_t RESERVED9[565];
480+
__IO uint32_t PTPPPSCR;
481+
uint32_t RESERVED9[564];
481482
__IO uint32_t DMABMR;
482483
__IO uint32_t DMATPDR;
483484
__IO uint32_t DMARPDR;
@@ -13247,6 +13248,30 @@ typedef struct
1324713248
#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */
1324813249

1324913250
/****************** Bit definition for SYSCFG_PMC register ******************/
13251+
#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
13252+
#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
13253+
#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
13254+
#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
13255+
#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
13256+
#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
13257+
#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
13258+
#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
13259+
#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
13260+
#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
13261+
#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
13262+
#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
13263+
#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
13264+
#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
13265+
#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
13266+
#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
13267+
#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
13268+
#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
13269+
#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
13270+
#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
13271+
#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
13272+
#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
13273+
#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
13274+
#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */
1325013275

1325113276
#define SYSCFG_PMC_ADCxDC2_Pos (16U)
1325213277
#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
@@ -15569,6 +15594,11 @@ typedef struct
1556915594
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
1557015595
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
1557115596

15597+
/* Bit definition for Ethernet PTP PPS Control Register */
15598+
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
15599+
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
15600+
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
15601+
1557215602
/******************************************************************************/
1557315603
/* Ethernet DMA Registers bits definition */
1557415604
/******************************************************************************/

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f750xx.h

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -478,7 +478,8 @@ typedef struct
478478
__IO uint32_t PTPTTLR;
479479
__IO uint32_t RESERVED8;
480480
__IO uint32_t PTPTSSR;
481-
uint32_t RESERVED9[565];
481+
__IO uint32_t PTPPPSCR;
482+
uint32_t RESERVED9[564];
482483
__IO uint32_t DMABMR;
483484
__IO uint32_t DMATPDR;
484485
__IO uint32_t DMARPDR;
@@ -13540,6 +13541,30 @@ typedef struct
1354013541
#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */
1354113542

1354213543
/****************** Bit definition for SYSCFG_PMC register ******************/
13544+
#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
13545+
#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
13546+
#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
13547+
#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
13548+
#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
13549+
#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
13550+
#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
13551+
#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
13552+
#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
13553+
#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
13554+
#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
13555+
#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
13556+
#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
13557+
#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
13558+
#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
13559+
#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
13560+
#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
13561+
#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
13562+
#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
13563+
#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
13564+
#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
13565+
#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
13566+
#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
13567+
#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */
1354313568

1354413569
#define SYSCFG_PMC_ADCxDC2_Pos (16U)
1354513570
#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
@@ -15862,6 +15887,11 @@ typedef struct
1586215887
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
1586315888
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
1586415889

15890+
/* Bit definition for Ethernet PTP PPS Control Register */
15891+
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
15892+
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
15893+
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
15894+
1586515895
/******************************************************************************/
1586615896
/* Ethernet DMA Registers bits definition */
1586715897
/******************************************************************************/

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -478,7 +478,8 @@ typedef struct
478478
__IO uint32_t PTPTTLR;
479479
__IO uint32_t RESERVED8;
480480
__IO uint32_t PTPTSSR;
481-
uint32_t RESERVED9[565];
481+
__IO uint32_t PTPPPSCR;
482+
uint32_t RESERVED9[564];
482483
__IO uint32_t DMABMR;
483484
__IO uint32_t DMATPDR;
484485
__IO uint32_t DMARPDR;
@@ -13540,6 +13541,30 @@ typedef struct
1354013541
#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */
1354113542

1354213543
/****************** Bit definition for SYSCFG_PMC register ******************/
13544+
#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
13545+
#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
13546+
#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
13547+
#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
13548+
#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
13549+
#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
13550+
#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
13551+
#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
13552+
#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
13553+
#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
13554+
#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
13555+
#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
13556+
#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
13557+
#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
13558+
#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
13559+
#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
13560+
#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
13561+
#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
13562+
#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
13563+
#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
13564+
#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
13565+
#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
13566+
#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
13567+
#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */
1354313568

1354413569
#define SYSCFG_PMC_ADCxDC2_Pos (16U)
1354513570
#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
@@ -15862,6 +15887,11 @@ typedef struct
1586215887
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
1586315888
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
1586415889

15890+
/* Bit definition for Ethernet PTP PPS Control Register */
15891+
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
15892+
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
15893+
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
15894+
1586515895
/******************************************************************************/
1586615896
/* Ethernet DMA Registers bits definition */
1586715897
/******************************************************************************/

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f765xx.h

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -519,7 +519,8 @@ typedef struct
519519
__IO uint32_t PTPTTLR;
520520
__IO uint32_t RESERVED8;
521521
__IO uint32_t PTPTSSR;
522-
uint32_t RESERVED9[565];
522+
__IO uint32_t PTPPPSCR;
523+
uint32_t RESERVED9[564];
523524
__IO uint32_t DMABMR;
524525
__IO uint32_t DMATPDR;
525526
__IO uint32_t DMARPDR;
@@ -15879,6 +15880,11 @@ typedef struct
1587915880
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
1588015881
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
1588115882

15883+
/* Bit definition for Ethernet PTP PPS Control Register */
15884+
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
15885+
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
15886+
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
15887+
1588215888
/******************************************************************************/
1588315889
/* Ethernet DMA Registers bits definition */
1588415890
/******************************************************************************/

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -522,7 +522,8 @@ typedef struct
522522
__IO uint32_t PTPTTLR;
523523
__IO uint32_t RESERVED8;
524524
__IO uint32_t PTPTSSR;
525-
uint32_t RESERVED9[565];
525+
__IO uint32_t PTPPPSCR;
526+
uint32_t RESERVED9[564];
526527
__IO uint32_t DMABMR;
527528
__IO uint32_t DMATPDR;
528529
__IO uint32_t DMARPDR;
@@ -16273,6 +16274,11 @@ typedef struct
1627316274
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
1627416275
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
1627516276

16277+
/* Bit definition for Ethernet PTP PPS Control Register */
16278+
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
16279+
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
16280+
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
16281+
1627616282
/******************************************************************************/
1627716283
/* Ethernet DMA Registers bits definition */
1627816284
/******************************************************************************/

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f769xx.h

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -523,7 +523,8 @@ typedef struct
523523
__IO uint32_t PTPTTLR;
524524
__IO uint32_t RESERVED8;
525525
__IO uint32_t PTPTSSR;
526-
uint32_t RESERVED9[565];
526+
__IO uint32_t PTPPPSCR;
527+
uint32_t RESERVED9[564];
527528
__IO uint32_t DMABMR;
528529
__IO uint32_t DMATPDR;
529530
__IO uint32_t DMARPDR;
@@ -16368,6 +16369,11 @@ typedef struct
1636816369
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
1636916370
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
1637016371

16372+
/* Bit definition for Ethernet PTP PPS Control Register */
16373+
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
16374+
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
16375+
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
16376+
1637116377
/******************************************************************************/
1637216378
/* Ethernet DMA Registers bits definition */
1637316379
/******************************************************************************/

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f777xx.h

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -523,7 +523,8 @@ typedef struct
523523
__IO uint32_t PTPTTLR;
524524
__IO uint32_t RESERVED8;
525525
__IO uint32_t PTPTSSR;
526-
uint32_t RESERVED9[565];
526+
__IO uint32_t PTPPPSCR;
527+
uint32_t RESERVED9[564];
527528
__IO uint32_t DMABMR;
528529
__IO uint32_t DMATPDR;
529530
__IO uint32_t DMARPDR;
@@ -16566,6 +16567,11 @@ typedef struct
1656616567
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
1656716568
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
1656816569

16570+
/* Bit definition for Ethernet PTP PPS Control Register */
16571+
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
16572+
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
16573+
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
16574+
1656916575
/******************************************************************************/
1657016576
/* Ethernet DMA Registers bits definition */
1657116577
/******************************************************************************/

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f779xx.h

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -524,7 +524,8 @@ typedef struct
524524
__IO uint32_t PTPTTLR;
525525
__IO uint32_t RESERVED8;
526526
__IO uint32_t PTPTSSR;
527-
uint32_t RESERVED9[565];
527+
__IO uint32_t PTPPPSCR;
528+
uint32_t RESERVED9[564];
528529
__IO uint32_t DMABMR;
529530
__IO uint32_t DMATPDR;
530531
__IO uint32_t DMARPDR;
@@ -16661,6 +16662,11 @@ typedef struct
1666116662
#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
1666216663
#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
1666316664

16665+
/* Bit definition for Ethernet PTP PPS Control Register */
16666+
#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
16667+
#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */
16668+
#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
16669+
1666416670
/******************************************************************************/
1666516671
/* Ethernet DMA Registers bits definition */
1666616672
/******************************************************************************/

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