@@ -220,7 +220,7 @@ void SystemInit (void)
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#endif
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#if defined (DATA_IN_D2_SRAM )
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- /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
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+ /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
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#if defined(RCC_AHB2ENR_D2SRAM3EN )
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RCC -> AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN );
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#elif defined(RCC_AHB2ENR_D2SRAM2EN )
@@ -333,27 +333,26 @@ void SystemCoreClockUpdate (void)
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if (pllm != 0U )
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{
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- switch (pllsource )
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- {
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+ switch (pllsource )
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+ {
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case RCC_PLLCKSELR_PLLSRC_HSI : /* HSI used as PLL clock source */
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-
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- hsivalue = (HSI_VALUE >> ((RCC -> CR & RCC_CR_HSIDIV )>> 3 )) ;
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- pllvco = ( (float_t )hsivalue / (float_t )pllm ) * ((float_t )(uint32_t )(RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + (fracn1 /(float_t )0x2000 ) + (float_t )1 );
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-
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- break ;
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+ hsivalue = (HSI_VALUE >> ((RCC -> CR & RCC_CR_HSIDIV )>> 3 )) ;
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+ pllvco = ( (float_t )hsivalue / (float_t )pllm ) * ((float_t )(uint32_t )(RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + (fracn1 /(float_t )0x2000 ) + (float_t )1 );
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+ break ;
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case RCC_PLLCKSELR_PLLSRC_CSI : /* CSI used as PLL clock source */
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pllvco = ((float_t )CSI_VALUE / (float_t )pllm ) * ((float_t )(uint32_t )(RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + (fracn1 /(float_t )0x2000 ) + (float_t )1 );
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- break ;
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+ break ;
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case RCC_PLLCKSELR_PLLSRC_HSE : /* HSE used as PLL clock source */
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pllvco = ((float_t )HSE_VALUE / (float_t )pllm ) * ((float_t )(uint32_t )(RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + (fracn1 /(float_t )0x2000 ) + (float_t )1 );
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- break ;
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+ break ;
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- default :
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- pllvco = ((float_t )CSI_VALUE / (float_t )pllm ) * ((float_t )(uint32_t )(RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + (fracn1 /(float_t )0x2000 ) + (float_t )1 );
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- break ;
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- }
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+ default :
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+ hsivalue = (HSI_VALUE >> ((RCC -> CR & RCC_CR_HSIDIV )>> 3 )) ;
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+ pllvco = ((float_t )hsivalue / (float_t )pllm ) * ((float_t )(uint32_t )(RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + (fracn1 /(float_t )0x2000 ) + (float_t )1 );
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+ break ;
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+ }
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pllp = (((RCC -> PLL1DIVR & RCC_PLL1DIVR_P1 ) >>9 ) + 1U ) ;
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common_system_clock = (uint32_t )(float_t )(pllvco /(float_t )pllp );
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}
@@ -364,7 +363,7 @@ void SystemCoreClockUpdate (void)
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break ;
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default :
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- common_system_clock = CSI_VALUE ;
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+ common_system_clock = ( uint32_t ) ( HSI_VALUE >> (( RCC -> CR & RCC_CR_HSIDIV )>> 3 )) ;
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break ;
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}
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