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system: WB: update STM32WBxx HAL Drivers to v1.9.0
Included in STM32CubeWB FW v1.12.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 5e72ff9 commit 096d8c6

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+3886
-2516
lines changed

‎system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

Lines changed: 110 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -7,13 +7,12 @@
77
******************************************************************************
88
* @attention
99
*
10-
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
11-
* All rights reserved.</center></h2>
10+
* Copyright (c) 2019-2021 STMicroelectronics.
11+
* All rights reserved.
1212
*
13-
* This software component is licensed by ST under BSD 3-Clause license,
14-
* the "License"; You may not use this file except in compliance with the
15-
* License. You may obtain a copy of the License at:
16-
* opensource.org/licenses/BSD-3-Clause
13+
* This software is licensed under terms that can be found in the LICENSE file
14+
* in the root directory of this software component.
15+
* If no LICENSE file comes with this software, it is provided AS-IS.
1716
*
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******************************************************************************
1918
*/
@@ -38,6 +37,14 @@ extern "C" {
3837
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
3938
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
4039
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
40+
#if defined(STM32U5)
41+
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
42+
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
43+
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
44+
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
45+
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
46+
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
47+
#endif /* STM32U5 */
4148
/**
4249
* @}
4350
*/
@@ -210,6 +217,18 @@ extern "C" {
210217
* @}
211218
*/
212219

220+
/** @defgroup CRC_Aliases CRC API aliases
221+
* @{
222+
*/
223+
#if defined(STM32WL) || defined(STM32WB) || defined(STM32L5) || defined(STM32L4)
224+
#else
225+
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
226+
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
227+
#endif
228+
/**
229+
* @}
230+
*/
231+
213232
/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
214233
* @{
215234
*/
@@ -235,7 +254,7 @@ extern "C" {
235254
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
236255
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
237256

238-
#if defined(STM32G4) || defined(STM32H7)
257+
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
239258
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
240259
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
241260
#endif
@@ -469,15 +488,24 @@ extern "C" {
469488
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
470489
#endif
471490
#if defined(STM32H7)
472-
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
473-
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
474-
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
475-
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
476-
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
477-
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
478-
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
479-
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
491+
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
492+
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
493+
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
494+
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
495+
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
496+
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
497+
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
498+
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
480499
#endif /* STM32H7 */
500+
#if defined(STM32U5)
501+
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
502+
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
503+
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
504+
#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
505+
#define OB_USER_nBOOT0 OB_USER_NBOOT0
506+
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
507+
#define OB_nBOOT0_SET OB_NBOOT0_SET
508+
#endif /* STM32U5 */
481509

482510
/**
483511
* @}
@@ -520,6 +548,7 @@ extern "C" {
520548
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
521549
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
522550
#endif /* STM32G4 */
551+
523552
/**
524553
* @}
525554
*/
@@ -594,12 +623,12 @@ extern "C" {
594623
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
595624
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
596625

597-
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
626+
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
598627
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
599628
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
600629
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
601630
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
602-
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
631+
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
603632

604633
#if defined(STM32L1)
605634
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@@ -851,6 +880,11 @@ extern "C" {
851880
#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
852881
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
853882
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
883+
884+
#if defined(STM32U5)
885+
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
886+
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
887+
#endif /* STM32U5 */
854888
/**
855889
* @}
856890
*/
@@ -1377,6 +1411,20 @@ extern "C" {
13771411
*/
13781412
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
13791413

1414+
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
1415+
|| defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
1416+
|| defined(STM32H7) || defined(STM32U5)
1417+
/** @defgroup DMA2D_Aliases DMA2D API Aliases
1418+
* @{
1419+
*/
1420+
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
1421+
for compatibility with legacy code */
1422+
/**
1423+
* @}
1424+
*/
1425+
1426+
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
1427+
13801428
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
13811429
* @{
13821430
*/
@@ -1395,6 +1443,28 @@ extern "C" {
13951443
* @}
13961444
*/
13971445

1446+
/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
1447+
* @{
1448+
*/
1449+
1450+
#if defined(STM32U5)
1451+
#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_AsyncCleanInvalidateByAddr
1452+
#endif /* STM32U5 */
1453+
1454+
/**
1455+
* @}
1456+
*/
1457+
1458+
#if !defined(STM32F2)
1459+
/** @defgroup HASH_alias HASH API alias
1460+
* @{
1461+
*/
1462+
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
1463+
/**
1464+
*
1465+
* @}
1466+
*/
1467+
#endif /* STM32F2 */
13981468
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
13991469
* @{
14001470
*/
@@ -3327,7 +3397,20 @@ extern "C" {
33273397
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
33283398
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
33293399
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
3330-
3400+
#if defined(STM32U5)
3401+
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
3402+
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
3403+
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
3404+
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
3405+
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
3406+
#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
3407+
#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
3408+
#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
3409+
#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
3410+
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
3411+
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
3412+
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
3413+
#endif
33313414
/**
33323415
* @}
33333416
*/
@@ -3344,7 +3427,7 @@ extern "C" {
33443427
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
33453428
* @{
33463429
*/
3347-
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
3430+
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
33483431
#else
33493432
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
33503433
#endif
@@ -3401,13 +3484,20 @@ extern "C" {
34013484
* @}
34023485
*/
34033486

3404-
/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
3487+
/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
34053488
* @{
34063489
*/
34073490

34083491
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
34093492
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
34103493

3494+
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
3495+
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
3496+
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
3497+
3498+
#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
3499+
#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
3500+
34113501
#if defined(STM32F4) || defined(STM32F2)
34123502
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
34133503
#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
@@ -3750,5 +3840,4 @@ extern "C" {
37503840

37513841
#endif /* STM32_HAL_LEGACY */
37523842

3753-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
37543843

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