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‎cores/arduino/ard_sup/analog/ap3_analog.cpp

Lines changed: 134 additions & 124 deletions
Original file line numberDiff line numberDiff line change
@@ -27,9 +27,9 @@ SOFTWARE.
2727

2828
#include "ap3_analog.h"
2929

30-
// Define the clock source and frequency to use for
31-
// PWM generation.
32-
// Chose 12 MHz to allow maximal resolution with a
30+
// Define the clock source and frequency to use for
31+
// PWM generation.
32+
// Chose 12 MHz to allow maximal resolution with a
3333
// target maximum width of 2ms (for RC servos)
3434
// 1/12MHz = 0.083 uS per LSB.
3535
// 2ms/0.083us = 24000 LSB for 2 ms wide pulse
@@ -41,14 +41,14 @@ SOFTWARE.
4141
instead or maybe we can even go ahead and support the Servo library
4242
*/
4343

44-
#define AP3_ANALOG_CLK
45-
#define AP3_ANALOG_FREQ 12000000
46-
#define AP3_ANALOG_FRAME_PERIOD 24000
44+
#define AP3_ANALOG_CLK
45+
#define AP3_ANALOG_FREQ 12000000
46+
#define AP3_ANALOG_FRAME_PERIOD 24000
4747

4848
//*****************************************************************************
4949
//
5050
// Tables copied from am_hal_ctimer.c because they are declared as static within
51-
// that file, but they would be useful here too.
51+
// that file, but they would be useful here too.
5252
//
5353
// Lookup tables used by am_hal_ctimer_output_config().
5454
//
@@ -65,63 +65,63 @@ SOFTWARE.
6565
// OUTCFG 7 = A7OUT2.
6666
//
6767
//*****************************************************************************
68-
#define CTXPADNUM(ctx) ((CTx_tbl[ctx] >> 0) & 0x3f)
69-
#define CTXPADFNC(ctx) ((CTx_tbl[ctx] >> 8) & 0x7)
70-
#define CTX(pad, fn) ((fn << 8) | (pad << 0))
68+
#define CTXPADNUM(ctx) ((CTx_tbl[ctx] >> 0) & 0x3f)
69+
#define CTXPADFNC(ctx) ((CTx_tbl[ctx] >> 8) & 0x7)
70+
#define CTX(pad, fn) ((fn << 8) | (pad << 0))
7171
static const uint16_t CTx_tbl[32] =
72-
{
73-
CTX(12,2), CTX(25,2), CTX(13,2), CTX(26,2), CTX(18,2), // 0 - 4
74-
CTX(27,2), CTX(19,2), CTX(28,2), CTX( 5,7), CTX(29,2), // 5 - 9
75-
CTX( 6,5), CTX(30,2), CTX(22,2), CTX(31,2), CTX(23,2), // 10 - 14
76-
CTX(32,2), CTX(42,2), CTX( 4,6), CTX(43,2), CTX( 7,7), // 15 - 19
77-
CTX(44,2), CTX(24,5), CTX(45,2), CTX(33,6), CTX(46,2), // 20 - 24
78-
CTX(39,2), CTX(47,2), CTX(35,5), CTX(48,2), CTX(37,7), // 25 - 29
79-
CTX(49,2), CTX(11,2) // 30 - 31
72+
{
73+
CTX(12, 2), CTX(25, 2), CTX(13, 2), CTX(26, 2), CTX(18, 2), // 0 - 4
74+
CTX(27, 2), CTX(19, 2), CTX(28, 2), CTX(5, 7), CTX(29, 2), // 5 - 9
75+
CTX(6, 5), CTX(30, 2), CTX(22, 2), CTX(31, 2), CTX(23, 2), // 10 - 14
76+
CTX(32, 2), CTX(42, 2), CTX(4, 6), CTX(43, 2), CTX(7, 7), // 15 - 19
77+
CTX(44, 2), CTX(24, 5), CTX(45, 2), CTX(33, 6), CTX(46, 2), // 20 - 24
78+
CTX(39, 2), CTX(47, 2), CTX(35, 5), CTX(48, 2), CTX(37, 7), // 25 - 29
79+
CTX(49, 2), CTX(11, 2) // 30 - 31
8080
};
8181

82-
#define OUTC(timB,timN,N2) ((N2 << 4) | (timB << 3) | (timN << 0))
83-
#define OUTCTIMN(ctx,n) (outcfg_tbl[ctx][n] & (0x7 << 0))
84-
#define OUTCTIMB(ctx,n) (outcfg_tbl[ctx][n] & (0x1 << 3))
85-
#define OUTCO2(ctx,n) (outcfg_tbl[ctx][n] & (0x1 << 4))
82+
#define OUTC(timB, timN, N2) ((N2 << 4) | (timB << 3) | (timN << 0))
83+
#define OUTCTIMN(ctx, n) (outcfg_tbl[ctx][n] & (0x7 << 0))
84+
#define OUTCTIMB(ctx, n) (outcfg_tbl[ctx][n] & (0x1 << 3))
85+
#define OUTCO2(ctx, n) (outcfg_tbl[ctx][n] & (0x1 << 4))
8686
static const uint8_t outcfg_tbl[32][4] =
87-
{
88-
{OUTC(0,0,0), OUTC(1,2,1), OUTC(0,5,1), OUTC(0,6,0)}, // CTX0: A0OUT, B2OUT2, A5OUT2, A6OUT
89-
{OUTC(0,0,1), OUTC(0,0,0), OUTC(0,5,0), OUTC(1,7,1)}, // CTX1: A0OUT2, A0OUT, A5OUT, B7OUT2
90-
{OUTC(1,0,0), OUTC(1,1,1), OUTC(1,6,1), OUTC(0,7,0)}, // CTX2: B0OUT, B1OUT2, B6OUT2, A7OUT
91-
{OUTC(1,0,1), OUTC(1,0,0), OUTC(0,1,0), OUTC(0,6,0)}, // CTX3: B0OUT2, B0OUT, A1OUT, A6OUT
92-
{OUTC(0,1,0), OUTC(0,2,1), OUTC(0,5,1), OUTC(1,5,0)}, // CTX4: A1OUT, A2OUT2, A5OUT2, B5OUT
93-
{OUTC(0,1,1), OUTC(0,1,0), OUTC(1,6,0), OUTC(0,7,0)}, // CTX5: A1OUT2, A1OUT, B6OUT, A7OUT
94-
{OUTC(1,1,0), OUTC(0,1,0), OUTC(1,5,1), OUTC(1,7,0)}, // CTX6: B1OUT, A1OUT, B5OUT2, B7OUT
95-
{OUTC(1,1,1), OUTC(1,1,0), OUTC(1,5,0), OUTC(0,7,0)}, // CTX7: B1OUT2, B1OUT, B5OUT, A7OUT
96-
{OUTC(0,2,0), OUTC(0,3,1), OUTC(0,4,1), OUTC(1,6,0)}, // CTX8: A2OUT, A3OUT2, A4OUT2, B6OUT
97-
{OUTC(0,2,1), OUTC(0,2,0), OUTC(0,4,0), OUTC(1,0,0)}, // CTX9: A2OUT2, A2OUT, A4OUT, B0OUT
98-
{OUTC(1,2,0), OUTC(1,3,1), OUTC(1,4,1), OUTC(0,6,0)}, // CTX10: B2OUT, B3OUT2, B4OUT2, A6OUT
99-
{OUTC(1,2,1), OUTC(1,2,0), OUTC(1,4,0), OUTC(1,5,1)}, // CTX11: B2OUT2, B2OUT, B4OUT, B5OUT2
100-
{OUTC(0,3,0), OUTC(1,1,0), OUTC(1,0,1), OUTC(1,6,1)}, // CTX12: A3OUT, B1OUT, B0OUT2, B6OUT2
101-
{OUTC(0,3,1), OUTC(0,3,0), OUTC(0,6,0), OUTC(1,4,1)}, // CTX13: A3OUT2, A3OUT, A6OUT, B4OUT2
102-
{OUTC(1,3,0), OUTC(1,1,0), OUTC(1,7,1), OUTC(0,7,0)}, // CTX14: B3OUT, B1OUT, B7OUT2, A7OUT
103-
{OUTC(1,3,1), OUTC(1,3,0), OUTC(0,7,0), OUTC(0,4,1)}, // CTX15: B3OUT2, B3OUT, A7OUT, A4OUT2
104-
{OUTC(0,4,0), OUTC(0,0,0), OUTC(0,0,1), OUTC(1,3,1)}, // CTX16: A4OUT, A0OUT, A0OUT2, B3OUT2
105-
{OUTC(0,4,1), OUTC(1,7,0), OUTC(0,4,0), OUTC(0,1,1)}, // CTX17: A4OUT2, B7OUT, A4OUT, A1OUT2
106-
{OUTC(1,4,0), OUTC(1,0,0), OUTC(0,0,0), OUTC(0,3,1)}, // CTX18: B4OUT, B0OUT, A0OUT, A3OUT2
107-
{OUTC(1,4,1), OUTC(0,2,0), OUTC(1,4,0), OUTC(1,1,1)}, // CTX19: B4OUT2, A2OUT, B4OUT, B1OUT2
108-
{OUTC(0,5,0), OUTC(0,1,0), OUTC(0,1,1), OUTC(1,2,1)}, // CTX20: A5OUT, A1OUT, A1OUT2, B2OUT2
109-
{OUTC(0,5,1), OUTC(0,1,0), OUTC(1,5,0), OUTC(0,0,1)}, // CTX21: A5OUT2, A1OUT, B5OUT, A0OUT2
110-
{OUTC(1,5,0), OUTC(0,6,0), OUTC(0,1,0), OUTC(0,2,1)}, // CTX22: B5OUT, A6OUT, A1OUT, A2OUT2
111-
{OUTC(1,5,1), OUTC(0,7,0), OUTC(0,5,0), OUTC(1,0,1)}, // CTX23: B5OUT2, A7OUT, A5OUT, B0OUT2
112-
{OUTC(0,6,0), OUTC(0,2,0), OUTC(0,1,0), OUTC(1,1,1)}, // CTX24: A6OUT, A2OUT, A1OUT, B1OUT2
113-
{OUTC(1,4,1), OUTC(1,2,0), OUTC(0,6,0), OUTC(0,2,1)}, // CTX25: B4OUT2, B2OUT, A6OUT, A2OUT2
114-
{OUTC(1,6,0), OUTC(1,2,0), OUTC(0,5,0), OUTC(0,1,1)}, // CTX26: B6OUT, B2OUT, A5OUT, A1OUT2
115-
{OUTC(1,6,1), OUTC(0,1,0), OUTC(1,6,0), OUTC(1,2,1)}, // CTX27: B6OUT2, A1OUT, B6OUT, B2OUT2
116-
{OUTC(0,7,0), OUTC(0,3,0), OUTC(0,5,1), OUTC(1,0,1)}, // CTX28: A7OUT, A3OUT, A5OUT2, B0OUT2
117-
{OUTC(1,5,1), OUTC(0,1,0), OUTC(0,7,0), OUTC(0,3,1)}, // CTX29: B5OUT2, A1OUT, A7OUT, A3OUT2
118-
{OUTC(1,7,0), OUTC(1,3,0), OUTC(0,4,1), OUTC(0,0,1)}, // CTX30: B7OUT, B3OUT, A4OUT2, A0OUT2
119-
{OUTC(1,7,1), OUTC(0,6,0), OUTC(1,7,0), OUTC(1,3,1)}, // CTX31: B7OUT2, A6OUT, B7OUT, B3OUT2
87+
{
88+
{OUTC(0, 0, 0), OUTC(1, 2, 1), OUTC(0, 5, 1), OUTC(0, 6, 0)}, // CTX0: A0OUT, B2OUT2, A5OUT2, A6OUT
89+
{OUTC(0, 0, 1), OUTC(0, 0, 0), OUTC(0, 5, 0), OUTC(1, 7, 1)}, // CTX1: A0OUT2, A0OUT, A5OUT, B7OUT2
90+
{OUTC(1, 0, 0), OUTC(1, 1, 1), OUTC(1, 6, 1), OUTC(0, 7, 0)}, // CTX2: B0OUT, B1OUT2, B6OUT2, A7OUT
91+
{OUTC(1, 0, 1), OUTC(1, 0, 0), OUTC(0, 1, 0), OUTC(0, 6, 0)}, // CTX3: B0OUT2, B0OUT, A1OUT, A6OUT
92+
{OUTC(0, 1, 0), OUTC(0, 2, 1), OUTC(0, 5, 1), OUTC(1, 5, 0)}, // CTX4: A1OUT, A2OUT2, A5OUT2, B5OUT
93+
{OUTC(0, 1, 1), OUTC(0, 1, 0), OUTC(1, 6, 0), OUTC(0, 7, 0)}, // CTX5: A1OUT2, A1OUT, B6OUT, A7OUT
94+
{OUTC(1, 1, 0), OUTC(0, 1, 0), OUTC(1, 5, 1), OUTC(1, 7, 0)}, // CTX6: B1OUT, A1OUT, B5OUT2, B7OUT
95+
{OUTC(1, 1, 1), OUTC(1, 1, 0), OUTC(1, 5, 0), OUTC(0, 7, 0)}, // CTX7: B1OUT2, B1OUT, B5OUT, A7OUT
96+
{OUTC(0, 2, 0), OUTC(0, 3, 1), OUTC(0, 4, 1), OUTC(1, 6, 0)}, // CTX8: A2OUT, A3OUT2, A4OUT2, B6OUT
97+
{OUTC(0, 2, 1), OUTC(0, 2, 0), OUTC(0, 4, 0), OUTC(1, 0, 0)}, // CTX9: A2OUT2, A2OUT, A4OUT, B0OUT
98+
{OUTC(1, 2, 0), OUTC(1, 3, 1), OUTC(1, 4, 1), OUTC(0, 6, 0)}, // CTX10: B2OUT, B3OUT2, B4OUT2, A6OUT
99+
{OUTC(1, 2, 1), OUTC(1, 2, 0), OUTC(1, 4, 0), OUTC(1, 5, 1)}, // CTX11: B2OUT2, B2OUT, B4OUT, B5OUT2
100+
{OUTC(0, 3, 0), OUTC(1, 1, 0), OUTC(1, 0, 1), OUTC(1, 6, 1)}, // CTX12: A3OUT, B1OUT, B0OUT2, B6OUT2
101+
{OUTC(0, 3, 1), OUTC(0, 3, 0), OUTC(0, 6, 0), OUTC(1, 4, 1)}, // CTX13: A3OUT2, A3OUT, A6OUT, B4OUT2
102+
{OUTC(1, 3, 0), OUTC(1, 1, 0), OUTC(1, 7, 1), OUTC(0, 7, 0)}, // CTX14: B3OUT, B1OUT, B7OUT2, A7OUT
103+
{OUTC(1, 3, 1), OUTC(1, 3, 0), OUTC(0, 7, 0), OUTC(0, 4, 1)}, // CTX15: B3OUT2, B3OUT, A7OUT, A4OUT2
104+
{OUTC(0, 4, 0), OUTC(0, 0, 0), OUTC(0, 0, 1), OUTC(1, 3, 1)}, // CTX16: A4OUT, A0OUT, A0OUT2, B3OUT2
105+
{OUTC(0, 4, 1), OUTC(1, 7, 0), OUTC(0, 4, 0), OUTC(0, 1, 1)}, // CTX17: A4OUT2, B7OUT, A4OUT, A1OUT2
106+
{OUTC(1, 4, 0), OUTC(1, 0, 0), OUTC(0, 0, 0), OUTC(0, 3, 1)}, // CTX18: B4OUT, B0OUT, A0OUT, A3OUT2
107+
{OUTC(1, 4, 1), OUTC(0, 2, 0), OUTC(1, 4, 0), OUTC(1, 1, 1)}, // CTX19: B4OUT2, A2OUT, B4OUT, B1OUT2
108+
{OUTC(0, 5, 0), OUTC(0, 1, 0), OUTC(0, 1, 1), OUTC(1, 2, 1)}, // CTX20: A5OUT, A1OUT, A1OUT2, B2OUT2
109+
{OUTC(0, 5, 1), OUTC(0, 1, 0), OUTC(1, 5, 0), OUTC(0, 0, 1)}, // CTX21: A5OUT2, A1OUT, B5OUT, A0OUT2
110+
{OUTC(1, 5, 0), OUTC(0, 6, 0), OUTC(0, 1, 0), OUTC(0, 2, 1)}, // CTX22: B5OUT, A6OUT, A1OUT, A2OUT2
111+
{OUTC(1, 5, 1), OUTC(0, 7, 0), OUTC(0, 5, 0), OUTC(1, 0, 1)}, // CTX23: B5OUT2, A7OUT, A5OUT, B0OUT2
112+
{OUTC(0, 6, 0), OUTC(0, 2, 0), OUTC(0, 1, 0), OUTC(1, 1, 1)}, // CTX24: A6OUT, A2OUT, A1OUT, B1OUT2
113+
{OUTC(1, 4, 1), OUTC(1, 2, 0), OUTC(0, 6, 0), OUTC(0, 2, 1)}, // CTX25: B4OUT2, B2OUT, A6OUT, A2OUT2
114+
{OUTC(1, 6, 0), OUTC(1, 2, 0), OUTC(0, 5, 0), OUTC(0, 1, 1)}, // CTX26: B6OUT, B2OUT, A5OUT, A1OUT2
115+
{OUTC(1, 6, 1), OUTC(0, 1, 0), OUTC(1, 6, 0), OUTC(1, 2, 1)}, // CTX27: B6OUT2, A1OUT, B6OUT, B2OUT2
116+
{OUTC(0, 7, 0), OUTC(0, 3, 0), OUTC(0, 5, 1), OUTC(1, 0, 1)}, // CTX28: A7OUT, A3OUT, A5OUT2, B0OUT2
117+
{OUTC(1, 5, 1), OUTC(0, 1, 0), OUTC(0, 7, 0), OUTC(0, 3, 1)}, // CTX29: B5OUT2, A1OUT, A7OUT, A3OUT2
118+
{OUTC(1, 7, 0), OUTC(1, 3, 0), OUTC(0, 4, 1), OUTC(0, 0, 1)}, // CTX30: B7OUT, B3OUT, A4OUT2, A0OUT2
119+
{OUTC(1, 7, 1), OUTC(0, 6, 0), OUTC(1, 7, 0), OUTC(1, 3, 1)}, // CTX31: B7OUT2, A6OUT, B7OUT, B3OUT2
120120
};
121121

122-
uint16_t _analogBits = 10; //10-bit by default
123-
uint8_t _analogWriteBits = 8; // 8-bit by default for writes
124-
uint8_t _servoWriteBits = 8; // 8-bit by default for writes
122+
uint16_t _analogBits = 10; //10-bit by default
123+
uint8_t _analogWriteBits = 8; // 8-bit by default for writes
124+
uint8_t _servoWriteBits = 8; // 8-bit by default for writes
125125

126126
uint16_t analogRead(uint8_t pinNumber)
127127
{
@@ -325,92 +325,102 @@ ap3_err_t ap3_change_channel(uint8_t padNumber)
325325
}
326326
}
327327

328-
329-
330-
331-
332-
333-
334-
335-
336-
337-
ap3_err_t ap3_pwm_output( uint8_t pin, uint32_t th, uint32_t fw, uint32_t clk ){
328+
ap3_err_t ap3_pwm_output(uint8_t pin, uint32_t th, uint32_t fw, uint32_t clk)
329+
{
338330
// handle configuration, if necessary
339331
ap3_err_t retval = AP3_OK;
340332

341333
ap3_gpio_pad_t pad = ap3_gpio_pin2pad(pin);
342-
if(( pad == AP3_GPIO_PAD_UNUSED) || ( pad >= AP3_GPIO_MAX_PADS )){ return AP3_INVALID_ARG; }
334+
if ((pad == AP3_GPIO_PAD_UNUSED) || (pad >= AP3_GPIO_MAX_PADS))
335+
{
336+
return AP3_INVALID_ARG;
337+
}
343338

344339
uint32_t timer = 0;
345340
uint32_t segment = AM_HAL_CTIMER_TIMERA;
346341
uint32_t output = AM_HAL_CTIMER_OUTPUT_NORMAL;
347342

348343
uint8_t ctx = 0;
349-
for(ctx = 0; ctx < 32; ctx++){
350-
if( CTXPADNUM(ctx) == pad ){
344+
for (ctx = 0; ctx < 32; ctx++)
345+
{
346+
if (CTXPADNUM(ctx) == pad)
347+
{
351348
break;
352349
}
353350
}
354-
if( ctx >= 32 ){
351+
if (ctx >= 32)
352+
{
355353
return AP3_ERR; // could not find pad in CTx table
356354
}
357355
// Now use CTx index to get configuration information
358356

359357
// Now, for the given pad, determine the above values
360-
if( (pad == 39) || (pad == 37) ){
358+
if ((pad == 39) || (pad == 37))
359+
{
361360
// pads 39 and 37 must be handled differently to avoid conflicting with other pins
362-
if(pad == 39){
361+
if (pad == 39)
362+
{
363363
// 39
364364
timer = 6;
365365
segment = AM_HAL_CTIMER_TIMERA;
366366
output = AM_HAL_CTIMER_OUTPUT_SECONDARY;
367-
}else{
367+
}
368+
else
369+
{
368370
// 37
369371
timer = 7;
370372
segment = AM_HAL_CTIMER_TIMERA;
371373
output = AM_HAL_CTIMER_OUTPUT_NORMAL;
372374
}
373-
}else{
374-
const uint8_t n = 0; // use the zeroeth index into the options for any pd except 37 and 39
375+
}
376+
else
377+
{
378+
const uint8_t n = 0; // use the zeroeth index into the options for any pd except 37 and 39
375379

376380
timer = OUTCTIMN(ctx, 0);
377-
if( OUTCTIMB(ctx, 0) ){
381+
if (OUTCTIMB(ctx, 0))
382+
{
378383
segment = AM_HAL_CTIMER_TIMERB;
379384
}
380-
if( OUTCO2(ctx, 0) ){
385+
if (OUTCO2(ctx, 0))
386+
{
381387
output = AM_HAL_CTIMER_OUTPUT_SECONDARY;
382388
}
383389
}
384390

385391
// Configure the pin
386-
am_hal_ctimer_output_config(timer,
387-
segment,
388-
pad,
389-
output,
390-
AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA); //
392+
am_hal_ctimer_output_config(timer,
393+
segment,
394+
pad,
395+
output,
396+
AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA); //
391397

392398
// Configure the repeated pulse mode with our clock source
393399
am_hal_ctimer_config_single(timer,
394-
segment,
400+
segment,
395401
// (AM_HAL_CTIMER_FN_PWM_REPEAT | AP3_ANALOG_CLK | AM_HAL_CTIMER_INT_ENABLE) );
396-
(AM_HAL_CTIMER_FN_PWM_REPEAT | clk) );
402+
(AM_HAL_CTIMER_FN_PWM_REPEAT | clk));
397403

398404
// If this pad uses secondary output:
399-
if( output == AM_HAL_CTIMER_OUTPUT_SECONDARY ){
405+
if (output == AM_HAL_CTIMER_OUTPUT_SECONDARY)
406+
{
400407
// Need to explicitly enable compare registers 2/3
401-
uint32_t* pui32ConfigReg = NULL;
402-
pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, timer, AUX0);
408+
uint32_t *pui32ConfigReg = NULL;
409+
pui32ConfigReg = (uint32_t *)CTIMERADDRn(CTIMER, timer, AUX0);
403410
uint32_t ui32WriteVal = AM_REGVAL(pui32ConfigReg);
404-
uint32_t ui32ConfigVal = (1 << CTIMER_AUX0_TMRA0EN23_Pos ); // using CTIMER_AUX0_TMRA0EN23_Pos because for now this number is common to all CTimer instances
405-
if ( segment == AM_HAL_CTIMER_TIMERB ){
411+
uint32_t ui32ConfigVal = (1 << CTIMER_AUX0_TMRA0EN23_Pos); // using CTIMER_AUX0_TMRA0EN23_Pos because for now this number is common to all CTimer instances
412+
if (segment == AM_HAL_CTIMER_TIMERB)
413+
{
406414
ui32ConfigVal = ((ui32ConfigVal & 0xFFFF) << 16);
407415
}
408416
ui32WriteVal = (ui32WriteVal & ~(segment)) | ui32ConfigVal;
409417
AM_REGVAL(pui32ConfigReg) = ui32WriteVal;
410418

411419
// then set the duty cycle with the 'aux' function
412-
am_hal_ctimer_aux_period_set( timer, segment, fw, th);
413-
}else{
420+
am_hal_ctimer_aux_period_set(timer, segment, fw, th);
421+
}
422+
else
423+
{
414424
// Otherwise simply set the primary duty cycle
415425
am_hal_ctimer_period_set(timer, segment, fw, th);
416426
}
@@ -423,58 +433,58 @@ ap3_err_t ap3_pwm_output( uint8_t pin, uint32_t th, uint32_t fw, uint32_t clk ){
423433
return AP3_OK;
424434
}
425435

426-
427-
ap3_err_t analogWriteResolution( uint8_t res ){
428-
if( res > 15 ){
436+
ap3_err_t analogWriteResolution(uint8_t res)
437+
{
438+
if (res > 15)
439+
{
429440
_analogWriteBits = 15; // max out the resolution when this happens
430441
return AP3_ERR;
431442
}
432443
_analogWriteBits = res;
433444
return AP3_OK;
434445
}
435446

436-
ap3_err_t analogWrite( uint8_t pin, uint32_t val ){
447+
ap3_err_t analogWrite(uint8_t pin, uint32_t val)
448+
{
437449
// Determine the high time based on input value and the current resolution setting
438-
uint32_t fsv = (0x01 << _analogWriteBits); // full scale value for the current resolution setting
439-
val = val % fsv; // prevent excess
440-
uint32_t clk = AM_HAL_CTIMER_HFRC_12MHZ; // Use an Ambiq HAL provided value to select which clock
450+
uint32_t fsv = (0x01 << _analogWriteBits); // full scale value for the current resolution setting
451+
val = val % fsv; // prevent excess
452+
uint32_t clk = AM_HAL_CTIMER_HFRC_12MHZ; // Use an Ambiq HAL provided value to select which clock
441453
//uint32_t fw = 32768; // Choose the frame width in clock periods (32768 -> ~ 350 Hz)
442454
// uint32_t th = (uint32_t)( (fw * val) / fsv );
443455

444-
if(val == 0){
445-
val = 1; // todo: change this so that when val==0 we set the mode to "force output low"
456+
if (val == 0)
457+
{
458+
val = 1; // todo: change this so that when val==0 we set the mode to "force output low"
446459
}
447-
if( val == fsv ){
448-
val -= 1; // todo: change this so that when val==fsv we just set the mode to "force output high"
460+
if (val == fsv)
461+
{
462+
val -= 1; // todo: change this so that when val==fsv we just set the mode to "force output high"
449463
}
450-
return ap3_pwm_output( pin, val, fsv, clk );
464+
return ap3_pwm_output(pin, val, fsv, clk);
451465
}
452466

453-
ap3_err_t servoWriteResolution( uint8_t res ){
454-
if( res > 15 ){
467+
ap3_err_t servoWriteResolution(uint8_t res)
468+
{
469+
if (res > 15)
470+
{
455471
_servoWriteBits = 15; // max out the resolution when this happens
456472
return AP3_ERR;
457473
}
458474
_servoWriteBits = res;
459475
return AP3_OK;
460476
}
461477

462-
ap3_err_t servoWrite( uint8_t pin, uint32_t val ){
478+
ap3_err_t servoWrite(uint8_t pin, uint32_t val)
479+
{
463480
// Determine the high time based on input value and the current resolution setting
464-
uint32_t fsv = (0x01 << _servoWriteBits); // full scale value for the current resolution setting
465-
val = val % fsv; // prevent excess
466-
uint32_t clk = AM_HAL_CTIMER_HFRC_3MHZ; // Using 3 MHz to get fine-grained control up to 20 ms wide
467-
uint32_t fw = 60000; // 20 ms wide frame
468-
uint32_t max = 6000; // max width of RC pwm pulse is 2 ms or 6000 counts
469-
uint32_t min = 3000; // min width of RC pwm pulse is 1 ms or 3000 counts
470-
uint32_t th = (uint32_t)( ((max - min) * val) / fsv ) + min;
471-
472-
return ap3_pwm_output( pin, th, fw, clk );
481+
uint32_t fsv = (0x01 << _servoWriteBits); // full scale value for the current resolution setting
482+
val = val % fsv; // prevent excess
483+
uint32_t clk = AM_HAL_CTIMER_HFRC_3MHZ; // Using 3 MHz to get fine-grained control up to 20 ms wide
484+
uint32_t fw = 60000; // 20 ms wide frame
485+
uint32_t max = 6000; // max width of RC pwm pulse is 2 ms or 6000 counts
486+
uint32_t min = 3000; // min width of RC pwm pulse is 1 ms or 3000 counts
487+
uint32_t th = (uint32_t)(((max - min) * val) / fsv) + min;
488+
489+
return ap3_pwm_output(pin, th, fw, clk);
473490
}
474-
475-
476-
477-
478-
479-
480-

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