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Pare down interrupt enable/disable function
I'm using Git for file transfer.... this is not standard but it works alright (except for preserving ugly intermediate steps forever haha)
1 parent f0b0318 commit c64f697

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2 files changed

+71
-265
lines changed

2 files changed

+71
-265
lines changed

‎cores/arduino/ard_sup/ap3_gpio.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -53,8 +53,8 @@ extern ap3_gpio_pad_t ap3_gpio_pin2pad(ap3_gpio_pin_t pin);
5353
inline bool ap3_gpio_is_valid(ap3_gpio_pad_t pad){ return AP3_GPIO_IS_VALID(pad); }
5454
inline bool ap3_gpio_has_gpio(ap3_gpio_pad_t pad){ return AP3_GPIO_IS_VALID(pad); }
5555

56-
// Frankenstein HAL GPIO config OR function
57-
uint32_t ap3_gpio_pinconfig_ORnot(uint32_t ui32Pin, am_hal_gpio_pincfg_t bfGpioCfg, bool ORnot);
56+
// Interrupt enable/disable function
57+
uint32_t ap3_gpio_enable_interrupts(uint32_t ui32Pin, bool enable);
5858

5959
void padMode(uint8_t pad, am_hal_gpio_pincfg_t mode);
6060
void padMode(uint8_t pad, am_hal_gpio_pincfg_t mode, ap3_err_t* retval);

‎cores/arduino/ard_sup/gpio/ap3_gpio.cpp

Lines changed: 69 additions & 263 deletions
Original file line numberDiff line numberDiff line change
@@ -236,270 +236,76 @@ extern void detachInterrupt(uint8_t pin)
236236

237237

238238

239-
uint32_t ap3_gpio_pinconfig_ORnot(uint32_t ui32Pin, am_hal_gpio_pincfg_t bfGpioCfg, bool ORnot)
239+
uint32_t ap3_gpio_enable_interrupts(uint32_t ui32Pin, bool enable)
240240
{
241-
// uint32_t ui32Padreg, ui32AltPadCfg, ui32GPCfg;
242-
// uint32_t ui32Funcsel, ui32PowerSw;
243-
// bool bClearEnable = false;
244-
245-
// #ifndef AM_HAL_DISABLE_API_VALIDATION
246-
// if (ui32Pin >= AM_HAL_GPIO_MAX_PADS)
247-
// {
248-
// return AM_HAL_STATUS_INVALID_ARG;
249-
// }
250-
// #endif // AM_HAL_DISABLE_API_VALIDATION
251-
252-
// //
253-
// // Initialize the PADREG accumulator variables.
254-
// //
255-
// ui32GPCfg = ui32Padreg = ui32AltPadCfg = 0;
256-
257-
// //
258-
// // Get the requested function and/or power switch.
259-
// //
260-
// ui32Funcsel = bfGpioCfg.uFuncSel;
261-
// ui32PowerSw = bfGpioCfg.ePowerSw;
262-
263-
// ui32Padreg |= ui32Funcsel << PADREG_FLD_FNSEL_S;
264-
265-
// //
266-
// // Check for invalid configuration requests.
267-
// //
268-
// if (bfGpioCfg.ePullup != AM_HAL_GPIO_PIN_PULLUP_NONE)
269-
// {
270-
// //
271-
// // This setting is needed for all pullup settings including
272-
// // AM_HAL_GPIO_PIN_PULLUP_WEAK and AM_HAL_GPIO_PIN_PULLDOWN.
273-
// //
274-
// ui32Padreg |= (0x1 << PADREG_FLD_PULLUP_S);
275-
276-
// //
277-
// // Check for specific pullup or pulldown settings.
278-
// //
279-
// if ((bfGpioCfg.ePullup >= AM_HAL_GPIO_PIN_PULLUP_1_5K) &&
280-
// (bfGpioCfg.ePullup <= AM_HAL_GPIO_PIN_PULLUP_24K))
281-
// {
282-
// ui32Padreg |= ((bfGpioCfg.ePullup - AM_HAL_GPIO_PIN_PULLUP_1_5K) << PADREG_FLD_76_S);
283-
// #ifndef AM_HAL_DISABLE_API_VALIDATION
284-
// if (!(g_ui8Bit76Capabilities[ui32Pin] & CAP_PUP))
285-
// {
286-
// return AM_HAL_GPIO_ERR_PULLUP;
287-
// }
288-
// }
289-
// else if (bfGpioCfg.ePullup == AM_HAL_GPIO_PIN_PULLDOWN)
290-
// {
291-
// if (ui32Pin != 20)
292-
// {
293-
// return AM_HAL_GPIO_ERR_PULLDOWN;
294-
// }
295-
// }
296-
// else if (bfGpioCfg.ePullup != AM_HAL_GPIO_PIN_PULLUP_WEAK)
297-
// {
298-
// if ((g_ui8Bit76Capabilities[ui32Pin] & (CAP_PUP | CAP_PDN)) == 0)
299-
// {
300-
// return AM_HAL_GPIO_ERR_PULLUP;
301-
// }
302-
// #endif // AM_HAL_DISABLE_API_VALIDATION
303-
// }
304-
// }
305-
306-
// //
307-
// // Check if requesting a power switch pin
308-
// //
309-
// if (ui32PowerSw != AM_HAL_GPIO_PIN_POWERSW_NONE)
310-
// {
311-
// if ((ui32PowerSw == AM_HAL_GPIO_PIN_POWERSW_VDD) &&
312-
// (g_ui8Bit76Capabilities[ui32Pin] & CAP_VDD))
313-
// {
314-
// ui32Padreg |= 0x1 << PADREG_FLD_76_S;
315-
// }
316-
// else if ((ui32PowerSw == AM_HAL_GPIO_PIN_POWERSW_VSS) &&
317-
// (g_ui8Bit76Capabilities[ui32Pin] & CAP_VSS))
318-
// {
319-
// ui32Padreg |= 0x2 << PADREG_FLD_76_S;
320-
// }
321-
// else
322-
// {
323-
// return AM_HAL_GPIO_ERR_PWRSW;
324-
// }
325-
// }
326-
327-
// //
328-
// // Depending on the selected pin and FNSEL, determine if INPEN needs to be set.
329-
// //
330-
// ui32Padreg |= (g_ui8Inpen[ui32Pin] & (1 << ui32Funcsel)) ? (1 << PADREG_FLD_INPEN_S) : 0;
331-
332-
// //
333-
// // Configure ui32GpCfg based on whether nCE requested.
334-
// //
335-
// if (g_ui8nCEpins[ui32Pin] == ui32Funcsel)
336-
// {
337-
// uint32_t ui32Outcfg;
338-
// uint8_t ui8CEtbl;
339-
340-
// #ifndef AM_HAL_DISABLE_API_VALIDATION
341-
// //
342-
// // User is configuring a nCE. Verify the requested settings and set the
343-
// // polarity and OUTCFG values (INCFG is not used here and should be 0).
344-
// // Valid uNCE values are 0-3 (uNCE is a 2-bit field).
345-
// // Valid uIOMnum are 0-6 (0-5 for IOMs, 6 for MSPI, 7 is invalid).
346-
// //
347-
// if (bfGpioCfg.uIOMnum > IOMNUM_MAX)
348-
// {
349-
// return AM_HAL_GPIO_ERR_INVCE; // Invalid CE specified
350-
// }
351-
// #endif // AM_HAL_DISABLE_API_VALIDATION
352-
353-
// //
354-
// // Construct the entry we expect to find in the table. We can determine
355-
// // the OUTCFG value by looking for that value in the pin row.
356-
// //
357-
// ui8CEtbl = (bfGpioCfg.uIOMnum << 4) | bfGpioCfg.uNCE;
358-
// for (ui32Outcfg = 0; ui32Outcfg < 4; ui32Outcfg++)
359-
// {
360-
// if (g_ui8NCEtable[ui32Pin][ui32Outcfg] == ui8CEtbl)
361-
// {
362-
// break;
363-
// }
364-
// }
365-
366-
// #ifndef AM_HAL_DISABLE_API_VALIDATION
367-
// if (ui32Outcfg >= 4)
368-
// {
369-
// return AM_HAL_GPIO_ERR_INVCEPIN;
370-
// }
371-
// #endif // AM_HAL_DISABLE_API_VALIDATION
372-
373-
// ui32GPCfg |= (ui32Outcfg << GPIOCFG_FLD_OUTCFG_S) |
374-
// (bfGpioCfg.eCEpol << GPIOCFG_FLD_INTD_S) |
375-
// (0 << GPIOCFG_FLD_INCFG_S);
376-
// }
377-
// else
378-
// {
379-
// //
380-
// // It's not nCE, it's one of the other funcsels.
381-
// // Start by setting the value of the requested GPIO input.
382-
// //
383-
// ui32Padreg |= (bfGpioCfg.eGPInput << PADREG_FLD_INPEN_S);
384-
385-
// //
386-
// // Map the requested interrupt direction settings into the Apollo3
387-
// // GPIOCFG register field, which is a 4-bit field:
388-
// // [INTD(1):OUTCFG(2):INCFG(1)].
389-
// // Bit0 of eIntDir maps to GPIOCFG.INTD (b3).
390-
// // Bit1 of eIntDir maps to GPIOCFG.INCFG (b0).
391-
// //
392-
// ui32GPCfg |= (bfGpioCfg.eGPOutcfg << GPIOCFG_FLD_OUTCFG_S) |
393-
// (((bfGpioCfg.eIntDir >> 0) & 0x1) << GPIOCFG_FLD_INTD_S) |
394-
// (((bfGpioCfg.eIntDir >> 1) & 0x1) << GPIOCFG_FLD_INCFG_S);
395-
396-
// if ((bfGpioCfg.eGPOutcfg == AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL) ||
397-
// pincfg_equ(&bfGpioCfg, (void *)&g_AM_HAL_GPIO_DISABLE))
398-
// {
399-
// //
400-
// // For pushpull configurations, we must be sure to clear the ENABLE
401-
// // bit. In pushpull, these bits turn on FAST GPIO. For regular
402-
// // GPIO, they must be clear.
403-
// //
404-
// bClearEnable = true;
405-
// }
406-
407-
// //
408-
// // There is some overlap between eGPRdZero and eIntDir as both settings
409-
// // utilize the overloaded INCFG bit.
410-
// // Therefore the two fields should be used in a mutually exclusive
411-
// // manner. For flexibility however they are not disallowed because
412-
// // their functionality is dependent on FUNCSEL and whether interrupts
413-
// // are used.
414-
// //
415-
// // In the vein of mutual exclusion, eGPRdZero is primarily intended for
416-
// // use when GPIO interrupts are not in use and can be used when no
417-
// // eIntDir setting is provided.
418-
// // If eIntDir is provided, eGPRdZero is ignored and can only be
419-
// // achieved via the AM_HAL_GPIO_PIN_INTDIR_NONE setting.
420-
// //
421-
// if (bfGpioCfg.eIntDir == 0)
422-
// {
423-
// ui32GPCfg &= ~(1 << GPIOCFG_FLD_INCFG_S);
424-
// ui32GPCfg |= (bfGpioCfg.eGPRdZero << GPIOCFG_FLD_INCFG_S);
425-
// }
426-
// }
427-
428-
// switch (bfGpioCfg.eDriveStrength)
429-
// {
430-
// // DRIVESTRENGTH is a 2-bit field.
431-
// // bit0 maps to bit2 of a PADREG field.
432-
// // bit1 maps to bit0 of an ALTPADCFG field.
433-
// case AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA:
434-
// ui32Padreg |= (0 << PADREG_FLD_DRVSTR_S);
435-
// ui32AltPadCfg |= (0 << 0);
436-
// break;
437-
// case AM_HAL_GPIO_PIN_DRIVESTRENGTH_4MA:
438-
// ui32Padreg |= (1 << PADREG_FLD_DRVSTR_S);
439-
// ui32AltPadCfg |= (0 << 0);
440-
// break;
441-
// case AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA:
442-
// ui32Padreg |= (0 << PADREG_FLD_DRVSTR_S);
443-
// ui32AltPadCfg |= (1 << 0);
444-
// break;
445-
// case AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA:
446-
// ui32Padreg |= (1 << PADREG_FLD_DRVSTR_S);
447-
// ui32AltPadCfg |= (1 << 0);
448-
// break;
449-
// }
450-
451-
// //
452-
// // At this point, the 3 configuration variables, ui32GpioCfg, ui32Padreg,
453-
// // and ui32AltPadCfg values are set (at bit position 0) and ready to write
454-
// // to their respective register bitfields.
455-
// //
456-
// uint32_t ui32GPCfgAddr, ui32PadregAddr, ui32AltpadAddr;
457-
// uint32_t ui32GPCfgClearMask, ui32PadClearMask;
458-
// uint32_t ui32GPCfgShft, ui32PadShft;
459-
460-
// ui32GPCfgAddr = AM_REGADDR(GPIO, CFGA) + ((ui32Pin >> 1) & ~0x3);
461-
// ui32PadregAddr = AM_REGADDR(GPIO, PADREGA) + (ui32Pin & ~0x3);
462-
// ui32AltpadAddr = AM_REGADDR(GPIO, ALTPADCFGA) + (ui32Pin & ~0x3);
463-
464-
// ui32GPCfgShft = ((ui32Pin & 0x7) << 2);
465-
// ui32PadShft = ((ui32Pin & 0x3) << 3);
466-
// ui32GPCfgClearMask = ~((uint32_t)0xF << ui32GPCfgShft);
467-
// ui32PadClearMask = ~((uint32_t)0xFF << ui32PadShft);
468-
469-
// //
470-
// // Get the new values into their rightful bit positions.
471-
// //
472-
// ui32Padreg <<= ui32PadShft;
473-
// ui32AltPadCfg <<= ui32PadShft;
474-
// ui32GPCfg <<= ui32GPCfgShft;
475-
476-
// AM_CRITICAL_BEGIN
477-
478-
// if (bClearEnable)
479-
// {
480-
// //
481-
// // We're configuring a mode that requires clearing the Enable bit.
482-
// //
483-
// am_hal_gpio_output_tristate_disable(ui32Pin);
484-
// }
485-
486-
// GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key;
487-
488-
// // Here's where the magic happens
489-
// if(ORnot){
490-
// AM_REGVAL(ui32PadregAddr) = (AM_REGVAL(ui32PadregAddr) & ui32PadClearMask) | ui32Padreg;
491-
// AM_REGVAL(ui32GPCfgAddr) = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgClearMask) | ui32GPCfg;
492-
// AM_REGVAL(ui32AltpadAddr) = (AM_REGVAL(ui32AltpadAddr) & ui32PadClearMask) | ui32AltPadCfg;
493-
// }else{
494-
// AM_REGVAL(ui32PadregAddr) = (AM_REGVAL(ui32PadregAddr) & ui32PadClearMask) & ~ui32Padreg;
495-
// AM_REGVAL(ui32GPCfgAddr) = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgClearMask) & ~ui32GPCfg;
496-
// AM_REGVAL(ui32AltpadAddr) = (AM_REGVAL(ui32AltpadAddr) & ui32PadClearMask) & ~ui32AltPadCfg;
497-
// }
498-
499-
500-
// GPIO->PADKEY = 0;
501-
502-
// AM_CRITICAL_END
241+
uint32_t ui32Padreg, ui32AltPadCfg, ui32GPCfg;
242+
uint32_t ui32Funcsel, ui32PowerSw;
243+
bool bClearEnable = false;
244+
245+
#ifndef AM_HAL_DISABLE_API_VALIDATION
246+
if (ui32Pin >= AM_HAL_GPIO_MAX_PADS)
247+
{
248+
return AM_HAL_STATUS_INVALID_ARG;
249+
}
250+
#endif // AM_HAL_DISABLE_API_VALIDATION
251+
252+
//
253+
// Initialize the PADREG accumulator variables.
254+
//
255+
ui32GPCfg = ui32Padreg = ui32AltPadCfg = 0;
256+
257+
258+
//
259+
// Map the requested interrupt direction settings into the Apollo3
260+
// GPIOCFG register field, which is a 4-bit field:
261+
// [INTD(1):OUTCFG(2):INCFG(1)].
262+
// Bit0 of eIntDir maps to GPIOCFG.INTD (b3).
263+
// Bit1 of eIntDir maps to GPIOCFG.INCFG (b0).
264+
//
265+
ui32GPCfg |= (((bfGpioCfg.eIntDir >> 0) & 0x1) << GPIOCFG_FLD_INTD_S) | (((bfGpioCfg.eIntDir >> 1) & 0x1) << GPIOCFG_FLD_INCFG_S);
266+
267+
268+
//
269+
// At this point, the configuration variable, ui32GpioCfg
270+
// value is set (at bit position 0) and ready to write
271+
// to their respective register bitfields.
272+
//
273+
uint32_t ui32GPCfgAddr;
274+
uint32_t ui32GPCfgClearMask;
275+
uint32_t ui32GPCfgShft;
276+
277+
ui32GPCfgAddr = AM_REGADDR(GPIO, CFGA) + ((ui32Pin >> 1) & ~0x3);
278+
279+
ui32GPCfgClearMask = ~((uint32_t)0xF << ui32GPCfgShft);
280+
281+
//
282+
// Get the new values into their rightful bit positions.
283+
//
284+
ui32GPCfg <<= ui32GPCfgShft;
285+
286+
AM_CRITICAL_BEGIN
287+
288+
if (bClearEnable)
289+
{
290+
//
291+
// We're configuring a mode that requires clearing the Enable bit.
292+
//
293+
am_hal_gpio_output_tristate_disable(ui32Pin);
294+
}
295+
296+
GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key;
297+
298+
// Here's where the magic happens
299+
if(ORnot){
300+
AM_REGVAL(ui32GPCfgAddr) = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgClearMask) | ui32GPCfg;
301+
}else{
302+
AM_REGVAL(ui32GPCfgAddr) = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgClearMask) & ~ui32GPCfg;
303+
}
304+
305+
306+
GPIO->PADKEY = 0;
307+
308+
AM_CRITICAL_END
503309

504310
return AM_HAL_STATUS_SUCCESS;
505311

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